Datasheet UDA1330ATS Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UDA1330ATS

Low-cost stereo filter DAC

Product specification
Supersedes data of 2000 April 18
File under Integrated Circuits, IC01

2001 Feb 02

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

FEATURES
General

• Low power consumption

• Power supply voltage from 2.7 to 5.5 V

• Selectable controlvia L3 microcontroller interface or via

static pin control

• System clock frequencies of 256fs, 384fsand 512f
selectable via L3 interface or 256fsand 384fs via static
pin control

• Supports sampling frequencies (fs) from 8 to 55 kHz

• Integrated digital filter plus non inverting

Digital-to-Analog Converter (DAC)

• No analog post filtering required for DAC

• Slave mode only applications

• Easy application

• Small package size (SSOP16)

• TTL tolerant input pads

• Pin and function compatible with the UDA1320ATS.

Multiple format input interface

• L3 mode: I2S-bus, MSB-justified or LSB-justified
16, 18 and 20 bits format compatible

• Static pin mode: I2S-bus and LSB-justified
16, 18 and 20 bits format compatible

• 1fsinput format data rate.

DAC digital sound processing

• Digital logarithmic volume control in L3 mode

• Digital de-emphasis for 32, 44.1 and 48 kHz sampling

frequenciesinL3 mode or 44.1 kHz sampling frequency
in static pin mode

• Soft mute control both in static pin mode and L3 mode.

s

APPLICATIONS

• PC audio applications

• Car radio applications.

GENERAL DESCRIPTION

The UDA1330ATS is a single-chip stereo DAC employing
bitstream conversion techniques.

The UDA1330ATS supports the I2S-bus data format with
wordlengths of upto20 bits, the MSB-justified dataformat
with word lengths of up to 20 bits and the LSB-justified
serial data format with word lengths of 16, 18 and 20 bits.

The UDA1330ATS canbe used in two modes: L3 mode or
the static pin mode.

In the L3 mode, all digital sound processing features must
becontrolled via the L3 interface, includingtheselectionof
the system clock setting.

In the two static modes, the UDA1330ATS can be
operated in the 256fsand 384fs system clock mode.
Muting, de-emphasis for 44.1 kHz and four digital input
formats (I2S-bus or LSB-justified 16, 18, and 20 bits) can
be selected via static pins. The L3 interface cannot be
used in this application mode, so volume control is not
available in this mode.

Advanced audio configuration

• Stereo line output (volume control in L3 mode)

• High linearity, wide dynamic range and low distortion.

ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

UDA1330ATS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

2001 Feb 02 2

PACKAGE

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

V

DDD

I

DDA

I

DDD

T

amb

Digital-to-analog converter (V

V

o(rms)

(THD + N)/S total harmonic distortion-plus-noise to

S/N signal-to-noise ratio code = 0; A-weighted − 100 95 dB

α

cs

Digital-to-analog converter (V

V

o(rms)

(THD + N)/S total harmonic distortion-plus-noise to

S/N signal-to-noise ratio code = 0; A-weighted − 100 − dB

α

cs

Power dissipation

P power dissipation playback mode

DAC analog supply voltage 2.7 5.0 5.5 V
digital supply voltage 2.7 5.0 5.5 V
DAC analog supply current V

DDA

= 5.0 V
operating − 9.5 − mA
power-down − 400 −µA

V

= 3.3 V

DDA

operating − 7.0 − mA
power-down − 250 −µA

digital supply current V

= 5.0 V − 5.5 − mA

DDD

V

= 3.3 V − 3.0 − mA

DDD

ambient temperature −40 − +85 °C

DDA=VDDD

= 5.0 V)

output voltage (RMS value) note 1 − 1.45 − V

at 0 dB −−90 −85 dB

signal ratio

at −60 dB; A-weighted −−40 −35 dB

channel separation − 100 − dB

DDA=VDDD

= 3.3 V)

output voltage (RMS value) note 1 − 1.0 − V

at 0 dB −−85 − dB

signal ratio

at −60 dB; A-weighted −−38 − dB

channel separation − 100 − dB

V

DDA=VDDD

V

DDA=VDDD

= 5.0 V − 75 − mW
= 3.3 V − 33 − mW

Note

1. The output voltage scales linearly with the power supply voltage.

2001 Feb 02 3

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

BLOCK DIAGRAM

handbook, full pagewidth

BCK

WS

DATAI

SYSCLK

VOUTL

V

DDD

4

1
2
3

UDA1330ATS

6

14

13 12

V

DDA

DIGITAL INTERFACE

VOLUME/MUTE/DE-EMPHASIS

INTERPOLATION FILTER

NOISE SHAPER

DAC

15

V

SSA

Fig.1 Block diagram.

Fig.0 Block diagram.

V

DAC

SSD

5

CONTROL

INTERFACE

V

ref(DAC)

7

APPSEL

11

APPL0

10

APPL1

9

APPL2

8

APPL3

16

VOUTR

MGL401

PINNING

SYMBOL PIN DESCRIPTION

BCK 1 bit clock input
WS 2 word select input
DATAI 3 data input
V

DDD

V

SSD

SYSCLK 6 system clock input: 256f

4 digital supply voltage
5 digital ground

and 512f

s

, 384f

s

APPSEL 7 application mode select input
APPL3 8 application input 3
APPL2 9 application input 2
APPL1 10 application input 1
APPL0 11 application input 0
V

ref(DAC)

V

DDA

12 DAC reference voltage

13 analog supply voltage for DAC
VOUTL 14 left channel output
V

SSA

15 analog ground
VOUTR 16 right channel output

handbook, halfpage

s

WS

DATAI

V

DDD

V

SSD

1
2
3
4

UDA1330ATS

5
6
7
8

MGL402

16
15
14
13
12
11
10

9

VOUTRBCK
V

SSA

VOUTL
V

DDA

V

ref(DAC)

APPL0SYSCLK
APPL1APPSEL
APPL2APPL3

Fig.2 Pin configuration.

2001 Feb 02 4

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

FUNCTIONAL DESCRIPTION
System clock

The UDA1330ATS operates in slave mode only.
Therefore, in all applications the system devices must
provide the system clock. The system frequency (f

sys

) is
selectable and depends on the application mode. The
options are: 256fs, 384fsand 512fs for the L3 mode and
256fsor 384fs for the static pin mode. The system clock
must be locked in frequency to the digital interface input
signals.

The UDA1330ATS supports sampling frequencies from
8 to 55 kHz.

Application modes

The application mode can be set with the three-level
pin APPSEL (see Table 1):

• L3 mode

• Static pin mode with f

• Static pin mode with f

sys
sys

= 384f
= 256fs.

s

Table 1 Selecting application mode and system clock

frequency via pin APPSEL

In the L3 mode, pin APPL0 must be set to LOW. It should
be noted that when the L3 mode is used, an initialization
must be performed when the IC is powered-up.

Multiple format input interface

D

ATA FORMATS

Thedigitalinterface of the UDA1330ATS supportsmultiple
format inputs (see Fig.3).

Left and right data-channel words are time multiplexed.
The WS signal must have a 50% duty factor for all

LSB-justified formats.
The BCK clock can be up to 64fs, or in other words the

BCK frequency is 64 times the Word Select (WS)
frequency or less: f

≤ 64 × fWS.

BCK

Important: the WS edge MUST fall on the negative edge
of the BCK at all times for proper operation of the digital
interface.

The UDA1330ATS also accepts double speed data for
double speed data monitoring purposes

L3 MODE

VOLTAGE ON

PIN APPSEL

V

SSD

0.5V

DDD

V

DDD

MODE f

sys

L3 mode 256fs, 384fsor 512f

static pin mode

384f
256f

s
s

The function of an application input pin (active HIGH)
depends on the application mode (see Table 2).

Table 2 Functions of application input pins

FUNCTION

PIN

L3 MODE STATIC PIN MODE

APPL0 TEST MUTE
APPL1 L3CLOCK DEEM
APPL2 L3MODE SF0
APPL3 L3DATA SF1

For example, in the static pin mode the output signal can
be soft muted by setting pin APPL0 to HIGH.
De-emphasis can be switched on for 44.1 kHz by setting
pin APPL1to HIGH; setting pin APPL1to LOW will disable
de-emphasis.

This mode supports the following input formats:

• I2S-bus format with data word length of up to 20 bits

s

• MSB-justified format with data word length up to 20 bits

• LSB-justified format with data word length of

16, 18 or 20 bits.

STATIC PIN MODE
This mode supports the following input formats:

• I2S-bus format with data word length of up to 20 bits

• LSB-justified format with data word length of

16, 18 or 20 bits.

These four formats are selectable via the static pin codes
SF0 and SF1 (see Table 3).

Table 3 Input format selection using SF0 and SF1

FORMAT SF0 SF1

2

I

S-bus 0 0
LSB-justified 16 bits 0 1
LSB-justified 18 bits 1 0
LSB-justified 20 bits 1 1

2001 Feb 02 5

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

Interpolation filter (DAC)

Thedigital filter interpolates from1fsto 128fsbycascading
a recursive filter and an FIR filter (see Table 4).

Table 4 Interpolation filter characteristics

ITEM CONDITION VALUE (dB)

Pass-band ripple 0 to 0.45f
Stop band >0.55f
Dynamic range 0 to 0.45f

s

s

s

±0.1

−50

108

Noise shaper

The 3rd-order noise shaper operates at 128f

. It shifts

s

in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a Filter
Stream DAC (FSDAC).

Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.

The output voltage of the FSDAC scales linearly with the
power supply voltage.

Pin compatibility

In the L3 mode the UDA1330ATS can be used on boards
that are designed for the UDA1320ATS.

Remark: It should be noted that the UDA1330ATS is
designed for 5 V operation while the UDA1320ATS is
designed for 3 V operation. This means that the
UDA1330ATS can be used with the UDA1320ATS supply
voltage range, but the UDA1320ATS can not beused with
the 5 V supply voltage.

2001 Feb 02 6

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2001 Feb 02 7

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Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

LEFT

LEFT

2

I

MSB-JUSTIFIED FORMAT

LEFT

LEFT

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

MSB B2

MSB B2 MSBLSB LSB MSB B2B2

RIGHT

3

21> = 812 3

MSB MSBB2

S-BUS FORMAT

RIGHT

> = 8 > = 8

MSB B2 B3 B4

321321

16

15 2 1

MSB

B2

16

1518 17 2 1

> = 8

B15

LSB

LSB-JUSTIFIED FORMAT 16 BITS

B17

LSB

LSB-JUSTIFIED FORMAT 18 BITS

RIGHT

RIGHT

16

MSB B2

16 1518 17 2 1

MSB B2 B3 B4

15 2 1

B15 LSB

B17 LSB

WS

BCK

DATA

LEFT

16

MSB B2 B3 B4 B5 B6

Fig.3 Digital interface input format data format.Fig.0 Digital interface input format data format.

1518 1720 19 2 1

B19

LSB

LSB-JUSTIFIED FORMAT 20 BITS

RIGHT

16

MSB B2 B3 B4 B5 B6

1518 1720 19 2 1

B19 LSB

MBL140

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

L3 INTERFACE

The following system and digital sound processing
features can be controlled in the L3 mode of the
UDA1330ATS:

• System clock frequency

• Data input format

• De-emphasis for 32, 44.1 and 48 kHz

• Volume

• Soft mute.

Theexchange of dataand control information betweenthe
microcontroller and the UDA1330ATS is accomplished
through a serial interface comprising the following signals:

• L3DATA

• L3MODE

• L3CLOCK.

Information transfer through the microcontroller bus is
organized in accordance with the L3 interface format, in
which two different modes of operation can be
distinguished: address mode and data transfer mode.

Address mode

The address mode (see Fig.4) is required to select a
device communicating via the L3 interface and to define
the destination registers for the data transfer mode.

Data bits 7 to 2 represent a 6-bit device address where
bit 7 is the MSB. The address of the UDA1330ATS is
000101 (bit 7 to bit 2). If the UDA1330ATS receives a
different address, it will deselect its microcontroller
interface logic.

Data transfer mode

The fundamental timing of data transfers (see Fig.5) is
essentially the same as the address mode. The maximum
input clock frequency and data rate is 64fs.

Data transfer can only be in one direction, consisting of
input to the UDA1330ATS to program sound processing
andother functional features. Alldatatransfersare by 8-bit
bytes. Data will be stored in the UDA1330ATS after
reception of a complete byte.

A multibyte transfer is illustrated in Fig.6.

Registers

The sound processing and other feature values are stored
inindependent registers. The first selectionoftheregisters
is achieved by the choice of data type that is transferred.
Thisis performed intheaddress mode usingbit 1 and bit 0
(see Table 5).

Table 5 Selection of data transfer

BIT 1 BIT 0 TRANSFER

0 0 data (volume, de-emphasis, mute)
0 1 not used
1 0 status (system clock frequency,

data input format)

1 1 not used

The second selection is performed by the 2 MSBs of the
data byte (bit 7 and bit 6). The other bits in the data byte
(bit 5 to bit 0) represent the value that is placed in the
selected registers.

The ‘status’ settings are given in Table 6 and the ‘data’
settings are given in Table 7.

The selected address remains active during subsequent
data transfers until the UDA1330ATS receives a new
address command.

2001 Feb 02 8

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

t

h(L3)A

t

BIT 0

t

CLK(L3)L

t

t

su(L3)DA

CLK(L3)H

su(L3)A

Fig.4 Timing address mode.

t

h(L3)DA

t

su(L3)A

t

h(L3)A

T

cy(CLK)(L3)

BIT 7

MGL723

t

t

su(L3)D

stp(L3)

BIT 0

t

CLK(L3)H

t

su(L3)DA

t

CLK(L3)L

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

WRITE

Fig.5 Timing data transfer mode.

2001 Feb 02 9

T

cy(CLK)L3

t

h(L3)DA

t

BIT 7

h(L3)D

t

stp(L3)

MGL882

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

t

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

stp(L3)

address

addressdata byte #1 data byte #2

MGL725

Fig.6 Multibyte data transfer.

Programming the features

When the data transfer of type ‘status’ is selected, the features for the system clock frequency and the data input format
can be controlled.

Table 6 Data transfer of type ‘status’

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED

0 0 SC1 SC0 IF2 IF1 IF0 0 SC = system clock frequency (2 bits); see Table 8

IF = data input format (3 bits); see Table 9

10000000not used

When the data transfer of type ‘data’ is selected, the features for volume, de-emphasis and mute can be controlled.

Table 7 Data transfer of type ‘data’

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED

0 0 VC5 VC4 VC3 VC2 VC1 VC0 VC = volume control (6 bits); see Table 11
01000000not used
1 0 0 DE1 DE0 MT 0 0 DE = de-emphasis (2 bits); see Table 10

MT = mute (1 bit); see Table 12

11000001default setting

2001 Feb 02 10

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

SYSTEM CLOCK FREQUENCY
The system clock frequency is a 2-bit value to select the

external clock frequency.

Table 8 System clock settings

SC1 SC0 FUNCTION

0 0 512f
0 1 384f
1 0 256f

s
s
s

1 1 not used

DATA FORMAT
The data format is a 3-bit value to select the used data

format.

Table 9 Data input format settings

IF2 IF1 IF0 FORMAT

2

000I

S-bus
0 0 1 LSB-justified 16 bits
0 1 0 LSB-justified 18 bits
0 1 1 LSB-justified 20 bits
1 0 0 MSB-justified
1 0 1 not used
1 1 0 not used
1 1 1 not used

DE-EMPHASIS
De-emphasis is a 2-bit value to enable the digital

de-emphasis filter.

VOLUME CONTROL
The volume control is a 6-bit value to program the volume

attenuation from 0 to −60 dB and −∞ dB in steps of 1 dB.

Table 11 Volume settings

VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)

000000 0
000001 0
000010 −1
000011 −2

:::::: :
110011
110100
110101
110110
110111
111000

−51

−52

−54

111001

−57111010
111011
111100
111101
111110
111111

−60

−∞

MUTE
Mute is a 1-bit value to enable the digital mute.

Table 12 Mute setting

Table 10 De-emphasis settings

DE1 DE0 FUNCTION

0 0 no de-emphasis
0 1 de-emphasis, 32 kHz
1 0 de-emphasis, 44.1 kHz
1 1 de-emphasis, 48 kHz

2001 Feb 02 11

MT FUNCTION

0 no muting
1 muting

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

V

DDA

T

xtal(max)

T

stg

T

amb

V

es

I

sc(DAC)

Notes

1. All supply connections must be made to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.

3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.

4. Short-circuit test at T

digital supply voltage note 1 − 6.0 V
analog supply voltage note 1 − 6.0 V
maximum crystal temperature − 150 °C
storage temperature −65 +125 °C
ambient temperature −40 +85 °C
electrostatic handling voltage note 2 −3000 +3000 V

note 3 −250 +250 V

short-circuit current of DAC note 4

− 450 mA

− 300 mA

=0°C and V

amb

output short-circuited to V
output short-circuited toV

= 3 V. DAC operation after short-circuiting cannot be warranted.

DDA

SSA(DAC)

DDA(DAC)

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 190 K/W

QUALITY SPECIFICATION

In accordance with

“SNW-FQ-611-E”

.

2001 Feb 02 12

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

DC CHARACTERISTICS

V

DDD=VDDA

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

V

DDD

I

DDA

I

DDD

Power dissipation

P power dissipation playback mode

Digital inputs: pins BCK, WS, DATAI, SYSCLK, APPL0, APPL1, APPL2 and APPL3 (note 2)
V

IH

V

IL

I

 input leakage current −−1µA

LI

C

i

Three-level input: APPSEL

V

IH

V

IM

V

IL

= 5.0 V; T

=25°C; RL=5kΩ; all voltages referenced to ground (pins V

amb

SSA

and V

SSD

); unless

DAC analog supply voltage note 1 2.7 5.0 5.5 V
digital supply voltage note 1 2.7 5.0 5.5 V
DAC analog supply current V

DDA

= 5.0 V
operating − 9.5 − mA
power-down − 400 −µA

V

= 3.3 V

DDA

operating − 7.0 − mA
power-down − 250 −µA

digital supply current V

HIGH-level input voltage V

LOW-level input voltage V

= 5.0 V − 5.5 − mA

DDD

V

= 3.3 V − 3.0 − mA

DDD

V

DDA=VDDD

V

DDA=VDDD

= 5.0 V 2.2 −−V

DDD

V

= 3.3 V 1.45 −−V

DDD

= 5.0 V −−0.8 V

DDD

V

= 3.3 V −−0.5 V

DDD

= 5.0 V − 75 − mW
= 3.3 V − 33 − mW

input capacitance −−10 pF

HIGH-level input voltage 0.9V
MIDDLE-levelinput voltage 0.4V

DDD
DDD

LOW-level input voltage −0.5 − +0.1V

− V

DDD

− 0.6V

+ 0.5 V

DDD

DDD

V
V

2001 Feb 02 13

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DAC

V

ref(DAC)

I

o(max)

reference voltage with respect to V

SSA

maximum output current (THD + N)/S < 0.1%;

RL=5kΩ

R

o

R

L

C

L

output resistance − 0.15 2.0 Ω
load resistance 3 −−kΩ
load capacitance note 3 −−50 pF

Notes

1. All supply connections must be made to the same external power supply unit.

2. The digital input pads are TTL compatible at 5 V, but the pads are not 5 V tolerant in the voltage range between

2.7 and 4.5 V.

3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.

0.45V

DDA

0.5V

DDA

0.55V

DDA

V

− 0.36 − mA

AC CHARACTERISTICS

fi= 1 kHz; T

=25°C; RL=5kΩ; all voltages referenced to ground (pins V

amb

SSA

and V

); unless otherwise specified.

SSD

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

Digital-to-analog converter (V

V

o(rms)

∆V

o

output voltage (RMS value) 1.45 − V
unbalance between channels 0.1 − dB

DDA=VDDD

(THD + N)/S total harmonic distortion-plus-noise to

signal ratio

= 5.0 V)

at 0 dB −90 −85 dB
at −60 dB; A-weighted −40 −35 dB

S/N signal-to-noise ratio code = 0; A-weighted 100 95 dB

α

cs

Digital-to-analog converter (V

V

o(rms)

∆V

o

(THD + N)/S total harmonic distortion-plus-noise to

channel separation 100 − dB

DDA=VDDD

= 3.3 V)

output voltage (RMS value) 1.0 − V
unbalance between channels 0.1 − dB

at 0 dB −85 − dB

signal ratio

at −60 dB; A-weighted −38 − dB

S/N signal-to-noise ratio code = 0; A-weighted 100 − dB

α

cs

PSRR power supply ripple rejection f

channel separation 100 − dB

= 1 kHz;

ripple

V

= 100 mV (p-p)

ripple

60 − dB

2001 Feb 02 14

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

TIMING

V

DDD=VDDA

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

System clock (see Fig.7)

T

sys

t

CWL

t

CWH

Digital interface (see Fig.8)
T

cy(BCK)

t

BCKH

t

BCKL

t

r

t

f

t

su(DATAI)

t

h(DATAI)

t

su(WS)

t

h(WS)

Control interface L3 mode (see Figs 4 and 5)
T

cy(CLK)L3

t

CLK(L3)H

t

CLK(L3)L

t

su(L3)A

t

h(L3)A

t

su(L3)D

t

h(L3)D

t

su(L3)DA

t

h(L3)DA

t

stp(L3)

= 4.5 to 5.5 V; T

system clock cycle time f

LOW-level system clock pulse width f

HIGH-level system clock pulse width f

= −40 to +85 °C; RL=5kΩ; all voltages referenced to ground (pins V

amb

= 256f
f
f

f

f

sys
sys
sys
sys
sys
sys
sys

s

= 384f

s

= 512f

s

< 19.2 MHz 0.3T

≥ 19.2 MHz 0.4T

< 19.2 MHz 0.3T

≥ 19.2 MHz 0.4T

71 88 488 ns
47 59 325 ns
36 44 244 ns

− 0.7T

sys

− 0.6T

sys

− 0.7T

sys

− 0.6T

sys

bit clock cycle time 300 −−ns
bit clock HIGH time 100 −−ns
bit clock LOW time 100 −−ns
rise time −−20 ns
fall time −−20 ns
data input set-up time 20 −−ns
data input hold time 0 −−ns
word select set-up time 20 −−ns
word select hold time 10 −−ns

L3CLOCK cycle time 500 −−ns
L3CLOCK HIGH time 250 −−ns
L3CLOCK LOW time 250 −−ns
L3MODE set-up time for address mode 190 −−ns
L3MODE hold time for address mode 190 −−ns
L3MODE set-up time for data transfer

190 −−ns

mode
L3MODE hold time for data transfer

190 −−ns

mode
L3DATA set-up time fordata transferand

190 −−ns

address mode
L3DATA hold time for data transfer and

30 −−ns

address mode
L3MODE stop time for data transfer

190 −−ns

mode

SSA

and V

sys
sys
sys
sys

ns
ns
ns
ns

SSD

);

2001 Feb 02 15

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

handbook, full pagewidth

handbook, full pagewidth

WS

t

CWH

t

CWL

T

sys

MGR984

Fig.7 System clock timing.

t

h(WS)

BCK

DATAI

t

BCKH

t

r

T

cy(BCK)

t

f

t

BCKL

Fig.8 Serial interface timing.

2001 Feb 02 16

t

su(WS)

t

su(DATAI)

t

h(DATAI)

MGL880

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

APPLICATION INFORMATION

handbook, full pagewidth

system

clock

R1

47 Ω

SYSCLK

BCK

WS

DATAI

APPSEL

APPL0
APPL1
APPL2
APPL3

15 13

6

1

2
3
7

11
10

9
8

analog

supply voltage

C1

100 µF

(16 V)

C5

100 nF

(63 V)

V

SSA

UDA1330ATS

V

R2
1 Ω

DDA

digital

supply voltage

C6

100 nF

(63 V)

V

SSD

45

R3
1 Ω

V

DDD

14

16

12

VOUTL

VOUTR

V

ref(DAC)

C2

47 µF
(16 V)

C3

47 µF
(16 V)

C7
100 nF
(63 V)

R5
10 kΩ

R7
10 kΩ

R4

100 Ω

R6

100 Ω

C4
47 µF
(16 V)

left
output

right
output

MGL403

Fig.9 Application diagram.

2001 Feb 02 17

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

PACKAGE OUTLINE

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

D

c

y

Z

16

pin 1 index

9

18

w M

b

e

p

E

H

E

A

2

A

1

L

detail X

A

X

v M

A

Q

(A )

L

p

A

3

θ

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

A

max.

0.15

mm

1.5

OUTLINE
VERSION

SOT369-1 MO-152

0.00

1.4

1.2

IEC JEDEC EIAJ

0.25

b

3

p

0.32

0.20

0.25

0.13

(1)E(1)

cD

5.30

5.10

REFERENCES

4.5

4.3

0.65

2001 Feb 02 18

eHELLpQZywv θ

1.0

0.75

0.45

0.65

0.45

PROJECTION

0.130.2 0.1

EUROPEAN

6.6

6.2

(1)

0.48

0.18

ISSUE DATE

95-02-04
99-12-27

o

10

o

0

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

SOLDERING
Introduction to soldering surface mount packages

Thistextgives a very briefinsighttoa complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering isnot always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board byscreen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) or printed-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswith leads on four sides,thefootprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement andbefore soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2001 Feb 02 19

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

SOLDERING METHOD

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e)equal toor larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2001 Feb 02 20

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

DATA SHEET STATUS

DATA SHEET STATUS

Objective specification Development This data sheet contains the design target or goal specifications for

Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be

Product specification Production This data sheet contains final specifications. Philips Semiconductors

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
atthese or at any otherconditionsabove those given inthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarranty that such applications will be
suitable for the specified use without further testing or
modification.

PRODUCT

STATUS

DEFINITIONS

product development. Specification may change in any manner without
notice.

published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result inpersonal injury. Philips
Semiconductorscustomersusingor selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseof any of these products,conveysnolicence or title
under any patent, copyright, or mask work right to these
products,and makes no representationsorwarranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

(1)

2001 Feb 02 21

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

NOTES

2001 Feb 02 22

Philips Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

NOTES

2001 Feb 02 23

Philips Semiconductors – a w orldwide compan y

Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
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Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

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Indonesia: PT Philips Development Corporation,Semiconductors Division,
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Ireland: Newstead, Clonskeagh, DUBLIN 14,
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Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
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Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2001

Internet: http://www.semiconductors.philips.com

71

Printed in The Netherlands 753503/05/pp24 Date of release: 2001 Feb 02 Document order number: 9397 750 07939