Datasheet UDA1321PS-N101, UDA1321H-N102, UDA1321H-N101, UDA1321H-N1, UDA1321T-N101 Datasheet (Philips)

DATA SH EET

Preliminary specification
Supersedes data of 1998 May 12
File under Integrated Circuits, IC01

1998 Oct 06

INTEGRATED CIRCUITS

UDA1321

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

1998 Oct 06 2

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

FEATURES
General

• Universal Serial Bus (USB) stereo Digital-to-Analog
Converter (DAC) system with adaptive (5 to 55 kHz)
20-bits digital-to-analog conversion and filtering

• USB-compliant audio and Human Interface Device
(HID)

• Supports 12 Mbits/s full-speed serial data transmission

• Supports multiple audio data formats (8, 16 and 24 bits)

• Supports headphone and line output

• Fully automatic ‘Plug-and-Play’ operation

• High linearity

• Wide dynamic range

• Superior signal-to-noise ratio (typical 95 dB)

• Low total harmonic distortion (typical 90 dB)

• 3.3 V power supply

• Efficient power management

• Low power consumption

• On-chip master clock oscillator, only an external crystal

is required

• Partly programmable USB descriptors and configuration
via I

2

C-bus.

Sound processing

• Separate digital volume control for left and right channel

• Soft mute

• Digital bass and treble tone control

• External Digital Sound Processor (DSP) option possible

via standard I

2

S-bus or Japanese digital I/O format

• Selectable clipping prevention

• Selectable Dynamic Bass Boost (DBB)

• On-chip digital de-emphasis.

Document references

•

“USB Specification”

•

“USB Common Class Specification”

•

“USB Device Class Definition for Audio Devices”

•

“Device Class Definition for Human Interface Devices
(HID)”

•

“USB HID Usage Table”

.

APPLICATIONS

• USB monitors

• USB speakers

• USB headsets

• USB telephone/answering machines

• USB links in consumer audio devices.

GENERAL DESCRIPTION

The UDA1321 is a stereo CMOS digital-to-analog
bitstream converter designed for USB-compliant audio
playback devices and multimedia audio
applications.The UDA1321 is an adaptive asynchronous
sink USB audio device with a continuous sampling
frequency (f

s

) range from 5 to 55 kHz. It contains a USB
interface, an embedded microcontroller and an
Asynchronous Digital-to-Analog Converter (ADAC).

The USB interface is the interface between the USB, the
ADAC and the microcontroller. The USB interface consists
of an analog front-end and a USB processor. The analog
front-end transforms the differential USB data to a digital
data stream. The USB processor buffers the input and
output data from the analog front-end and handles all
low-level USB protocols. The USB processor selects the
relevant data from the universal serial bus, performs an
extensive error detection and separates control
information (input and output) and audio information (input
only).

1998 Oct 06 3

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

The control information becomes accessible at the
microcontroller. The audio information becomes available
at the digital I/O output or is fed directly to the ADAC.

The microcontroller handles the high-level USB protocols,
translates the incoming control requests and manages the
user interface via General Purpose (GP) pins and an
I2C-bus.

The ADAC enables the wide and continuous range of input
sampling frequencies. By means of a Sample Frequency
Generator (SFG), the ADAC is able to reconstruct the
average sample frequency from the incoming audio
samples. The ADAC also performs the sound processing.

The ADAC consists of FIFO registers, a unique audio
feature processing DSP, the SFG, digital up-sampling
filters, a variable hold register, a Noise Shaper (NS) and a
Filter Stream DAC (FSDAC) with integrated filter and line
output drivers. The audio information is applied to the
ADAC via the USB processor or via the digital I/O input.

An external DSP can be used for adding extra sound
processing features via the digital I/O-bus.

The UDA1321 supports the standard I2S-bus data input
format and the LSB-justified serial data input format with
word lengths of 16, 18 and 20 bits.

The wide dynamic range of the bitstream conversion
technique used in the UDA1321 guarantees a high audio
sound quality.

QUICK REFERENCE DATA

Notes

1. VDD is the supply voltage on pins V

DDA

, V

DDE

, V

DDI

and V

DDX

. VSS is the ground on pins V

SSA

, V

SSE

, V

SSI

and V

SSX

.

All VDD and VSS pins must be connected to the same supply or ground respectively.

2. The audio information from the USB interface is fed directly to the ADAC.

3. The power-save mode (power management) is not supported in the UDA1321/N101;
see Chapter “USB-DAC UDA1321/N101 (Firmware sw 2.1.1.7)”.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DD

supply voltage note 1 3.0 3.3 3.6 V

I

DD(tot)

total supply current − 50 − mA

I

DD(ps)

supply current in power-save
mode

note 3 − 18 − mA

Dynamic performance DAC

total harmonic
distortion-plus-noise to signal
ratio

fs= 44.1 kHz; RL=5kΩ

at input signal of 1 kHz (0 dB) −−90

(2)

−80 dB

− 0.0032 0.01 %

at input signal of 1 kHz (−60 dB) −−30

(2)

−20 dB

− 3.2 10 %

S/N

bz

signal-to-noise ratio at bipolar
zero

A-weighted at code 0000H 90 95 − dBA

V

o(FS)(rms)

full-scale output voltage
(RMS value)

VDD= 3.3 V − 0.66 − V

General characteristics

f

i(sample)

audio sample input frequency 5 − 55 kHz

T

amb

operating ambient temperature 0 25 70 °C

THD N+

S

---------------------- -

1998 Oct 06 4

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

UDA1321H/N101 QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm);

body 14 × 20 × 2.8 mm

SOT319-2

UDA1321T/N101 SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1
UDA1321PS/N101 SDIP32 plastic shrink dual in-line package; 32 leads (400 mil) SOT232-1

1998 Oct 06 5

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGM839

ANALOG FRONT-END

D+

USB-PROCESSOR

FIFO REGISTERS

OSC

TEST

CONTROL

BLOCK

MICRO-

CONTROLLER

LEFT

DAC

RIGHT

DAC

TIMING

f

s

f

s

64f

s

128f

s

SAMPLE
FREQUENCY
GENERATOR

UP-SAMPLE FILTERS

VARIABLE HOLD REGISTER

UDA1321H
UDA1321T

UDA1321PS

3rd-ORDER

NOISE SHAPER

REFERENCE

VOLTAGE

AUDIO FEATURE

PROCESSING DSP

DIGITAL I/O

GP4/BCKO

GP2/DO

GP0/BCKI

GP3/WSO

GP1/DI

V

SSX

TC

RTCB

SHTCB

XTAL2

XTAL1

V

DDX

VOUTL

GP5/WSI

SCL
SDA

EA
PSEN

ALE
P2.0

P2.1
P2.2

P2.3
P2.4

P2.5
P2.6

P2.7
P0.0

P0.1
P0.2
P0.3

P0.4
P0.5

P0.6
P0.7

V

DDE

V

SSE

V

SSI

V

DDI

V

DDO

V

SSO

V

DDA

V

SSA

VOUTR

V

ref

D−

1998 Oct 06 6

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

PINNING

SYMBOL

PIN

QFP64

PIN

SDIP32

PIN

SO28

I/O DESCRIPTION

GP5/WSI 2 29 25 I/O general purpose pin 5 or word select input
SCL 3 30 26 I/O serial clock input (I

2

C-bus)

SDA 4 31 27 I/O serial data input/output (I

2

C-bus)
P0.7 5 n.a. n.a. I/O Port 0.7 of the microcontroller
EA 6 n.a. n.a. I/O external access (active LOW)
GP1/DI 7 32 28 I/O general purpose pin 1 or data input
PSEN 8 n.a. n.a. I/O program store enable (active LOW)
ALE 9 n.a. n.a. I/O address latch enable (active HIGH)
GP2/DO 10 1 1 I/O general purpose pin 2 or data output for extra DSP

chip
P2.0 11 n.a. n.a. I/O Port 2.0 of the microcontroller
P2.1 12 n.a. n.a. I/O Port 2.1 of the microcontroller
GP3/WSO 13 2 2 I/O general purpose pin 3 or master word select output for

extra DSP chip
GP4/BCKO 14 3 3 I/O general purpose pin 4 or master bit clock output for

extra DSP chip
SHTCB 15 4 4 I shift clock TCB input (active HIGH)
D− 17 6 5 I/O negative data line of the differential data bus conform

to the USB-standard
P2.2 18 n.a. n.a. I/O Port 2.2 of the microcontroller
P2.3 19 n.a. n.a. I/O Port 2.3 of the microcontroller
D+ 20 7 6 I/O positive data line of the differential data bus conform to

the USB-standard
P2.4 21 n.a. n.a. I/O Port 2.4 of the microcontroller
P2.5 22 n.a. n.a. I/O Port 2.5 of the microcontroller
P2.6 23 n.a. n.a. I/O Port 2.6 of the microcontroller
P2.7 24 n.a. n.a. I/O Port 2.7 of the microcontroller
V

DDI

25 8 7 − digital supply voltage core

V

SSI

29 9 8 − digital ground core

V

SSE

30 10 9 − digital ground I/O pins

V

DDE

32 11 10 − digital supply voltage I/O pins

V

SSX

36 13 11 − crystal oscillator ground
XTAL1 37 14 12 I crystal oscillator input1
XTAL2 38 15 13 O crystal oscillator output 2
V

DDX

39 16 14 − crystal oscillator supply voltage
V

ref

42 18 15 O reference output voltage
V

SSA

44 19 16 − analog ground
V

DDA

45 20 17 − analog supply voltage
VOUTR 46 21 18 O right channel output voltage
V

SSO

49 22 19 − operational amplifier ground

1998 Oct 06 7

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

V

DDO

51 23 20 − operational amplifier supply voltage
VOUTL 53 24 21 O left channel output voltage
TC 55 25 22 I test control input (active HIGH)
P0.0 56 n.a. n.a. I/O Port 0.0 of the microcontroller
P0.1 57 n.a. n.a. I/O Port 0.1 of the microcontroller
P0.2 58 n.a. n.a. I/O Port 0.2 of the microcontroller
P0.3 59 n.a. n.a. I/O Port 0.3 of the microcontroller
P0.4 60 n.a. n.a. I/O Port 0.4 of the microcontroller
RTCB 61 26 23 I asynchronous reset input for test control box (active

HIGH)
P0.5 62 n.a. n.a. I/O Port 0.5 of the microcontroller
P0.6 63 n.a. n.a. I/O Port 0.6 of the microcontroller
GP0/BCKI 64 27 24 I/O general purpose pin 0 or master bit clock input
n.c. 1, 16, 26,

27, 28, 31,
33, 34, 35,
40, 41, 43,
47, 48, 50,

52, 54

5, 12, 17,

28

n.a. − not connected

SYMBOL

PIN

QFP64

PIN

SDIP32

PIN

SO28

I/O DESCRIPTION

1998 Oct 06 8

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Fig.2 Pin configuration QFP64.

handbook, full pagewidth

UDA1321H

MGM850

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19

n.c.

GP5/WSI

SCL
SDA
P0.7

EA

GP1/DI

PSEN

ALE

GP2/DO

P2.0
P2.1

GP3/WSO

GP4/BCKO

SHTCB

n.c.

D−
P2.2
P2.3

V

DDO

n.c.
V

SSO

n.c.
n.c.
VOUTR

V

DDA

V

SSA
n.c.
V

REF
n.c.

n.c.
V

DDX
XTAL2

XTAL1
V

SSX
n.c.

n.c.
n.c.

51

50
49
48
47
46
45
44
43
42

41
40
39
38
37
36
35
34
33

20

21

22

23

24

25

26

27

28

29

30

31

32

64

63

62

61

60

59

58

57

56

55

54

53

52

GP0/BCKI

P0.6

P0.5

RTCB

P0.4

P0.3

P0.2

P0.1

P0.0

TC

n.c.

VOUTL

n.c.

D+

P2.4

P2.5

P2.6

P2.7

V

DDI

n.c.

n.c.

n.c.

V

SSI

V

SSE

n.c.

V

DDE

1998 Oct 06 9

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Fig.3 Pin configuration SO28.

handbook, halfpage

GP2/DO

GP3/WSO

GP4/BCKO

SHTCB

D−
D+

V

DDI

V

SSI

V

SSE

V

DDE

V

SSX

XTAL1
XTAL2

V

DDX

GP1/DI
SDA
SCL
GP5/WSI

RTCB
TC

GP0/BCKI

VOUTL
V

DDO

V

SSO

VOUTR
V

DDA

V

SSA

V

ref

1
2
3
4
5
6
7
8

9
10
11
12
13

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

UDA1321T

MGM840

Fig.4 Pin configuration SDIP32.

handbook, halfpage

UDA1321PS

MGM841

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

GP2/DO GP1/DI

GP3/WSO SDA

GP4/BCKO SCL

SHTCB GP5/WSI

n.c.

n.c.

n.c.
D− GP0/BCKI
D+ RTCB

V

DDI

V

SSI

V

SSE

V

DDE

V

SSX

V

DDX

TC

VOUTL

VOUTR

XTAL1

V

SSA

V

DDA

V

SSO

V

DDO

XTAL2

V

ref

n.c.

1998 Oct 06 10

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

FUNCTIONAL DESCRIPTION
All bold-faced parameters given in this data sheet

such as ‘bAlternateSetting’ are part of the USB
specification as described in

“USB Device Class

Definition for Audio Devices”

.

The Universal Serial Bus (USB)

Data and power are transferred via the USB by a 4-wire
cable. The signalling occurs via two wires and
point-to-point segments. The signals on each segment are
differentially driven into a cable of 90 Ω intrinsic
impedance. The differential receiver features input
sensitivity of at least 200 mV and sufficient common mode
rejection.

The analog front-end

The analog front-end is an on-chip generic USB
transceiver. It is designed to allow voltage levels up to V

DD

from standard or programmable logic to interface with the
physical layer of the USB. It is capable of receiving and
transmitting serial data at full speed (12 Mbits/s).

The USB processor

The USB processor forms the interface between the
analog front-end, the ADAC and the microcontroller.
The USB processor consists of:

• The Philips Serial Interface Engine (PSIE)

• The Memory Management Unit (MMU)

• The Audio Sample Redistribution (ASR) module.

T

HE PHILIPS SERIAL INTERFACE ENGINE AND MEMORY

MANAGEMENT UNIT (PSIE AND MMU)
The PSIE and MMU translate the electrical USB signals

into bytes and signals. Depending upon the USB device
address and the USB endpoint address, the USB data is
directed to the correct endpoint buffer on the PSIE and
MMU interface. The data transfer could be of the bulk,
isochronous, control or interrupt type. The USB device
address is configured during the enumeration process.
The UDA1321 has three endpoints. These are:

• Control endpoint 0

• Status interrupt endpoint

• Isochronous data sink endpoint.

The amount of bytes per packet on the control endpoint is
limited by the PSIE and MMU hardware to 8 bytes per
packet.

The PSIE is the digital front-end of the USB processor.This
module recovers the 12 MHz USB clock, detects the USB
sync word and handles all low-level USB protocols and
error checking.

The MMU is the digital back-end of the USB processor.
It handles the temporary data storage of all USB packets
that are received or sent over the bus. Three types of
packets are defined on the USB. These are:

• Token packets

• Data packets

• Handshake packets.

The token packet contains information about the
destination of the data packet. The audio data is
transferred via an isochronous data sink endpoint and
consequently no handshaking mechanism is used.
The MMU also generates a 1 kHz clock that is locked to
the USB Start-Of-Frame (SOF) token.

T

HE AUDIO SAMPLE REDISTRIBUTION (ASR) MODULE

The ASR module reads the audio samples from the MMU
and distributes these samples equidistant over a 1 ms
frame period. The distributed audio samples are translated
by the digital I/O module to standard I2S-bus format or
Japanese digital I/O format. The ASR module generates
the bit clock and the word select signal of the digital I/O.
The digital I/O formats the received audio samples to one
of the four specified serial digital audio formats
(standard I2S-bus, 16, 18 or 20 bits LSB-justified).

The microcontroller

The microcontroller receives the control information
selected from the USB by the USB processor. It handles
the high-level USB protocols and the user interfaces.

The major task of the software process, that is mapped
upon the microcontroller, is to control the different modules
of the UDA1321 in such a way that it behaves as a USB
device. Therefore the microcontroller:

• Interprets the USB requests and maps them upon the
UDA1321 application

• Controls the internal operation of the UDA1321 and the
digital I/O pins

• Communicates with the external world (EEPROM) using
the I

2

C-bus facility and the general purpose I/O pins.

1998 Oct 06 11

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

The Asynchronous Digital-to-Analog Converter
(ADAC)

The ADAC receives USB audio information from the USB
processor or from the digital I/O-bus. The ADAC is able to
reconstruct the sample clock from the rate at which the
audio samples arrive and handles the audio sound
processing. After processing, the audio signal is
up-sampled, noise-shaped and converted to analog output
voltages capable of driving a line output. The ADAC
consists of:

• A Sample Frequency Generator (SFG)

• First-In First-Out (FIFO) registers

• An audio feature processing DSP

• Two digital up-sample filters

• A variable hold register

• A digital Noise Shaper (NS)

• A Filter Stream DAC (FSDAC) with integrated filter and

line output drivers.

THE SAMPLE FREQUENCY GENERATOR (SFG)
The SFG controls the timing signals for the asynchronous

digital-to-analog conversion. By means of a digital PLL,
the SFG automatically recovers the applied sampling
frequency and generates the accurate timing signals for
the audio feature processing DSP and the up-sample
filters.

F

IRST-IN FIRST-OUT (FIFO) REGISTERS

The FIFO registers are used to store the audio samples
temporarily coming from the USB processor or from the
digital I/O input. The use of a FIFO register (in conjunction
with the SFG) is necessary to remove all jitter present on
the incoming audio signal.

T

HE AUDIO FEATURE PROCESSING DSP

A DSP processes the sound features. The control and
mapping of the sound features is explained in Section
“Controlling the USB Digital-to-Analog Converter (DAC)”.
Depending on the sampling rate (fs) the DSP has four
frequency domains in which the treble and bass are
regulated (see Table 1). The domain is chosen
automatically.

T

HE UP-SAMPLE FILTERS AND VARIABLE HOLD REGISTER

After the audio feature processing DSP two up-sample
filters and a variable hold register increase the
oversampling rate to 128fs.

Table 1 Frequency domains for audio processing

T

HE NOISE SHAPER

A 3rd-order noise shaper converts the oversampled data
to a noise-shaped bitstream for the FSDAC. The in-band
quantization noise is shifted to frequencies well above the
audio band.

T

HE FILTER STREAM DAC (FSDAC)

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post filter is not needed
because of the inherent filter function of the DAC.
On-board amplifiers convert the FSDAC output current to
an output voltage signal capable of driving a line output.

USB Digital-to-Analog Converter (DAC) descriptors

In a typical USB environment the USB host has to know
which kind of devices are connected. For this purpose
each device contains a number of USB descriptors. These
descriptors describe, from different points of view (USB
configuration, USB interface and USB endpoint), the
capabilities of a device. Each of them can be requested by
the host. The collection of descriptors is denoted as a
descriptor map. This descriptor map will be reported to the
USB host during enumeration and on request.

The full descriptor map is implemented in the firmware
exploiting the full functionality of the UDA1321. The USB
descriptors and their most important fields, in relationship
to the characteristics of the UDA1321 are briefly explained
below.

G

ENERAL DESCRIPTORS

The UDA1321 supports one configuration containing a
control interface, an audio interface and a HID interface.
The descriptor map that describes this configuration is
partly fixed and partly programmable.

DOMAIN SAMPLE FREQUENCY (kHz)

1 5 to 12
212to25
325to40
440to55

1998 Oct 06 12

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Fig.5 Audio function topology.

handbook, full pagewidth

MBK530

INPUT TERMINAL

OUTPUT TERMINAL

FEATURE UNIT

FU

IT

OT

The programmable part can be retrieved from one of four
configuration maps located in the firmware or from an
I2C-bus EEPROM. At start-up one of four configuration
maps can be selected depending on the logical
combination of GP3 and GP0. It is possible to overwrite
this configuration map with a configuration map loaded
from an I2C-bus EEPROM.

A

UDIO DEVICE CLASS SPECIFIC DESCRIPTORS

The audio device class is partly specified with standard
descriptors and partly with specific audio device class
descriptors. The standard descriptors specify the number
and the type of the interface or endpoint. The UDA1321
supports 7 different audio modes:

• 8-bit Pulse Code Modulation (PCM) mono or stereo
audio data

• 16-bit PCM mono or stereo audio data

• 24-bit PCM mono or stereo audio data

• Zero bandwidth mode.

Each mode is defined as an alternate setting of the audio
interface, selectable with the standard audio streaming
interface descriptor bAlternateSetting field.

The seven alternate settings are described in more detail
by the specific audio device class descriptors.

The UDA1321 supports the Input Terminal (IT), Output
Terminal (OT) and the Feature Unit (FU) descriptors.

The input and output terminals are not controllable via the
USB. The feature unit provides the basic manipulation of
the incoming logical channels.

The supported sound features are:

• Volume control

• Mute control

• Treble control

• Bass control

• Bass boost control.

Table 2 Audio bandwidth at each audio mode

The maximum number of audio data samples within a USB
packet arriving on the isochronous sink endpoint is
restricted by the buffer capacity of this isochronous
endpoint. The maximum buffer capacity is 336 bytes/ms.

For each alternate setting with audio, a maximum
bandwidth is claimed as indicated in the standard
isochronous audio data endpoint descriptor
wMaxPacketSize field. To allow a small overshoot in the
number of audio samples per packet, the top sample
frequency of 55 kHz is taken in the calculation of the
bandwidth for each alternate setting. For each alternate
setting, with its own isochronous audio data endpoint
descriptor, wMaxPacketSize field is then defined as
described in Table 2.

Although in a specific UDA1321 application no endpoint
control properties can be used upon the isochronous
adaptive sink endpoint, the descriptors are still necessary
to inform the host about the definition of this endpoint:
isochronous, adaptive, sink, continuous sampling
frequency (at input side of this endpoint) with lower bound
of 5 kHz and upper bound of 55 kHz.

The audio class specific descriptors can be requested with
the ‘Get descriptor: configuration request’, which returns
all the descriptors, except the device descriptor.

H

UMAN INTERFACE DEVICE SPECIFIC DESCRIPTORS

The inputs defined on the UDA1321 are transmitted via the
USB to the host according to the HID class. The host

AUDIO MODE wMaxPacketSize

8-bit PCM; mono 56 (8⁄8× 1 × 56)
8-bit PCM; stereo 112 (8⁄8× 2 × 56)
16-bit PCM; mono 112 (16⁄8× 1 × 56)
16-bit PCM; stereo 224 (16⁄8× 2 × 56)
24-bit PCM; mono 168 (24⁄8× 1 × 56)
24-bit PCM; stereo 336 (24⁄8× 2 × 56)

1998 Oct 06 13

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

responds with the appropriate settings via the audio device
class for the audio related parts or via the HID class for the
HID related inputs and outputs of the UDA1321.

A HID descriptor is necessary to inform the host about the
conception of the user interface. The host communicates
via the HID device driver using either the control pipe or
the interrupt pipe. The UDA1321 uses USB endpoint 0
(control pipe) to respond to the HID specific ‘Get/set report
request’ to receive or transmit data from or to the
UDA1321. The UDA1321 uses the status interrupt
endpoint as interrupt pipe for polling asynchronous data.

The UDA1321 is a high-speed device. The maximum
transaction size is 64 bytes per USB frame and the polling
rate is defined at a maximum of every 1 ms.

The host requests the configuration descriptor which
includes the standard interface descriptor, the HID
endpoint descriptor and the HID descriptor. The HID
device driver of the host then requests the report
descriptor.

Report descriptors are composed of pieces of information
about the device. Each piece of information is called an
item. All items have a 1-byte prefix that contains the item
tag, type and size. In the UDA1321 only the short item
basic type is used.

The hosts HID device driver will parse the report descriptor
and the defined items. By examining all of these items, the
HID class driver is able to determine the size and
composition of data reports from the device.

The main items of the UDA1321 are input and output
reports. Input reports are sent via the interrupt pipe
(UDA1321 USB address 3). Input and output reports can
be requested by the host via the control endpoint (USB
address 0).

The UDA1321 supports a maximum of three pushbuttons,
which represents a certain feature of the UDA1321. If
pressed by the user the pushbutton will go to its ‘ON’ state,
if not pressed the pushbutton will go back to its ‘OFF’ state.
The UDA1321 supports a maximum of two outputs for e.g.
user LEDs.

For more information about the input and output functions
of the UDA1321 see the application documentation of the
device.

Controlling the USB Digital-to-Analog Converter
(DAC)

This section describes the functionality of the feature unit
of the UDA1321. The mapping of this functionality onto
USB descriptors is as implemented in the firmware.

The sound features as defined in the

“USB Device Class

Definition for Audio Devices”

are mapped on the UDA1321
specific feature registers by the microcontroller. These
specific sound features are:

• Volume control (separate for left and right stereo

channels, no master channel)

• Mute control (only master channel)

• Treble control (only master channel)

• Bass control (only master channel)

• Dynamic bass boost control (only master channel).

These specific features can be activated via the host
(audio device class requests) or via the GP pins (HID plus
audio device class requests). Via the I2C-bus the user is
able to download the necessary configuration data for
different applications (definition of the function of the GP
pins, with or without digital I/O functionality, etc.).
The mapping and control of the standard USB audio
features and UDA1321 specific features is described
below.

V

OLUME CONTROL

Volume control is possible via the host or via predefined
GP pins. The setting of 0 dB is always referenced to the
maximum available volume setting. Table 3 gives the
mapping of wVolume value (as defined in the

“USB

Device Class Definition for Audio Devices”

) upon the
actual volume setting of the USB DAC. When using the
UDA1321, the range is 0 down to−60 dB (in steps of 1 dB)
and −∞ dB. Independant control of ‘left’/’right’ volume is
possible. It should be noted that wVolume bits B7 to B0
are not used. Values above 0 dB are returned as 0 dB.
The volume value at start-up of the device is defined in the
selected configuration map.

Balance control is possible via the separate volume control
option of both channels. Therefore the characteristics of
the balance control are equal to the volume control
characteristics.

1998 Oct 06 14

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Table 3 Volume control characteristics; note 1

Note

1. The volume control characteristics of this table are in accordance with the latest Audio Device Class Definition.
The volume control characteristics of the UDA1321/N101 are slightly different; see Chapter “USB-DAC
UDA1321/N101 (Firmware sw 2.1.1.7)”

wVOLUME

VOLUME USB SIDE

(dB)

VOLUME USB DAC

(dB)

B15 B14 B13 B12 B11 B10 B9 B8

00000000 0 0
11111111 −1 −1
11111110 −2 −2
11111101 −3 −3
11111100 −4 −4
11111011 −5 −5
11111010 −6 −6
11111001 −7 −7
11111000 −8 −8
11110111 −9 −9
11110110 −10 −10

... ... ... ... ... ... ... ... ... ...

11000101 −59 −59
11000100 −60 −60
11000011 −61 −∞
11000010 −62 −∞

... ... ... ... ... ... ... ... ... ...

10000000 −∞ −∞

MUTE CONTROL
Mute is one of the sound features as defined in the

“USB

Device Class Definition for Audio Devices”

. The mute
control request data bMute controls the position of the
mute switch. The position can be either on or off. When
bMute is true the feature unit is muted. When bMute is
false the feature unit is not muted.

When the mute is active for the master channel, the value
of the sample is decreased smoothly to zero following a
raised cosine curve. There are 32 coefficients used to step
down the value of the data, each one being used 32 times
before stepping to the next.

This amounts to a mute transition of 23 ms at
f

s

= 44.1 kHz. When the mute is released, the samples are
returned to the full level again following a raised cosine
curve with the same coefficients being used in reversed
order. The mute, on the master channel is synchronized to
the sample clock, so that operation always takes place on
complete samples.

A mute can be given via the host or by pressing a
predefined GP pin.

1998 Oct 06 15

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

TREBLE CONTROL
The treble control is available for the master channel of the UDA1321. Treble can be regulated in three modes: minimum,

flat and maximum mode. The preferred mode is selected at start-up of the device (configuration map). The corner
frequency is 3000 Hz for the minimum mode and 1500 Hz for the maximum mode. The treble range is from 0 to 6 dB in
steps of 2 dB. It should be noted that the negative treble values as defined in the

“USB Device Class Definition for Audio

Devices”

are not supported by the UDA1321; the 0 dB value is returned as 0 dB. Table 4 gives the mapping of the

bTreble value upon the actual treble setting of the USB DAC.

Table 4 Treble control characteristics; note 1

Note

1. The 2 dB step is not supported in the UDA1321/N101; see Chapter “USB-DAC UDA1321/N101
(Firmware sw 2.1.1.7)”.

bTREBLE

TREBLE USB

SIDE (dB)

TREBLE USB DAC (dB)

B7 B6 B5 B4 B3 B2 B1 B0 minimum flat maximum

0 0 0 0 0 0 0 0 0.00 0 0 0
0 0 0 0 0 0 0 1 0.25
0 0 0 0 0 0 1 0 0.50
0 0 0 0 0 0 1 1 0.75
0 0 0 0 0 1 0 0 1.00
0 0 0 0 0 1 0 1 1.25 2 0 2
0 0 0 0 0 1 1 0 1.50
0 0 0 0 0 1 1 1 1.75
0 0 0 0 1 0 0 0 2.00
0 0 0 0 1 0 0 1 2.25
0 0 0 0 1 0 1 0 2.50
0 0 0 0 1 0 1 1 2.75
0 0 0 0 1 1 0 0 3.00
0 0 0 0 1 1 0 1 3.25 4 0 4

...

0 0 0 1 0 1 0 1 5.25 6 0 6

...

0 0 0 1 1 1 0 1 7.25 6 0 6

...

0 0 1 0 0 1 0 1 9.25 6 0 6

...

0 1 1 1 1 1 1 1 31.75 6 0 6

1998 Oct 06 16

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

BASS CONTROL
The bass control is available for the master channel of the UDA1321. Bass can be regulated in three modes: minimum,

flat and maximum mode. The preferred mode is selected at start-up of the device (configuration map). The Bass range
is from 0 to about 14 dB (minimum mode) or about 24 dB (maximum mode) in steps of 2 dB. It should be noted that the
negative bass values as defined in the

“USB Device Class Definition for Audio Devices”

are not supported by the
UDA1321; the 0 dB value is returned as 0 dB. The maximum Bass value which will be reported to the host is always
24 dB independent of the mode. The maximum mode is the most accurate mode when the Bass values are reported to
the host. The corner frequency is 100 Hz for the minimum mode and 75 Hz for the maximum mode. Table 5 gives the
mapping of the bBass value upon the actual bass setting of the USB DAC.

Table 5 Bass control characteristics

bBASS

BASS USB

SIDE (dB)

BASS USB DAC (dB)

B7 B6 B5 B4 B3 B2 B1 B0 minimum flat maximum

0 0 0 0 0 0 0 0 0.00 0 0 0
0 0 0 0 0 0 0 1 0.25
0 0 0 0 0 0 1 0 0.50
0 0 0 0 0 0 1 1 0.75
0 0 0 0 0 1 0 0 1.00
0 0 0 0 0 1 0 1 1.25 1.1 0 1.7
0 0 0 0 0 1 1 0 1.50
0 0 0 0 0 1 1 1 1.75
0 0 0 0 1 0 0 0 2.00
0 0 0 0 1 0 0 1 2.25
0 0 0 0 1 0 1 0 2.50
0 0 0 0 1 0 1 1 2.75
0 0 0 0 1 1 0 0 3.00
0 0 0 0 1 1 0 1 3.25 2.4 0 3.6

...

0 0 0 1 0 1 0 1 5.25 3.7 0 5.4

...

0 0 0 1 1 1 0 1 7.25 5.2 0 7.4

...

0 0 1 0 0 1 0 1 9.25 6.8 0 9.4

...

0 0 1 0 1 1 0 1 11.25 8.4 0 11.3

...

0 0 1 1 0 1 0 1 13.25 10.2 0 13.3

...

0 0 1 1 1 1 0 1 15.25 11.9 0 15.2

...

0 1 0 0 0 1 0 1 17.25 13.7 0 17.3

...

1998 Oct 06 17

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

0 1 0 0 1 1 0 1 19.25 13.7 0 19.2

...

0 0 1 1 1 0 1 1 21.25 13.7 0 21.2

...

0 1 0 1 0 1 0 1 23.25 13.7 0 23.2

...

0 1 1 0 0 1 0 1 25.25 13.7 0 23.2

...

0 1 1 0 1 1 0 1 27.25 13.7 0 23.2

...

0 1 1 1 0 1 0 1 29.25 13.7 0 23.2

...

0 1 1 1 1 1 0 1 31.25 13.7 0 23.2

...

0 1 1 1 1 1 1 1 31.75 13.7 0 23.2

bBASS

BASS USB

SIDE (dB)

BASS USB DAC (dB)

B7 B6 B5 B4 B3 B2 B1 B0 minimum flat maximum

DYNAMIC BASS BOOST CONTROL
Bass boost is one of the sound features as defined in the

“USB Device Class Definition for Audio Devices”

.
The bass boost control request databBassBoost controls
the position of the bass boost switch. The position can be
either on or off. When bBassBoost is true the bass boost
is activated. When bBassBoost is false the bass boost is
off.

When clipping prevention is active, the bass is reduced to
avoid clipping with high volume settings. Bass boost is
selectable via the configuration map (see Table 6).
If byte 19H is loaded with 00H, bass boost is not reported
to the USB host by the device.

Clipping prevention

If the maximum of the bass plus volume gives clipping, the
Bass is reduced. Clipping prevention is selectable via the
configuration map.

De-emphasis

De-emphasis is one of the properties which is not
supported by the USB. De-emphasis for 44.1 kHz can be
predefined in the configuration map selected at start-up of
the UDA1321.

1998 Oct 06 18

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Fig.6 Diode matrix selection.

handbook, full pagewidth

MGM109

10 nF

10 nF

22 pF 22 pF

4

6

5

3

2

1

USB-B

connector

V

bus

22 Ω

22 Ω

D−

GP5

GP3

GP0

D+

1.5 kΩ

22 kΩ

22 kΩ

22 kΩ 22 kΩ

22 kΩ

22 kΩ

TR3

TR1 TR2

3.3 V 3.3 V 3.3 V 3.3 V

22 kΩ

V

bus

1

2

D2

1

2

D1

KEY 1

SW1

KEY 2

SW2

Start-up and configuration of the UDA1321

S

TART-UP OF THE UDA1321

After power-on, an internal power-on reset signal becomes
HIGH after a certain RC-time (R = 5 kΩ and C = C

ref

).
During 10 ms after power-on reset the UDA1321 has to
initiate the internal settings. After the power-on reset the
UDA1321 becomes master of the I2C-bus. The UDA1321
tries to read the eventually connected EEPROM and if an
EEPROM is detected, the internal descriptors are
overwritten and the selected port configuration is applied.
If no EEPROM is detected, the UDA1321 tries to read the
logical levels of GP3 and GP0. A choice can be made from
four configuration maps via these two pins.

C

ONFIGURATION SELECTION OF THE UDA1321 VIA A DIODE

MATRIX

The UDA1321 uses a configuration map to hold a number
of specific configurable data on hardware, product,
component and USB configuration level. At start-up
without EEPROM, the UDA1321 will scan the logical levels
of GP3 and GP0. With these two pins it is possible to
select one of the four possible (vendor specific)
configuration maps. This selection can be achieved via a
diode matrix (see Fig.6).

After selecting a configuration map the user cannot
change the chosen settings for the GP pins, internal
configuration, descriptors, etc.

For more information about the four (vendor specific)
configuration maps and the diode matrix see the
application documentation.

C

ONFIGURATION OPTIONS OF THE UDA1321 VIA AN I

2

C-BUS

EEPROM
If an EEPROM is detected (reading byte 0 as AAH and

byte 1 as 55H), the UDA1321 will use the configuration
map in the EEPROM instead of one of four configuration
maps. The layout of the configuration map is fixed, the
values (except bytes 0 and 1) are user definable (see
Table 6). If the user wants to change these values
(the manufacturers name for instance), this can be
achieved via the EEPROM code.

The communication between the UDA1321 and the
external I2C-bus device is based on the standard I2C-bus
protocol given in the Philips specification

“The I2C-bus and

how to use it (including specifications)”

, which can be
ordered using the code 9398 393 40011. The I2C-bus has
two lines: a clock line SCL and a serial data line SDA
(see Fig.7).

1998 Oct 06 19

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)

Digital-to-Analog Converter (DAC)

UDA1321

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MBC611

P

S

Sr

P

t

SU;STO

t

SP

t

HD;STA

t

SU;STA

t

SU;DAT

t

f

t

HIGH

t

r

t

HD;DAT

t

LOW

t

HD;STA

t

BUF

SDA

SCL

Fig.7 Definition of timing of the I2C-bus.

1998 Oct 06 20

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Table 6 Control options for the UDA1321 via the EEPROM configuration map; note 1

BYTE
(HEX)

REGISTER

NAME

COMMENTS BIT VALUE

0 − recognition pattern; do not change it AAH
1 − recognition pattern; do not change it 55H
2 ASR control register robust word clock 7 0 = off

1=on

serial I

2

S-bus output format 6 and 5 00 = I2S-bus

01 = 16-bit LSB
10 = 18-bit LSB
11 = 20-bit LSB

phase inversion 4 0 = mono phase inversion off

1 = mono phase inversion on

bits per sample modi 3 and 2 00 = reserved

01 = 8-bit audio
10 = 16-bit audio
11 = 24-bit audio

audio mode 1 0 = mono

1 = stereo

ASR register start-up mode 0 0 = stop

1=go

3 ADAC mode register 0 selection ADAC mode register 7 0

audio feature mode 6 and 5 00 = flat

01 = minimum
10 = minimum
11 = maximum

de-emphasis 4 0 = de-emphasis off

1 = de-emphasis on

channel manipulation 3 0 = L ⇒ L, R ⇒ R

1=L⇒R, R ⇒ L

synchronous/asynchronous control 2 0 = asynchronous

1 = synchronous

mute control 1 0 = no mute

1 = mute active

reset ADAC 0 0 = no reset ADAC

1 = reset ADAC

1998 Oct 06 21

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

4 ADAC mode register 1 selection ADAC mode register 7 1

digital PLL lock speed 6 and 5 00 = lock after 512 samples

01 = lock after 2048 samples
10 = lock after 4096 samples
11 = lock after 16384 samples

digital PLL lock mode 4 0 = adaptive

1 = fixed

digital PLL mode 3 and 2 00 = adaptive

01 = fixed state 1
10 = fixed state 2
11 = fixed state 3

serial I

2

S-bus input format 1 and 0 00 = I2S-bus

01 = 16-bit LSB
10 = 18-bit LSB
11 = 20-bit LSB

5 I/O selection register clipping 7 0 = clipping prevention off

1 = clipping prevention on

I

2

S-bus usage 6 0 = no I2S-bus used

1=I2S-bus used

4/6 pins I

2

S-bus (see Section “The

general purpose pins (GP0 to GP5)”)

5 only if I2S-bus is used;

0 = 4 pins I2S-bus
1 = 6 pins I2S-bus

GP4 4 0 = function 1

1 = function 2
(see Tables 7, 8 and 9)

GP3 3
GP2 2
GP1 1

GP0 0
6 GP0 Usage Page if HID selected
7 GP0 Usage if HID selected
8 reserved
9 reserved
A GP3 Usage Page if HID selected
B GP3 Usage if HID selected
C reserved
D reserved
E GP4 Usage Page if HID selected
F GP4 Usage if HID selected

10 reserved

BYTE
(HEX)

REGISTER

NAME

COMMENTS BIT VALUE

1998 Oct 06 22

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

11 GP1 and GP2 outputs

definition register

reserved 7

reserved 6

application GP2 function 2 5 0 = HID output 2

1 = LED output 2 (activated
when DBB is active)

application GP1 function 2 4 0 = HID output 1

1 = LED output 1 (activated
when mute is active)

polarity GP2 function 1 3 normal or inversed output

functionality:
0 = according Table 7
1 = inversed

polarity GP1 function 1 2

polarity GP2 function 2 1

polarity GP1 function 2 0

12 GP1 Usage Page if HID selected
13 GP1 Usage if HID selected
14 GP2 Usage Page if HID selected
15 GP2 Usage if HID selected
16 time between releasing standby and

enabling the audio output; steps of

20 ms

17 time between ‘no isochronous data

present’ and activating the mute

output; steps of 1 s (only applicable for

function 1, no digital I/O

communication)

18 time between activating the mute

output and activating the standby

output; steps of 5 s (only applicable for

function 1, no digital I/O

communication); when filled-in with

zero, standby will not be activated

19 default bass boost value on top of

Bass USB DAC for Dynamic Bass

Boost (DBB); see Table 5

bass boost = register value; if
bass boost + Bass USB DAC
is larger then the maximum
value of T able 5, the maximum
value is used (no bass boost

in flat mode)
1A default volume value of USB DAC volume = −register value
1B idVendor high byte
1C idVendor low byte
1D idProduct high byte
1E idProduct low byte

1F bmAttributes
20 maximum power steps of 2 mA with

maximum 500 mA

BYTE
(HEX)

REGISTER

NAME

COMMENTS BIT VALUE

1998 Oct 06 23

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Notes

1. An extensive description of the USB control options is available in the

“USB Device Class Definition for Audio

Devices”

.

2. The serial number is only supported in the external configuration map and not in the four internal configuration maps.

The general purpose pins (GP0 to GP5)

The UDA1321 has 6 General Purpose (GP) pins; these are pins GP0 to GP5. These can be used either for digital I/O
functions or for general purposes. The configurations presented are as implemented in the standard firmware.

There are basically three port configurations:

• No digital I/O communication

• 4-pins digital I/O communication

• 6-pins digital I/O communication.

These port configurations can be selected via the configuration map at start-up of the UDA1321.
The user can make a selection between two functions for each of the pins GP0 to GP4 (see byte 5 in Table 6), except if

digital I/O communication is selected (see Tables 7, 8 and 9).

21 wTerminalType high byte
22 wTerminalType low byte
23
24
25 pointer language string 32
26 pointer manufacturer string 36
27 pointer product string 46
28 pointer serial number 54

32 ⇒ language string
36 ⇒− manufacturer string
46 ⇒− product string
54 ⇒− serial number; note 2

BYTE
(HEX)

REGISTER

NAME

COMMENTS BIT VALUE

1998 Oct 06 24

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Table 7 No digital I/O communication

Notes

1. The input pins must have a pull-up resistor.

2. Connect/disconnect: holds the USB ‘disconnected’ as long as the initialization is not finished.

3. Alarm mute: input to switch the sound off; specially used if the USB host program does not respond to the control.This
pin acts directly on the sound and passes the mute to the USB host.

4. Standby is switched on (output becomes LOW) after a programmable time if mute is active (see Byte 18 of Table 6).

5. Mute is switched on (output becomes LOW) after a programmable time if the isochronous data flow is interrupted
(see Byte 17 of Table 6).

6. For selection between HID/LED application see configuration map byte 11 (output is active HIGH).

Table 8 4-pins digital I/O communication

Notes

1. Connect/disconnect: holds the USB ‘disconnected’ as long as the initialization is not finished.

2. Alarm mute: input to switch the sound off; specially used if the USB host program does not respond to the control.
This pin acts directly on the sound and passes the mute to the USB host.

PIN INPUT/OUTPUT FUNCTION 1 FUNCTION 2

GP5 output; not programmable; note 2 connect/disconnect connect/disconnect
GP4 inputs; programmable; note 1 alarm mute; note 3 HID input 3
GP3 HID input 2 HID input 2
GP0 HID input 1 HID input 1
GP2 outputs; programmable standby; note 4 HID/LED output 2; note 6
GP1 mute; note 5 HID/LED output 1; note 6

PIN INPUT/OUTPUT FUNCTION 1 FUNCTION 2

GP5 output; not programmable; note 1 connect/disconnect connect/disconnect
GP4 digital I/O-bus BCKO BCKO
GP3 WSO WSO
GP2 DO DO
GP1 DI DI
GP0 input; programmable HID input 1 alarm mute; note 2

1998 Oct 06 25

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Table 9 6-pins digital I/O communication

Filter characteristics

The overall filter characteristic of the UDA1321 in flat mode is given in Fig.8. The overall filter characteristic of the
UDA1321 includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the FSDAC
(f

s

= 44.1 kHz).

DSP extension port

An external DSP can be used for adding extra sound processing features via the digital I/O-bus. The UDA1321 supports
the standard I

2

S-bus data protocol and the LSB-justified serial data input format with word lengths of 16, 18 and 20 bits.
Using the 4-pins digital I/O-bus the UDA1321 device acts as a master, controlling the BCK and WS signals. The period
of the WS signal is determined by the number of samples in the 1 ms frame of the USB. This implies that the WS signal
does not have a constant period time, but is jittery. Using the 6-pins digital I/O-bus GP2, GP3 and GP4 are the output
pins (master) and GP0, GP1 and GP5 are the input pins (slave).

For characteristic timing of the I2S-bus input interface see Figs 9 and 10.

PIN INPUT/OUTPUT FUNCTION

GP5 digital I/O-bus WSI
GP4 BCKO
GP3 WSO
GP2 DO
GP1 DI
GP0 BCKI

1998 Oct 06 26

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Fig.8 Overall filter characteristics of the UDA1321.

handbook, full pagewidth

MGM110

volume

(dB)

f (kHz)

10 20 30 40 50 60 70 80 90 1000

−160

−120

−80

−40

−140

−100

−60

−20

−0

Fig.9 Timing of digital I/O input signals.

handbook, full pagewidth

MGK003

WS

RIGHT

LSB MSB

LEFT

BCK

DATA

t

f

t

r

t

h;WS

t

s;WS

t

BCK(H)

t

BCK(L)

T

cy

t

s;DAT

t

h;DAT

1998 Oct 06 27

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)

Digital-to-Analog Converter (DAC)

UDA1321

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LSB-JUSTIFIED FORMAT 16 BITS

LSB-JUSTIFIED FORMAT 18 BITS

LSB-JUSTIFIED FORMAT 20 BITS

LEFT

LEFT

LEFT

RIGHT

RIGHT

RIGHT

2

215161718 1

1516 1

MSB LSBB2

MSB B2 B3 B4

B15

LSB

B17

215161718 1

MSB B2 B3 B4

LSB

B17

2151617181920 1

MSB B2 B3 B4 B5 B6

LSB

B19

2151617181920 1

MSB B2 B3 B4 B5 B6

LSB

B19

21516 1

MSB LSBB2 B15

WS

LEFT

RIGHT

321321

MSB B2 MSBLSB LSB MSBB2

>=8 >=8

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

INPUT FORMAT I

2

S-BUS

MGK002

Fig.10 Input formats.

1998 Oct 06 28

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

2. Equivalent to discharging a 200 pF capacitor through a 2.5 µH series inductor and a 25 Ω resistor.

For pin V

DDO

the electrostatic handling is limited to 250 V.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

All digital I/Os

V

I/O

DC input/output voltage range −0.5 − V

DD

V

I

O

output current −−4mA

Temperature

T

j

junction temperature 0 − 125 °C

T

stg

storage temperature −55 − +150 °C

T

amb

operating ambient temperature 0 25 70 °C

Electrostatic handling

V

es

electrostatic handling note 1 −3000 − +3000 V

note 2 −300 − +300 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air

QFP64 48 K/W
SDIP32 57 K/W
SO28 65 K/W

1998 Oct 06 29

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

RECOMMENDED OPERATING CONDITIONS

DC CHARACTERISTICS

V

DD

= 3.3 V; VSS=0V; T

amb

=25°C; f

osc

= 48 MHz; fs= 44.1 kHz; unless otherwise specified.

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DD

supply voltage 3.0 3.3 3.6 V

V

I

DC input voltage for D+ and D− 0.0 − V

DD

V

V

I/O

DC input voltage for the digital I/Os 0.0 − V

DD

V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDE

digital supply voltage I/O pins 3.0 3.3 3.6 V

V

DDI

digital supply voltage core 3.0 3.3 3.6 V

V

DDA

analog supply voltage 3.0 3.3 3.6 V

V

DDO

operational amplifier supply voltage 3.0 3.3 3.6 V

V

DDX

crystal oscillator supply voltage 3.0 3.3 3.6 V

I

DDE

digital supply current I/O pins note 1 − 3 − mA

I

DDI

digital supply current core − 36 − mA

I

DDA

analog supply current − 4.2 − mA

I

DDO

operational amplifier supply current − 4.0 − mA

I

DDX

crystal oscillator supply current − 2.1 15.0

(2)

mA

P

tot

total power dissipation − 165 − mW

P

tot(ps)

total power dissipation in
power-save mode

note 3 − 60 − mW

Inputs/outputs D+ and D−

V

I

static DC input voltage −0.5 − V

DDI

V

V

OH

static DC output voltage HIGH RL=15kΩ to ground 2.8 − V

DDI

V

V

OL

static DC output voltage LOW RL= 1.5 kΩ to 3.6 V −−0.3 V

ILO high impedance state data line

output leakage current

−−10 µA

∆V

I(dif)

differential input sensitivity 0.2 −− V

V

CM(dif)

differential common mode voltage 0.8 − 2.5 V

V

SE(RX)th

single-ended receiver threshold
voltage

0.8 − 2.0 V

C

I(TRX)

transceiver input capacitance pin to ground −−20 pF

Digital inputs/outputs

V

IL

LOW-level input voltage −−0.3V

DDI

V

V

IH

HIGH-level input voltage 0.7V

DDI

− V

DDI

V

V

OL

LOW-level output voltage −−0.4 V

V

OH

HIGH-level output voltage V

DDI

− 0.4 −− V

I

LI

 input leakage current −−1µA

C

i

input capacitance pin to ground −−5pF

1998 Oct 06 30

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Notes

1. This value depends strongly on the application. The specified value is the typical value obtained using the application

as given in Fig.12.

2. At start-up of the oscillator.

3. The power-save mode (power management) is not supported in the UDA1321/N101;

see Chapter “USB-DAC UDA1321/N101 (Firmware sw 2.1.1.7)”.

Filter stream DAC

V

ref

reference voltage − 0.5V

DDA

− V

V

o(cm)

common mode output voltage − 0.5V

DDA

− V

R

o

output resistance at pins VOUTL
and VOUTR

− 11 −Ω

R

o(L)

output load resistance 2.0 −− kΩ

C

o(L)

output load capacitance −−50 pF

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1998 Oct 06 31

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

AC CHARACTERISTICS

V

DD

= 3.3 V; VSS=0V; T

amb

=25°C; f

osc

= 48 MHz; fs= 44.1 kHz; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Driver characteristics D+ and D− (full-speed mode)

t

r

rise time CL=50pF 4 − 20 ns

t

f

fall time CL=50pF 4 − 20 ns

t

rf(m)

matching rise/fall time (tr/tf)90−110 %

V

cr

output signal crossover voltage 1.3 − 2.0 V

R

(o)driver

driver output resistance steady-state drive 28 − 43 Ω

Data source timings D+ and D− (full-speed mode)

f

i(sample)

audio sample input frequency 5 − 55 kHz

f

fs(D)

full-speed data rate 11.97 12.00 12.03 Mbits/s

t

fr

frame interval 0.9995 1.0000 1.0005 ms

t

J1(dif)

source differential jitter to next
transition

−3.5 0.0 +3.5 ns

t

J2(dif)

source differential jitter for paired
transitions

−4.0 0.0 +4.0 ns

t

W(EOP)

source End Of Packet (EOP) width 160 − 175 ns

t

EOP(dif)

differential to EOP transition skew −2.0 − +5.0 ns

t

JR1

receiver data jitter tolerance to next
transition

−18.5 0.0 +18.5 ns

t

JR2

receiver data jitter tolerance for
paired transitions

−9.0 0.0 +9.0 ns

t

EOPR1

EOP width at receiver must reject as
EOP

40 −− ns

t

EOPR2

EOP width at receiver must accept
as EOP

82 −− ns

Serial input/output data timing; see Fig.9
f

clk(sys)

system clock frequency − 12 − MHz

f

i(WS)

word select input frequency 5 − 55 kHz

t

r

rise time −−20 ns

t

f

fall time −−20 ns

t

BCK(H)

bit clock HIGH time 55 −− ns

t

BCK(L)

bit clock LOW time 55 −− ns

t

s;DAT

data set-up time 10 −− ns

t

h;DAT

data hold time 20 −− ns

t

s;WS

word select set-up time 20 −− ns

t

h;WS

word select hold time 10 −− ns

1998 Oct 06 32

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

SDA and SCL lines (standard I2C-bus); see Fig.7
f

SCL

SCL clock frequency 0 − 100 kHz

t

BUF

bus free time between a STOP
and START condition

4.7 −− µs

t

HD;STA

hold time (repeated) START
condition

4.0 −− µs

t

LOW

SCL LOW time 4.7 −− µs

t

HIGH

SCL HIGH time 4.0 −− µs

t

SU;STA

set-up time for a repeated START
condition

4.7 −− µs

t

SU;STO

set-up time for a STOP condition 4.0 −− µs

t

HD;DAT

data hold time 5.0 − 0.9 µs

t

SU;DAT

data set-up time 250 −− ns

t

r

rise time of both SDA and SCL
signals

−−1000 ns

t

f

fall time of both SDA and SCL
signals

−−300 ns

C

L(bus)

load capacitance for each bus line −−400 pF
Oscillator; note 1
f

osc

oscillator frequency − 48 − MHz
δ duty factor − 50 − %
g

m

transconductance 13.5 23.0 30.5 mS
R

o

output resistance 450 700 1450 Ω
C

i(XTAL1)

parasitic input capacitance at XT AL1 10 11 12 pF
C

i(XTAL2)

parasitic input capacitance at XT AL2 4.5 5.0 5.5 pF
I

start

start current 4.3 8.8 15.0 mA

Power-on reset

t

su(POR)

power-on reset set-up time notes 2 and 3 5C

ref

−− ms

Filter Stream DAC (FSDAC)

RES resolution 16 −− bits
V

o(FS)(rms)

full-scale output voltage

(RMS value)

VDD= 3.3 V − 0.66 − V

SVRR supply voltage ripple rejection of

V

DDA

and V

DDO

f

ripple

= 1 kHz;

V

ripple(p-p)

= 0.1 V

− 60 − dB

∆V

o

 channel unbalance maximum volume − 0.03 − dB

α

ct

crosstalk between channels RL=5kΩ−95 − dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1998 Oct 06 33

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Notes

1. A 3rd overtone crystal of 48 MHz must be used in combination with a filter connected to the oscillator output (XTAL2),
(L = 1.5 µH ±10%; C = 10 nF ±10%). The series resistance of the crystal must be below 60 Ω. C

xtal1

= 4.7 pF ±10%;

C

xtal2

=12pF±10%).

2. Strongly depends on the external decoupling capacitor connected to V

ref

.

3. Use for calculation of the power-on reset set-up time the C

ref

value in µF.

4. The audio information from the USB interface is fed directly to the ADAC.

APPLICATION INFORMATION

The UDA1321 is designed to be used as a self-powered device.
The I

2

C-bus EEPROM is optional and can be used e.g. to program your own Vendor ID and Product ID. In order to help
customers with defining there own configuration map, a special program called ‘Configuration map editor’ has been
developed. It is available from your local Philips Semiconductors Field Application Engineer.

More information about the firmware, descriptors and configurations can be obtained from several application notes.

(THD + N)/S total harmonic distortion-plus-noise

to signal ratio

fs= 44.1 kHz;
RL=5kΩ

at input signal of
1 kHz (0 dB)

−−90

(4)

−80 dB

− 0.0032 0.01 %

at input signal of
1 kHz (−60 dB)

−−30

(4)

−20 dB

− 3.2 10 %

S/N

bz

signal-to-noise ratio at bipolar zero A-weighted at

code 0000H

90 95 − dBA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1998 Oct 06 34

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

USB-DAC UDA1321/N101 (FIRMWARE SW 2.1.1.7)

The following items are different for the UDA1321/N101 compared to the general content of this data sheet:

• Volume control

• Treble control

• Power management.

Table 10 Volume control characteristics

The treble control is available for the master channel of the UDA1321. Treble can be regulated in three modes: minimum,
flat and maximum mode. The preferred mode is selected via the configuration map. The corner frequency is 3000 Hz for
the minimum mode and 1500 Hz for the maximum mode. The treble range is from 0 to 6 dB (discrete steps
0, 4 and 6 dB). It should be noted that the negative treble values as defined in the

“USB Device Class Definition for Audio

Devices”

are not supported by the UDA1321; the 0 dB value is returned as 0 dB. Table 4 gives the mapping of the

bTreble value upon the actual treble setting of the USB DAC.

wVOLUME

VOLUME USB SIDE

(dB)

VOLUME USB DAC

(dB)

B15 B14 B13 B12 B11 B10 B9 B8

00000000 0 0
11111111 0 0
11111110 −1 −1
11111101 −2 −2
11111100 −3 −3
11111011 −4 −4
11111010 −5 −5
11111001 −6 −6
11111000 −7 −7
11110111 −8 −8
11110110 −9 −9

... ... ... ... ... ... ... ... ... ...

11000101 −58 −58
11000100 −59 −59
11000011 −60 −60
11000010 −61 −∞
11000001 −62 −∞

... ... ... ... ... ... ... ... ... ...

10000000 −∞ −∞

1998 Oct 06 35

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Table 11 Treble control characteristics

The power saving mode is not supported (no power management).
The content of the four internal configuration maps is written in the

‘sw 2.1.1.7 configuration maps’

document. This

document is available at your local Philips Semiconductors Field Application Engineer.

bTREBLE

TREBLE USB

SIDE (dB)

TREBLE USB DAC (dB)

B7 B6 B5 B4 B3 B2 B1 B0 minimum flat maximum

0 0 0 0 0 0 0 0 0.00 0 0 0
0 0 0 0 0 0 0 1 0.25
0 0 0 0 0 0 1 0 0.50
0 0 0 0 0 0 1 1 0.75
0 0 0 0 0 1 0 0 1.00
0 0 0 0 0 1 0 1 1.25 4 0 4
0 0 0 0 0 1 1 0 1.50
0 0 0 0 0 1 1 1 1.75
0 0 0 0 1 0 0 0 2.00
0 0 0 0 1 0 0 1 2.25
0 0 0 0 1 0 1 0 2.50
0 0 0 0 1 0 1 1 2.75
0 0 0 0 1 1 0 0 3.00
0 0 0 0 1 1 0 1 3.25 6 0 6

...

0 0 0 1 0 1 0 1 5.25 6 0 6

...

0 0 0 1 1 1 0 1 7.25 6 0 6

...

0 0 1 0 0 1 0 1 9.25 6 0 6

...

0 1 1 1 1 1 1 1 31.75 6 0 6

1998 Oct 06 36

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

APPLICATION DIAGRAM

handbook, full pagewidth

64

GP0/BCKI

2

GP5/WSI

7

GP1/DI

17

D−

20

D+

32

V

DDE

30

V

SSE

25

V

DDI

29

4544

V

SSI

UDA1321H

+V

D

100 nF

(63 V)

100 nF

(63 V)

C17

C18

1 Ω
R17

L12
BLM32A07

+V

C

+V

D

+V

C

+V

A

100 nF

(63 V)

100 nF
(63 V)

C15

C16

1 Ω
R16

L11
BLM32A07

BLM32A07

4.7 pF
(50 V)

C13

12 pF

(63 V)

C6

+V

A

100 nF

(63 V)

47 µF
(16 V)

C8

C14

R15
1 Ω

+V

C

37

XTAL1

38

XTAL2

R9

1.5 kΩ
R14

22 Ω

R13

22 Ω

P5

digital

input

BCK

WS

DI

C4
22 pF
(63 V)

C5
22 pF
(63 V)

C26
10 nF
(50 V)

1

L9

8

2

7

3

6

45

V

DDA

V

SSA

10 nF

(63 V)

C7

L10

1.5 µH

C1
100 µF
(16 V)

C2
100 µF
(16 V)

C3
100 µF
(16 V)

10 nF

(50 V)

C27

X1 48 MHz

L15

BLM32A07

L14

BLM32A07

L16

V

D(ext)

(2)

V

A(ext)

(1)

GND

MGM842

4

3

2

1

Fig.11 Application diagram QFP64 (continued in Fig.12).

(1) BLM32A07.
(2) V

D(ext)

can be connected to 5 V max. (5 V tolerant I/O).

1998 Oct 06 37

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Fig.12 Application diagram QFP64 (continued from Fig.11).

(1) BLM32A07.

handbook, full pagewidth

MGM843

56

P0.0

57

P0.1

58

P0.2

59

P0.3

60

P0.4

62

P0.5

63

P0.6

5

P0.7

9

ALE

11

P2.0

12

P2.1

18

P2.2

19

P2.3

21

P2.4

22

P2.5

4

SDA

3

SCL

8

PSEN

18

D7

17

D6

14

D5

1

A0

2

A1

3

A2

4

V

SS

8

V

DD

7

PTC

6

SCL

5

SDA

13

D4

8

D3

7

D2

4

D1

3

D0

11

LE

14
13
10

39

61

RTCB

55

TC

15

SHTCB

V

DDX

36

V

SSX

51

V

DDO

49

V

SSO

1

19
16
15
12

9
6
5
2

20

10

OE

Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
V

CC

GND

74HCT373D

D3

D2

D4

UDA1321H

PCX8582X-2

10

A0

9

A1

8

A2

7

A3

6

A4

4

A6

5

A5

3

A7

24

A9

25

A8

21

A10

2

11
12
13
15
16
17
18
19

28

14

A12

23

A11

O0
O1
O2
O3
O4
O5
O6
O7

V

CC

EEPM27128

26

A13

22

OE

6

EA

20

CE

27

PGM

GND

1

V

PP

+V

D

+V

D

+V

D

C25

100 nF
(50 V)

+V

D

C24

100 nF
(50 V)

+V

C

100 nF

(63 V)

100 nF

(63 V)

C28

C21

1 Ω
R19

L13
BLM32A07

+V

A

100 nF

(63 V)

47 µF
(16 V)

C9

C19

1 Ω
R18

42

V

REF

53

VOUTL

R6
10 kΩR710 kΩ

+VD

P8

SDA
SCL

1
2

C10

R8

4.7 kΩ

R20

1 Ω

audio
output

47 µF

(16 V)

C11

47 µF

(16 V)

46

VOUTR

C12
47 µF
(16 V)

C22
100 nF
(63 V)

C23
100 nF
(63 V)

+V

D

1

2

3

J1

GP4/BCKO
GP3/WSO
GP2/DO

BCK
WS

DO

digital
output

(I2C-bus)

(internal ROM
external ROM)

1998 Oct 06 38

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)

Digital-to-Analog Converter (DAC)

UDA1321

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h

andbook, full pagewidth

MGM844

24 (27)

7

(8)

V

DDI

8

(9)

V

SSI

25 (29)
28 (32)

5 (6)
6 (7)

22pF22

pF

GP0/BCKI

GP5/WSI

(31) 27

(18) 15

SDA

V

ref

(23) 20

V

DDO

(22)19

V

SSO

(30) 26

SCL

GP1/DI

BCK

digital

input

WS

DI

D−7

+3.3 V

D+

8

6
5

10
nF

10 nF

L6

(1)

1.5
kΩ

22 Ω
22 Ω

100 nF

100 nF

1 Ω

10

(11)

V

DDE

9

(10)

V

SSE

(1)

100 nF

100 nF

1 Ω

14

(16)

V

DDX

11

(13)

V

SSX

(1)

100 nF

100 nF

100 nF

1 Ω

1 Ω

100 µF

+3.3 V

+3.3 V

1

V

DD

8

A0

2

PTC

7

A1

3

SCL

6

A2

4

SDA

5

V

SS

10

kΩ

+3.3 V

10
kΩ

PCX8582X-2

100nF4.7

µF

(24) 21

VOUTL

47 µF

LEFT

(21) 18

VOUTR

47 µF

RIGHT

100 nF

1 Ω

+3.3 V

(20) 17

V

DDA

(19) 16

V

SSA

100 nF

1 Ω

+3.3 V

(1) 1

GP2/DO

(2) 2

GP3/WSO

(3) 3

GP4/BCKO

(4) 4

SHTCB

(25) 22

TC

(26) 23

RTCB

BCK

digital

output

WS
DO

10 nF

13 (15)

12 (14)

XTAL2

XTAL1

1.5 µH

12 pF

4.7 pF

48 MHz

UDA1321T

(UDA1321PS)

1
2
3
4

1

X4

2
3
4

(I2C-bus)

Fig.13 Application diagram SO28 and SDIP32.

Pin numbers in parenthesis represent the UDA1321PS.
(1) BLM32A07.

1998 Oct 06 39

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

PACKAGE OUTLINES

UNIT A1A2A3bpcE

(1)

eH

E

LL

p

Zywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.25

0.05

2.90

2.65

0.25

0.50

0.35

0.25

0.14

14.1

13.9

1

18.2

17.6

1.2

0.8

7
0

o
o

0.2 0.10.21.95

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

1.0

0.6

SOT319-2

95-02-04
97-08-01

D

(1) (1)(1)

20.1

19.9

H

D

24.2

23.6

E

Z

1.2

0.8

D

e

θ

E

A

1

A

L

p

detail X

L

(A )

3

B

19

y

c

E

H

A

2

D

Z

D

A

Z

E

e

v M

A

1

64

52

51 33

32

20

X

pin 1 index

b

p

D

H

b

p

v M

B

w M

w M

0 5 10 mm

scale

QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

SOT319-2

A

max.

3.20

1998 Oct 06 40

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

UNIT

A

max.

A

1

A

2

A3b

p

cD

(1)E(1) (1)

eHELLpQ

Z

ywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

2.65

0.30

0.10

2.45

2.25

0.49

0.36

0.32

0.23

18.1

17.7

7.6

7.4

1.27

10.65

10.00

1.1

1.0

0.9

0.4

8
0

o
o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.1

0.4

SOT136-1

X

14

28

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

c

L

v M

A

e

15

1

(A )

3

A

y

0.25

075E06 MS-013AE

pin 1 index

0.10

0.012

0.004

0.096

0.089

0.019

0.014

0.013

0.009

0.71

0.69

0.30

0.29

0.050

1.4

0.055

0.419

0.394

0.043

0.039

0.035

0.016

0.01

0.25

0.01

0.004

0.043

0.016

0.01

0 5 10 mm

scale

SO28: plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

95-01-24
97-05-22

1998 Oct 06 41

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

UNIT b

1

cEe M

H

L

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

DIMENSIONS (mm are the original dimensions)

SOT232-1

92-11-17
95-02-04

b

max.

w

M

E

e

1

1.3

0.8

0.53

0.40

0.32

0.23

29.4

28.5

9.1

8.7

3.2

2.8

0.181.778 10.16

10.7

10.2

12.2

10.5

1.6

4.7 0.51 3.8

M

H

c

(e )

1

M

E

A

L

seating plane

A

1

w M

b

1

e

D

A

2

Z

32

1

17

16

b

E

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

(1) (1)

D

(1)

Z

A

max.

12

A

min.

A

max.

SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)

SOT232-1

1998 Oct 06 42

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(order code 9398 652 90011).

SDIP

S

OLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

QFP and SO

REFLOW SOLDERING
Reflow soldering techniques are suitable for all QFP and

SO packages.
The choice of heating method may be influenced by larger

plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body.

For details, refer to the Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages;
Section: Packing Methods”

.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

W

AVE SOLDERING

QFP

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

SO

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

1998 Oct 06 43

Philips Semiconductors Preliminary specification

Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)

UDA1321

Method (QFP and SO)

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

2

C COMPONENTS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

2

C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
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South America: Al. Vicente Pinzon, 173, 6th floor,
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Spain: Balmes 22, 08007 BARCELONA,
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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
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Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
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Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
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Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: seeAustria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone]

Printed in The Netherlands 545102/750/04/pp44 Date of release: 1998 Oct 06 Document order number: 9397 750 04262