Datasheet UDA1320ATS Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UDA1320ATS

Low-cost stereo filter DAC

Preliminary specification
File under Integrated Circuits, IC01

1999 Oct 11

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

CONTENTS

1 FEATURES

1.1 General

1.2 Multiple format input interface

1.3 DAC digital sound processing

1.4 Advanced audio configuration
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 ORDERING INFORMATION
5 QUICK REFERENCE DATA
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION

8.1 System clock

8.2 Application modes

8.3 Multiple format input interface

8.4 Static pin mode

8.5 Pin compatibility

8.6 Interpolation filter (DAC)

8.7 Noise shaper

8.8 Filter-Stream DAC
9 L3 INTERFACE DESCRIPTION

9.1 The L3 interface

9.2 Data transfer mode

9.3 Programming the features
10 LIMITING VALUES
11 HANDLING
12 QUALITY SPECIFICATION
13 THERMAL CHARACTERISTICS
14 DC CHARACTERISTICS
15 AC CHARACTERISTICS

15.1 Analog

15.2 Digital
16 APPLICATION INFORMATION
17 PACKAGE OUTLINE
18 SOLDERING

18.1 Introduction

18.2 Reflow soldering

18.3 Wave soldering

18.4 Repairing soldered joints
19 DEFINITIONS
20 LIFE SUPPORT APPLICATIONS

1999 Oct 11 2

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

1 FEATURES

1.1 General

• Low power consumption.

• 2.7 to 3.6 V power supply.

• Selectable controlvia L3 microcontroller interface or via

static pin control.

• 256, 384 and 512fs system clock (f
the L3 interface or 256 and 384fs clock mode via static
pin control

• supports sampling frequencies from 16kHz to 48kHz.

• Integrated digital filter plus non inverting DAC

Digital-to-Analog Converter (DAC).

• Easyapplication and no analog postfilteringrequiredfor
DAC.

• Slave mode only applications.

• Small package size (SSOP16).

1.2 Multiple format input interface

• I2S-bus, MSB-justified and LSB-justified 16,18 and 20
bits format compatible (in L3-mode).

• I2S-bus and LSB-justified 16,18 and 20 bits format
compatible in static mode.

• 1fs input format data rate.

1.3 DAC digital sound processing

• Digital logarithmic volume control via L3.

• Digital de-emphasis for 32, 44.1 and 48 kHz fs via

L3 or 44.1 kHz fs via static pin control.

• Soft mute via static pin control or via L3 interface.

1.4 Advanced audio configuration

• Stereo line output (under L3 volume control)

• High linearity, wide dynamic range, low distortion.

), selectable via

sys

2 APPLICATIONS

• Portable digital audio equipment, see Fig.8.

• Set-top boxes

3 GENERAL DESCRIPTION

TheUDA1320ATS/N2 is asingle-chip non inverting stereo
DAC employing bitstreamconversion techniques. The low
power consumption and low voltage requirements make
the device eminently suitable for use in digital audio
equipment which incorporates playback functions.

The UDA1320ATS/N2 supports the I2S-bus data format
with word lengths of up to 20 bits, the MSB-justified data
format with word lengths of up to 20 bits and the
LSB-justified serial data format with word lengths of 16,
18 and 20 bits.

The UDA1320ATS/N2 can be used in two modes, either
L3-mode or static pin mode.

In the L3-mode, all digital soundprocessing features must
becontrolled via the L3 interface, includingtheselectionof
the system clock setting.

In the two static-modes, the UDA1320ATS/N2 can be
operated in the 256fs and 384fs system clock mode. The
mute,de-emphasisfor 44.1 kHz and 4 digital inputformats
(I2S and 16, 18, 20 bits LSB formats) can be selected via
static pins. The L3 interface cannot be used in this
application mode, also, volume control is not available in
this mode.

4 ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

UDA1320ATS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

1999 Oct 11 3

PACKAGE

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

5 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DDA

V

DDD

I

DDA

I

DDD

T

amb

DAC

V

o(rms)

(THD + N)/S total harmonic distortion plus

S/N signal-to-noise ratio code = 0; A-weighted − 100 95 dB

α

cs

T

amb

analog supply voltage 2.7 3.3 3.6 V
digital supply voltage 2.7 3.3 3.6 V
DAC supply current − 6.5 − mA
digital supply current − 3.0 − mA
operating ambient temperature −20 − +85

°

C

output voltage (RMS value) note 1, 2 − 1.0 − V

at 0 dB −−90 −85 dB

noise-to-signal ratio

at −60 dB; A-weighted −−38 −35 dB

channel separation − 100 − dB
operating ambient temperature −30 − +85

°

C

Notes

1. the output voltage has been changed with respect to the UDA1320TZ/N1.

2. the output voltage scales linearly with the power supply voltage.

6 BLOCK DIAGRAM

handbook, full pagewidth

BCK

WS

DATAI

SYSCLK

V

O(L)

1
2
3

UDA1320A

6

14

V

DDD

4

DIGITAL INTERFACE

VOLUME/MUTE/DE-EMPHASIS

INTERPOLATION FILTER

NOISE SHAPER

DAC

V

DAC

SSD

5

INTERFACE

CONTROL

7

APPSEL

11

APPL0

10

APPL1

9

APPL2

8

APPL3

16

V

O(R)

13 12

V

DDA

V

SSA

Fig.1 Block diagram.

1999 Oct 11 4

15

V

REF(DAC)

MGM816

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

7 PINNING

SYMBOL PIN

DESCRIPTION

BCK 1 bit clock
WS 2 word select
DATAI 3 data input
V

DDD

V

SSD

SYSCLK 6 system clock: 256f

4 digital power supply
5 digital ground

, 384fs, 512f

s

s

APPSEL 7 application mode select
APPL3 8 application pin 3
APPL2 9 application pin 2
APPL1 10 application pin 1
APPL0 11 application pin 0
V

REF(DAC)

V

DDA

V

O(L)

V

SSA

V

O(R)

12 DAC reference voltage
13 analog supply voltage
14 left output voltage
15 analog ground
16 right output voltage

8 FUNCTIONAL DESCRIPTION

8.1 System clock

The UDA1320ATS/N2 operates in slave mode only. This
means in all applications the system devices must provide
the system clock. The system frequency is selectable and
depends on the mode of operation.

The options are 256fs, 384fs and 512fs for the L3 mode
and 256fsplus 384fsfor the static mode. The system clock
must be locked in frequency to the digital interface input
signals.

The UDA1320ATS/N2 supports sampling frequencies
from 16kHz up to 48kHz

8.2 Application modes

The application mode can be set with the tri-value
APPSEL pin, to L3 mode (APPSEL = V
two static modes (APPSEL = 0.5V
APPSEL = V

). See Table 1 for APPL0 to APPL3 pin

DDD

DDD

) or to either of

SSD

or

functions (active = HIGH).

handbook, halfpage

BCK

WS

DATAI

V

DDD

V

SSD

1
2
3
4

UDA1320A

5
6
7
8

MGM817

16
15
14
13
12
11
10

9

V

O(R)

V

SSA

V

O(L)

V

DDA

V

REF(DAC)

APPL0SYSCLK
APPL1APPSEL
APPL2APPL3

Fig.2 Pin configuration.

Table 1 Selection modes via APPSEL (note 1)

APPSEL

PIN

V

SSD

0.5V
(384fs)

DDD

V

DDD

(256fs)

APPL0 TEST MUTE MUTE
APPL1 L3CLOCK DEEM DEEM
APPL2 L3MODE SF0 SF0
APPL3 L3DATA SF1 SF1

For example, in static pin control mode, the output signal
can be soft muted by setting APPL0 HIGH. De-emphasis
can be switched on for 44.1 kHz by setting APPL1 HIGH.
APPL1 LOW will disable de-emphasis.

Note that when L3 interface is used, an L3 initialisation
must be done when the IC is powered up!

In L3 mode pin APPL0 must be set to LOW.

1999 Oct 11 5

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

8.3 Multiple format input interface

L3 mode:

• I2S-bus with data word length of up to 20 bits

• MSB-justified format with data word length up to 20 bits

• LSB-justified format with data word length of 16,

IMPORTANT: UDA1320ATS/N2 differs from the
UDA1320TZ/N1 with respect to:

• in the static mode 384fs is supported instead of 512fs.

• the output voltage of the DAC. In the UDA1320TZ/N1

this is 800mVrmsat 3.0V, now it is 1Vrms at3.3V power
supply

18 or 20 bits.

8.6 Interpolation filter (DAC)

8.4 Static pin mode

The digital filter interpolates from 1 to 128fs by cascading

The UDA1320ATS/N2 supports the following data input

a recursive filter and a FIR filter, see Table 3.

name formats in the static pin mode (via SF0 and SF1):

• I2S bus with data word length of up to 20 bits

• LSB-justified format with data word length of 16,

18 or 20 bits.

See Table 2, for the static pin codes of the 4 formats,
selectable via SF0 and SF1.

Table 3 Interpolation filter characteristics

ITEM CONDITION VALUE (dB)

Pass-band ripple 0 to 0.45f
Stop band >0.55f

Dynamic range 0 to 0.45f
The UDA1320ATS/N2 also accepts double speed data for
double speed data monitoring purposes.

Table 2 Input format selection using SF0 and SF1

FORMAT SF0 SF1

2

I

S00

LSB-justified 16 bits 0 1

8.7 Noise shaper

The 3rd-order noise shaper operates at 128f
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a
Filter-Stream DAC (FSDAC).

LSB-justified 18 bits 1 0
LSB-justified 20 bits 1 1

8.8 Filter-Stream DAC

s

s

s

±0.1

−50

108

. It shifts

s

The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed. The WS signal
must have 50% duty-factor for all LSB-justified modes.

For BCK and WS holds that the BCK frequency must be
equal or smaller then 64 times WS, or f

=< 64*fWS in

BCK

both L3 and static mode.

8.5 Pin compatibility

InL3 interface mode theUDA1320ATS/N2canbe used on
boards that are designed for the UDA1322. The software
for UDA1322 can be used for the UDA1320ATS/N2 to
control de-emphasis, volume control and mute and also
the status settings like system clock setting andinput data
format.

1999 Oct 11 6

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to be
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter isnot needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.

The output voltage of the FSDAC scales linearly with the
power supply voltage.

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1999 Oct 11 7

handbook, full pagewidth

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

WS

BCK

DATAI

WS

BCK

DATAI

WS

BCK

DATAI

WS

BCK

LEFT

≥8 ≥8

MSB B2 MSBLSB LSB MSBB2

LEFT

1321

≥8 ≥8

MSB B2 MSBLSB LSB MSB B2B2

LEFT

1516 1

MSB LSBB2

LEFT

RIGHT

321321

INPUT FORMAT I

RIGHT

32

MSB-JUSTIFIED FORMAT

2

B15

LSB-JUSTIFIED FORMAT 16 BITS

215161718 1

2

S-BUS

RIGHT

21516 1

MSB LSBB2 B15

RIGHT

215161718 1

DATAI

WS

BCK

DATAI

MSB B2 B3 B4

LEFT

MSB B2 B3 B4 B5 B6

Fig.3 Serial interface; input format I2S-bus.

LSB

B17

LSB-JUSTIFIED FORMAT 18 BITS

2151617181920 1

LSB

B19

LSB-JUSTIFIED FORMAT 20 BITS

MSB B2 B3 B4

RIGHT

MSB B2 B3 B4 B5 B6

B17

B19

LSB

2151617181920 1

LSB

MBK071

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

9 L3 INTERFACE DESCRIPTION

9.1 The L3 interface

The following system and digital sound processing
features can be controlled in the microcontroller mode of
the UDA1320ATS/N2:

• System clock frequency

• Data input format

• De-emphasis for 32 kHz, 44.1 kHz and 48 kHz

• Volume

• Soft mute.

Theexchange of dataand control information betweenthe
microcontrollerand the UDA1320ATS/N2 isaccomplished
through a serial hardware interface comprising the
following pins:

• L3DATA

• L3MODE

• L3CLOCK.

Information transfer through the microcontroller bus is
organized in accordance with the L3 format, in which two
differentmodesofoperationcanbedistinguished; address
mode and data transfer mode (see Figs 4 and 6).

The address mode is required to select a device
communicating via the L3 bus and to define the
destination registers for the data transfer mode.

Data transfer can only be in one direction, consisting of
input to the UDA1320ATS/N2 to program sound
processing and other functional features.

Data bits 7 to 2 represent a 6-bit device address, bit 7
being the MSB. The address of the UDA1320ATS/N2 is
000101 (bit 7 to bit 2). If the UDA1320ATS/N2 receives a
different address, it will deselect its microcontroller
interface logic.

9.2 Data transfer mode

The selected address remains active during subsequent
data transfers until the UDA1320ATS/N2 receives a new
address command. The fundamental timing of data
transfers is essentially the same as in the address mode,
see Fig.6. The maximum input clock and data rate is 64 fs.
All transfers are by 8-bit bytes. Data will be stored in the
UDA1320ATS/N2 after reception of a complete byte. See
Fig.5 for a multi-byte transfer.

Table 4 Selection of data transfer

BIT 1 BIT 0 TRANSFER

0 0 DATA (volume, de-emphasis, mute)
0 1 not used
1 0 STATUS (system clock frequency,

data input format)

1 1 not used

handbook, full pagewidth

L3MODE

L3CLCK

L3DATA

t

h(L3)A

t

BIT 0

su(L3)A

t

su(L3)DA

t

CLK(L3)L

t

CLK(L3)H

Fig.4 Timing address mode.

1999 Oct 11 8

t

h(L3)DA

t

su(L3)A

t

h(L3)A

T

cy(CLK)(L3)

BIT 7

MBK072

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

t

handbook, full pagewidth

L3MODE

L3CLK

L3DATA

stp(L3)

handbook, full pagewidth

L3MODE

L3CLCK

L3DATA

write

t

t

su(L3)D

stp(L3)

address

t

h(L3)DA

BIT 0

Fig.5 Multi-byte transfer.

t

CLK(L3)L

t

CLK(L3)H

t

su(L3)DA

T

cy(CLK)L3

addressdata byte #1 data byte #2

BIT 7

t

h(L3)D

t

h(L3)DA

MBK074

t

stp(L3)

MBK073

Fig.6 Timing for data transfer mode.

The sound feature values are stored in independent
registers. The first selection of the registers is achieved by
the choice of data type that is transferred (‘STATUS’ or
‘DATA’ transfer). This is performed in the address mode
usingbit 1 and bit 0,see Table 4,.The settings thatcanbe
controlled with ‘STATUS’ transfer are given in table5, and

1999 Oct 11 9

the settings that can be controlled using ‘DATA’ transfer
are given in table 6.

The second selection is performed by the 2 MSBs of the
data byte (bit 7 and bit 6). The other bits in the data byte
(bit 5 to bit 0) is the value that is placed in the selected
registers.

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

Table 5 Data transfer of type ‘status’

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED

0 0 SC1 SC0 IF2 IF1 IF0 0 System Clock frequency (1 : 0);

data Input Format (2 : 0)

10000000reserved

Table 6 Data transfer of type ‘data’

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED

0 0 VC5 VC4 VC3 VC2 VC1 VC0 Volume Control (5 : 0)
01000000reserved
1 0 0 DE1 DE0 MT 0 0 DE-emphasis (1 : 0); MuTe
11000001default setting

9.3 Programming the features

When the data transfer of type ‘STATUS’ is selected, the
features SYSTEM CLOCK FREQUENCY and DATA
INPUT FORMAT can be controlled.

System clock frequency: a 2-bit value to select the used
external clock frequency.

Table 7 System clock settings

SC1 SC0 FUNCTION

0 0 512f
0 1 384f
1 0 256f

s
s
s

1 1 not used

Data input format: a 3-bit value to select the data format.

Table 8 Data input format settings

IF2 IF1 IF0 FUNCTION

2

000I

Sbus
0 0 1 LSB-justified, 16 bits
0 1 0 LSB -justified, 18 bits
0 1 1 LSB-justified, 20 bits
1 0 0 MSB-justified
1 0 1 not used
1 1 0 not used
1 1 1 not used

When the data transfer of type ‘DATA’ is selected, the
features VOLUME, DE-EMPHASIS and MUTE can be
controlled.

Volume control: a 6-bit value to program the volume
attenuation (VC5 to VC0), 0 to −∞ dB in steps of 1 dB.

Table 9 Volume settings

VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)

000000 0
000001 0
000010 −1
000011 −2

:::::: :
111101 −60
111111 −∞

De-emphasis: a 2-bit value to enable the digital
de-emphasis filter.

Table 10 De-emphasis settings

DE1 DE0 FUNCTION

0 0 no de-emphasis
0 1 de-emphasis, 32 kHz
1 0 de-emphasis, 44.1 kHz
1 1 de-emphasis, 48 kHz

Mute: a 1-bit value to enable the digital mute.

Table 11 Mute setting

MT FUNCTION

0 no muting
1 muting

1999 Oct 11 10

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

10 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

V

DDA

T

xtal(max)

T

stg

T

amb

V

es

Notes

1. All supply connections must be made to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor, except pin 14 which must be specified to

-2500V (MIN) and +2500V (MAX).

3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.

digital supply voltage note 1 − 5.0 V
analog supply voltage note 1 − 5.0 V
maximum crystal temperature − 150 °C
storage temperature −65 +125 °C
operating ambient temperature −30 +85 °C
electrostatic handling note 2 −3000 +3000 V

note 3 −300 +300 V

11 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.

12 QUALITY SPECIFICATION

In accordance with

Handbook”

. The handbook can be ordered using the code 9397 750 00192.

“SNW-FQ-611-E”

. The number of the quality specification can be found in the

“Quality Reference

13 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 190 K/W

1999 Oct 11 11

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

14 DC CHARACTERISTICS

V

DDD=VDDA

= 3.3 V; T

=25°C; RL=5kΩ. All voltages referenced to ground (pins 5 and 15) unless otherwise

amb

specified.

SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT

Supply

V
V
I

DDA

I

DDD

DDA
DDD

DAC analog supply voltage note 1 2.7 3.3 3.6 V
digital supply voltage note 1 2.7 3.3 3.6 V
analog supply current operation mode − 6.5 − mA
digital supply current operation mode − 3.0 − mA

Digital input pins

V

IH

V

IL

I

 input leakage current −−1µA

LI

C

i

V

IH

V

IL

HIGH-level input voltage 0.8V

DDD

LOW-level input voltage −−0.2V

input capacitance −−10 pF
HIGH-level input voltage −−V
LOW-level input voltage −0.5 −−V

−−V
V

DDD

+ 0.5 V

DDD

DAC

V

ref

I

o(max)

reference voltage with respect to V

SSA

maximum output current (THD + N)/S < 0.1%

0.45V

DDA

0.5V

DDA

0.55V

− 0.22 − mA

DDA

V

RL=5kΩ

R

out

R

L

C

L

output resistance - 0.15 2.0 Ω
load resistance 3 −−kΩ
load capacitance note 2 −−50 pF

Notes

1. All supply connections must be made to the same external power supply unit.

2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.

1999 Oct 11 12

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

15 AC CHARACTERISTICS

15.1 Analog

V

DDD=VDDA

= 3.3 V; fi= 1 kHz; T

=25°C; RL=5kΩ. All voltages referenced to ground (pins 5 and 15) unless

amb

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DAC

V

o(rms)

∆V

o

(THD + N)/S total harmonic distortion plus

output voltage (RMS value) − 1.0 − V
unbalance between channels − 0.1 − dB

at 0 dB −−90 −85 dB

noise-to-signal ratio

at −60 dB; A-weighted −−38 -35 dB

S/N signal-to-noise ratio code = 0; A-weighted − 100 95 dB

α

cs

PSRR power supply ripple rejection

channel separation − 100 − dB

f

ratio

ripple

V

ripple(p-p)

= 1 kHz;

= 100 mV

− 50 − dB

1999 Oct 11 13

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

15.2 Digital

V

DDD=VDDA

= 2.7 to 3.6 V; T

= −20 to +85 °C; RL=5kΩ. All voltages referenced to ground (pins 5 and 15); unless

amb

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

T

sys

t

CWL

t

CWH

system clock cycle f

LOW-level system clock pulse width f

HIGH-level system clock pulse width f

= 256f
f
f

f

f

sys
sys
sys
sys
sys
sys
sys

s

= 384f

s

= 512f

s

< 19.2 MHz 30 − 70 %T

≥ 19.2 MHz 40 − 60 %T

< 19.2 MHz 30 − 70 %T

≥ 19.2 MHz 40 − 60 %T

78 88 244 ns
52 59 162 ns
39 44 122 ns

Serial input data timing (see Fig.7)
T

cy(CLK)(bit)

t

CLKH(bit)

t

CLKL(bit)

t

r

t

f

t

su(i)(D)

t

h(i)(D)

t

su(WS)

t

h(WS)

bit clock period 300 −−ns
bit clock HIGH time 100 −−ns
bit clock LOW time 100 −−ns
rise time −−20 ns
fall time −−20 ns
data input set-up time 20 −−ns
data input hold time 0 −−ns
word selection set-up time 20 −−ns

word selection hold time 10 −−ns
Microcontroller interface timing (see Figs 4 and 6)
T

cy(CLK)(L3)

t

CLK(L3)H

t

CLK(L3)L

t

su(L3)A

t

h(L3)A

t

su(L3)D

t

h(L3)D

t

su(L3)DA

L3CLK 500 −−ns

L3CLK HIGH period 250 −−ns

L3CLK LOW period 250 −−ns

L3MODE set-up time addressing mode 190 −−ns

L3MODE hold time addressing mode 190 −−ns

L3MODE set-up time data transfer mode 190 −−ns

L3MODE hold time data transfer mode 190 −−ns

L3DATA set-up time data transfer and

190 −−ns

addressing mode

t

h(L3)DA

L3DATA hold time data transfer and

30 −−ns

addressing mode

t

stp(L3)

L3MODE halt time 190 −−ns

sys
sys
sys
sys

1999 Oct 11 14

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

handbook, full pagewidth

WS

t

CLKH(bit)

BCLK

DATAI

t

r

t

CLKH(bit)
T

t

cy(CLK)(bit)

16 APPLICATION INFORMATION

handbook, full pagewidth

R1

system

clock

SYSCLK

47 Ω

BCK

WS

DATAI

APPSEL

APPL0
APPL1
APPL2
APPL3

f

6

1
2
3
7

11
10

9
8

t

h(WS)

Fig.7 Serial interface timing.

analog

supply voltage

R2
1 Ω

C1

100 µF

(16 V)

C5

100 nF

(63 V)

V

SSA

15 13

V

DDA

UDA1320A

100 nF

V

t

su(WS)

digital

supply voltage

R3
1 Ω

C6

(63 V)

V

SSD

DDD

45

14

16

12

V

O(L)

V

O(R)

V

REF(DAC)

t

su(i)(D)

C2

47 µF
(16 V)

C3

47 µF

(16 V)

C7
100 nF
(63 V)

R5
10 kΩ

R7
10 kΩ

R4

100 Ω

R6

100 Ω

C4
47 µF
(16 V)

t

h(i)(D)

MGM818

MBK075

left
output

right
output

Fig.8 Application schematic.

1999 Oct 11 15

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

17 PACKAGE OUTLINE

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

D

c

y

Z

16

pin 1 index

9

18

w M

b

e

p

E

H

E

A

2

A

1

L

detail X

A

X

v M

A

Q

(A )

L

p

A

3

θ

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

OUTLINE

VERSION

SOT369-1

A

max.

1.5

0.15

0.00

p

1.4

1.2

IEC JEDEC EIAJ

0.25

0.32

0.20

0.25

0.13

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

(1)E(1)

cD

5.30

5.10

REFERENCES

4.5

4.3

0.65

1999 Oct 11 16

eHELLpQZywv θ

1.0

0.75

0.45

0.65

0.45

PROJECTION

0.130.2 0.1

EUROPEAN

6.6

6.2

(1)

0.48

0.18

ISSUE DATE

94-04-20
95-02-04

o

10

o

0

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

18 SOLDERING

18.1 Introduction to soldering surface mount
packages

Thistextgives a very briefinsighttoa complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering isnot always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

18.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board byscreen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswith leads on four sides,thefootprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement andbefore soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

18.3 Wave soldering

Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) or printed-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

1999 Oct 11 17

18.4 Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

18.5 Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

SOLDERING METHOD

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e)equal toor larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

19 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

20 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Oct 11 18

Philips Semiconductors Preliminary specification

Low-cost stereo filter DAC UDA1320ATS

NOTES

1999 Oct 11 19

Philips Semiconductors – a w orldwide compan y

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Tel. [phone], Fax. [phone]
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220050 MINSK, Tel. [phone], Fax. [phone]

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Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
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Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
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Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
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Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
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Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

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Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 545002/25/01/pp20 Date of release: 1999 Oct 11 Document order number: 9397 750 03335