The TEA5170 is designed to work in the secondary
part of an off-line SMPS, sending pulses to the
slaved TEA2260/61 which are located on the primary side of the main transformer. An accurate
regulated voltage is obtained by duty cycle control.
The TEA5170 can be externally synchronized by
higher or lower frequency signal, then it could be
used in applications like TV set ones. For more
details, refer to application note AN408/0591.
The TEA5170 takes place in the secondary part of
an isolated off-line SMPS. During normal mode
operation, it sends pulses to the slave circuit located in the primary si de (TEA 2164, T EA2260/61)
through a pulse transformer to achieve a very
precisely regulated voltage by duty cycle control.
The main blocs of the circuit are :
- an error voltage amplifier
- an RC oscillator
- an output stage
-a V
monitor
CC
- a voltage reference bloc
- a pulse width modulator
- two logic blocs
- a soft start and Duty cycle limiting bloc
PRINCIPL E OF OPER ATION
The TEA5170 sends pulses continuously to the
slave circuit in order to insure a proper behaviour
of the primary side.
- According to this, the output duty cycle is vary ing
between D
ON (min.)
(0.05) and D
ON (max.)
(0.75) :
then even in case of open load, pulses are still
sent to the slave circuit.
Figure 1 : Basic Concept
ASYNCHRONIZED MODE (Figure 2)
The regulated voltage image is compared to 2V
vol-tage reference. The error voltage amplifier output and the RC oscillator voltage ramp are applied
to the internal Pulse Width Modulator Inputs.
The PWM logic Output is connected to a logic bloc
which behaves like a RS latch, sets by the PWM
output and resets when Ct downloading occurs.
Finally, the push-pull output bloc delivers square
wave signal whom output leading edge occurs
during Ct uploading time, and output trailing edge
at Ct downloading time end. The duty cycle is
limited to 75% of oscillator period as maximum
value and to Ct downloading time/oscillator period
as minimum value (Figure 2).
Figure 2
V2
V
t
OSCILLATOR RAMP
POWER OUTPUT
max.
V1
4/9
SLAVE
CIRCUIT
MASTER-SLAVE ARCHITECTURE
MASTER
CIRCUIT
PWM
T1
T
on max.
T2 =T
SYNCHRONIZED MODE (see Figure 3)
The TEA5170 will enter the Synchronized Mode
when it receives one pulse through Rt during Ct
discharge.
At that time Ct charging current will be multiplied
by 0.75 and period will increase up to To x 1.26.
A pulse occur ing during the s ync hro window , commands the Ct downloading. If none, the TEA5170
will return to normal mode at the end of the period.
5170-03.EPS
on min.
5170-04.EPS
Page 5
Figure 3
TEA5170
UNSYNCHRONIZED
MODE
Vct
Vtsy
Vrt
Wtrig-Wtrig+
SYNCHRONIZED MODE
Remark : In case of an application between
TEA5170 and TEA2164, t o optimize th e
synchronization windows of these
circuits, the following relations have to
be used : T
T
SYNC
=
m
1.06
Te =
T
m
1.223
with Te : Free period of the TEA2164
oscillator, and T
: Free period of the
m
TEA5170 oscillator .
UNSYNCHRONIZED
MODE
Figure 4 : Triggering Schematic
7
Ct
1kΩ
5170-05.EPS
V
CC
from logic
BLOCK DESCRIPTION
The error voltage am plifier invert ing-input and output are accessible to use different feed-back network and allowing parasitic filtering network. The
non-inverting input is internaly connected to 2V
reference voltage.
The RC oscillator is designed to work at high
frequency (up to 250kHz). R
charging current Io = 2/R
The capacitor C
during T1 =
an integrated resistor R
is loaded from V1 ≈ 1V to V2 = 2V
T
C
T RT
and then down loaded through
1.985
2
sets the capacitor
T
.
T
≈ 1kΩ during T2 = 1300 C
The ramp is used to limit the duty cycle. Then the
maximum duty cycle is
DONMAX =
The output level is V
1
T1 +
(0.73 T1 + T2)
T2
independant when VCC is
CC
over 8V.
The V
V
CC
monitoring switches the circuit on when
CC
is over 4V and s witches it of f when under 3.8V.
This function insures a proper starting procedure
(made by the primary side circuit).
SYNCHRONIZATION
(see Figures 4 and 5)
Network
Figure 5 : Typical W avef orms
T
Vct
Vrt
2.7V
2V
2.7V
8
2.7V
+
towards logic
5170-06.EPS
Rt
1V
T
trigP
5170-07.EPS
5/9
Page 6
TEA5170
STARTING
When VCC is under 4V, output pulses are not
allowed and the slave circuit keeps its own mode.
When V
is going over 4V, output pulses are sent
CC
via the pulse transformer (or an optical device) to
the slave circuit which is synchronizing and entering the slaved mode. Output pulses can be shut
down only if V
goes below 3.8 Volt.
CC
Figure 6 : Soft-Start Sequence
V(V)
CC
12
4
V(V)
CSF
3.2
2
SOFT START
Using Csf, it is possible to make a soft start sequence. When V
on Csf equals 0V. When V
grows from 0V to 4V, voltage
CC
is higher than 4V, Csf
CC
is loaded by a 3.7µA current, then TonMAX (Vcsf)
will vary linearly f rom Tonmin to Tonmax according
to Csfst bias.
When V
will go low (3.8 Volt threshold), Csf will
CC
be downloaded by an internal transistor.
t
t
Duty cycle
D
on max.
D
on min.
POWER OU TPUT STAGE
Figure 7 : Electrical Schematic
1mA
from logic
V
1mA
CC
maximum
minimum
Pout
3
t
5170-08.EPS
6/9
5170-09.EPS
Page 7
Figure 8
135V
TEA5170
Sync.
Input
P1
47kΩ
100µF
(250V)
BY218-600
G4466-01
313
120kΩ
15V
470µF
BA157
20
2.2kΩ
10V
10kΩ
(25V)
1000µF
(25V)
BY218-100
19
14
6
9
Stand-by
Control
Ω
75k
3.3
nF
BC547C
20V
470µF
(40V)
BY318-100
22
21
717
TEA5170
16V
3781
220Ω
(8W)
BA159
2465
10µF
BUV56A
47nF
1.2nF2%
4.7nF
1kV
150pF
1N4148
Ω
270
Ω
100k
6.8kΩ
1%
Pulse
Transformer
Ω
100
4 x BY254
BA157
(3W)
Ω
220µF
4.7
(2W)
44kΩ
220µF
(250V)
68kΩ
20%110
AC
V
P2
1nF
25V
18ΩBZX85C-3V0
2.2µF47µF
6.8Ω
(3W)
141
15
22kΩ
45121316
9
10
100nF
2
11
F
µ
4.7
3
TEA2164
1.2nF2%
8
76
100Ω
0.18Ω (1W)
1N4148
330
Ω
1kΩ
16V
1nF
: 90W
OUT
f : 16kHz
1%
110kΩ
P
5170-10.EPS
7/9
Page 8
TEA5170
Figure 9
135V
0.8A
Sync.
Input
Ω
12V
Ω
2.2k
120k
7.5V
1A
Stand-by
Control
Ω
Ω
10k
75k
5
6
4
1.2
nF
0.5A
F
µ
470
(25V)
BC547C
25V
F
µ
1000
(25V)
F
µ
1000
(40V)
2
F
µ
10
16V
1
8
7
TEA5170
560
3
150pF
6.8kΩ100kΩ
47nF
1N4148
pF
Ω
P1
47k
(250V)
100µF
270Ω1kΩ
BY218-600
G4576-02
4 x 1N4007
AC
V
170
PLR811
BY218-100
13
20
19
14717922
BY218-100
21
220Ω(16W)
3
6
2.7nF
BY299
1kV
SGSF344
100
pF
BA157
1N4148
Ω
39
(3W)
18kΩ
150µF
(385V)
Ω
4.7k
AC
V
270
P2
F
µ
330
2.2Ω (0.5W)
25V
6.8Ω
(1W)
22kΩ
1
BZX85C -3V0
18Ω
2.2µF47µF
1615
314
(16V)
2.2µF
1nF
12 13
5
8
9
TEA2164
4
1kΩ
1kΩ
Ω
22k
6
7
3.3nF
220nF
220nF
2
1nF
1110
Ω
56kΩ
100Ω
(1W)
Ω
0.135
330Ω
150k
: 140W
OUT
f : 32kHz
P
BC547C
8/9
1MΩ
5170-11.EPS
Page 9
PACKAGE MECHANICAL DATA
8 PINS - PLASTIC DIP
b
Z
D
e3
TEA5170
e4
I
A
L
a1
B
B1
e
E
Z
b1
8
5
F
14
Dimensions
Min.Typ.Max.Min.Typ.Max.
MillimetersInches
A3.320.131
a10.510.020
B1.151.650.0450.065
b0.3560.550.0140.022
b10.2040.3040.0080.012
D10.920.430
E7.959.750.3130.384
e2.540.100
e37.620.300
e47.620.300
F6.60260
i5.080.2 00
L3.183.810.1250.150
Z1.520.060
Information furnished i s believed to be accurate and rel iabl e. However, S GS-THOMSON Microel ectroni cs assumes no responsibil ity
for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.