• Smoothed transitions before and after digital mute (soft
mute)
• Fade function: duration-programmable (6 ms to 22.4 s
at 44.1 kHz) digital volume control (attenuation as well
as gain): +6 dB to −90 dB in steps of 0.375 dB with
automatic soft mute
• Digital balance: 0 dB to −22.5 dB in steps of −1.5 dB
(maximum overall attenuation combined with volume
control: −90 dB)
OLUME CONTROL FEATURES
) 256fs or 384f
sys
s
TDA1546T
1.3.2S
• Digital de-emphasis filter for three sample rates (32 kHz,
44.1 kHz or 48 kHz)
• Digital treble: −10.5 dB to +12 dB at 20 kHz; 16 steps
spaced at 1.5 dB
• Digital bass: −9 dB to +13.5 dB at 20 Hz; 16 steps
spaced at 1.5 dB
• Distortion-free digital dynamic bass boost: 0 dB to
+37 dB at 10 Hz; 15 steps spaced at 2 dB
• Can be used for loudness or dynamic digital bass boost
• Double-speed mode (e.g. for high-speed dubbing)
• Pseudo double-speed mode (for power saving
application)
• Digital speaker system mode including digital crossover
filter.
1.3.3S
• Spectrum analyzer for seven different frequency ranges
• Digital silence detection. Level (−48 dB to∞dB, in steps
of 3 dB) and duration (200 ms to 3.2 s, in steps of
200 ms at 44.1 kHz) programmable. Output via versatile
pins.
• Peak level detection and readout to microcontroller
(dB linear, 0 dB to −90 dB in steps of 1.5 dB)
• Digital overload detection. Level-programmable (dB
linear, −1.5 dB to−46.5 dB, in steps of 3 dB). Output via
versatile pins.
• Digital spectrum analyzer by combination of peak
detection and 7-band selective filter
• Optional combination spectrum analyzer and overload
detection for frequency-dependent overload detection.
OUND PROCESSING FEATURES
OUND MONITOR FEA TURES
2ORDERING INFORMATION
TYPE
NUMBER
TDA1546TSO28plastic small outline package; 28 leads; body width 7.5 mmSOT136-1
January 19954
NAMEDESCRIPTIONVERSION
PACKAGE
Page 5
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
TDA1546T
digital sound processing (BCC-DAC)
3QUICK REFERENCE DATA
SYMBOLSPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
V
DD
I
DDD
I
DDA
I
DDO
I
DDX
V
FS(rms)
(THD+N)/Stotal harmonic distortion
S/Nsignal-to-noise ratio at
t
dg
BRinput bit rate at data inputfs= 48 kHz;
f
sys
TC
FS
T
amb
supply voltagenote 13.85.05.5V
digital supply currentnote 2−40−mA
analog supply currentnote 2−5.5−mA
operational amplifier
note 2−6.5−mA
supply current
clock circuitry supply
note 2−1−mA
current
full-scale output voltage
VDD= 5 V1.4251.51.575V
(RMS value)
at 0 dB signal level−−88−81dB
plus noise-to-signal ratio
at −60 dB signal level;
−0.0040.009%
−−44−40dB
A-weighted
A-weighted; at code
bipolar zero
00000H
group delayfs= sample rate;
normal-speed
100108−dB
−−s
24
-----f
s
−−3.072Ms
normal-speed
fs= 48 kHz;
−−6.144Ms
double-speed
system clock frequency6.4−18.432MHz
full-scale temperature
−±100× 10−6−
coefficient at analog
outputs (VOL and VOR)
operating ambient
−20−+70°C
temperature
−1
−1
Notes
1. All V
and VSS pins must be connected to the same supply or ground respectively.
DD
2. Measured at input code 00000H and VDD=5V.
January 19955
Page 6
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
4GENERAL DESCRIPTION
The TDA1546T is the first Bitstream Continuous
Calibration digital-to-analog converter (BCC-DAC) to
feature unique signal processing functions. In addition to
the basic functions of digital filtering and digital-to-analog
conversion, it offers such advanced digital signal
processing functions as volume control, tone control, bass
boost, peak or spectrum analyzer readout and many more
convenient functions. The digital processing features are
of high sound quality due to the wide dynamic range of the
bitstream conversion technique.
2
The TDA1546T accepts I
word lengths of up to 20 bits and various Japanese serial
data input formats with word lengths of 16, 18 and 20 bits.
The circuit can operate as a master or slave with different
system clocks (256fs or 384fs) and is therefore, eminently
suitable for use in various applications such as DCC, CD,
DAT and MD.
S-bus data input formats with
TDA1546T
The range of applications is further extended by an
incorporated Digital Speaker System mode (DSS) with
digital crossover filter.
Four cascaded FIR filters and a sample-and-hold function
increase the oversampling rate from 1f
(384fssystem clock) or 128fs (256fs system clock).
A second-order noise shaper converts this oversampled
data to a bitstream for the 5-bit DACs.
The DACs are of the continuous calibration type and
incorporate a special data coding technique, which
contributes to a high signal-to-noise ratio and dynamic
range.
On-board amplifiers convert the output current to a voltage
signal capable of driving a line output. Externally
connected capacitors perform the required first-order
filtering. Additional post filtering is not required.
to 96f
s
s
Fig.1 Digital audio reconstruction system using the TDA1546T.
January 19956
Page 7
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
5BLOCK DIAGRAM
handbook, full pagewidth
VERS1
VERS0
SPECTRUM ANALYSER
dB CONVERTER
SILENCE
DETECTION
21
VERSATILE
20
OUTPUT
BCK5WS6DATA
4
PEAK
DETECTION
OVERLOAD
DETECTION
SOURCE
SELECTION
MULTIPLE FORMAT
INPUT INTERFACE
DE-EMPHASIS
VOLUME CONTROL
BALANCE
SOFT MUTE
TONE CONTROL 1
BASS
TONE CONTROL 2
TREBLE
TONE CONTROL 3
BASS BOOST
CKSL
7
CRYSTAL
OSCILLATOR
CLOCK
GENERATION
AND
DISTRIBUTION
TDA1546T
12
XTAL1
13
XTAL2
16
CDEC
14
V
DDX
15
V
SSX
10
V
DDD
9
V
SSD
TEST1
TEST2
1 nF
C
EXT1
1 µF
V
V
GND
OL
FIR FILTER
3
11
23FILTCL
2.2 kΩ
22
26
ref
TDA1546T
LINEAR INTERPOLATOR 8f to 16f
6 x OVERSAMPLING (SAMPLE-AND-HOLD)
SECOND ORDER NOISE SHAPER
DATA ENCODER
LEFT OUTPUT SWITCHES
16 (4-bit)
R
CONV1
V
27
SSO
CALIBRATED
CURRENT
SOURCES
16 (4-bit)
CALIBRATED
CURRENT
28
V
DDO
SINKS
STAGE 1:1f to 2f
STAGE 2:2f to 4f
STAGE 3:4f to 8f
ss
REFERENCE
SOURCE
ss
FIR FILTER
ss
FIR FILTER
s
s
LINEAR INTERPOLATOR 8f to 16f
6 x OVERSAMPLING (SAMPLE-AND-HOLD)
SECOND ORDER NOISE SHAPER
RIGHT OUTPUT SWITCHES
16 (4-bit)
CALIBRATED
CURRENT
SOURCES
16 (4-bit)
CALIBRATED
CURRENT
SINKS
MICROCONTROLLER
INTERFACE
DATA ENCODER
1
V
DDA
ss
R
V
SSA
CONV2
2.2 kΩ
OP1OP1
2
8
19
18
17
24 FILTCR
25
MLC782
POR
L3DATA
L3CLK
L3MODE
V
OR
C
1 nF
EXT2
Fig.2 Block diagram.
January 19957
Page 8
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
7FUNCTIONAL DESCRIPTION
The TDA1546T CMOS digital-to-analog bitstream
converter incorporates an up-sampling digital filter and
noise shaper which increase the oversample rate of 1f
input data to 128fs in the normal-speed mode. This
high-rate oversampling, together with the 5-bit DAC,
enables the filtering required for waveform smoothing and
out-of-band noise reduction to be achieved by simple
first-order analog post-filtering.
In the double-speed mode, the input sample frequency is
twice that of the normal-speed mode, as is the signal
bandwidth. The TDA1546T is able to distinguish between
the two modes (by means of a special programming bit),
so that in the double-speed mode, only half the amount of
oversampling is applied, and digital filtering is applied over
double the bandwidth compared to normal-speed. Thus in
the double-speed mode, the input sample rate of 1fs input
data is up-sampled by a factor 64f
, achieving the same
s
absolute output sample frequency as in normal-speed
mode.
In the block diagram, Fig.2, a general subdivision into main
functional Sections is illustrated. The actual signal
processing takes place in the digital signal processing
block. The two blocks named microcontroller interface and
clock generation and distribution fulfil a general auxiliary
function to the audio data processing path. The
microcontroller interface provides access to all the blocks
that require, or allow, configuration or selection and
processes the data readout from the peak detection block,
all via a simple three-line interface. The clock generation
and distribution section, which is driven by the external
system clock or crystal oscillator, provides the data
processing blocks with time bases and controls the system
mode dependent frequency settings. The following
sections give detailed explanations of the operation of
each block and their setting options processed by the
microcontroller interface, the use of the microcontroller
interface and of the operation of the clock section with its
various system settings.
s
TDA1546T
7.1Clock generation and distribution
The TDA1546T has an internal clock generator that may
be used by connecting a crystal of 11.2896 MHz (256f
16.9344 MHz (384fs) between pins XTAL1 and XTAL2.
This mode is used when the TDA1546T is the master in
the system. The circuit diagram of Fig.4 shows the typical
connection of the external oscillator circuitry for master
mode operation.
Alternatively, the TDA1546T can also operate in slave
mode. Figure 5 shows how to connect for slave mode
operation. In this mode, pin XTAL1 receives an input clock
of 256 or 384f
(fs= 32, 44.1 or 48 kHz) and voltage levels
s
of 0 V to 5 V by AC coupling and attenuation.
The CDEC output (pin 16) contains a buffered version of
the system clock for external use. The clock selection pin
CKSL is used to select between system clock frequency
ratios. Its effect is shown in Table 1.
Table 1 System clock selection
PIN CKSLSYSTEM CLOCKCDEC OUTPUT
0256f
1384f
s
s
256f
384f
Fig.4 External crystal oscillator circuit.
) or
s
s
s
January 19959
Page 10
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
Fig.5 External clock input connection.
7.2Power-on reset
The internal register file of the TDA1546T is initialized by a
power-on reset sequence which can be instigated via the
POR input pin 8. A LOW input on POR causes the reset
sequence to be active. This input has an internal
resistance to VDD to allow for passive use with only an
external capacitor connected between this pin and ground.
For correct detection by the TDA1546T internal controller,
the system clock must be running, andPOR should remain
LOW for at least one audio sample period before being
returned HIGH. Following detection another audio sample
period is needed to complete the initialization procedure,
after which the values of the various control bits in the
internal register file are at their predefined initial values
(see Section 7.3).
TDA1546T
7.3Microprocessor interface
The exchange of data and control information between the
TDA1546T and a microcontroller is accomplished through
a serial hardware interface comprising the following pins:
L3DATA: microcontroller interface bidirectional data
line.
Information transfer through the microcontroller bus is
organized according to the so-called ‘L3’ format, in which
two different modes of operation can be distinguished;
address mode and data transfer mode.
The address mode is required to select a device
communicating via the L3-bus and to determine the
direction of data transfer in data transfer mode. Data
transfer for the TDA1546T can be in two directions, input
to the TDA1546T to program its sound processing and
other functional features, and output from the TDA1546T
for transfer of audio peak data, which it has acquired and
processed, to the system microcontroller.
7.3.1A
The address mode is used to select a device for
subsequent data transfer and to define the direction of that
transfer as well as the source or destination registers. The
address mode is characterized by L3MODE being LOW
and a burst of 8 clock pulses on L3CLK, accompanied by
8 data bits. The fundamental timing is shown in Fig.6.
DDRESS MODE
Fig.6 Timing address mode.
January 199510
Page 11
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
Data bits 0 to 1 indicate the type of the subsequent data
transfer as shown below in Table 2. The direction of the
channel status and user data transfers depends on the
transmit/receive mode.
Table 2 Selection of data exchange
(1)
BIT 1
X0data to TDA1546Tinput
X1data from
Note
1. Where X = don't care.
Data bits 2 to 7 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
BIT 0TRANSFERDIRECTION
output
TDA1546T
TDA1546T
TDA1546T is 000100 (bit 7 to bit 2). In the event that the
TDA1546T receives a different address, it immediately
3-states the L3DATA pin and deselects its microcontroller
interface logic. A dummy address of 000000 is defined for
the deselection of all devices that are connected to the
serial microcontroller bus.
7.3.2D
The selection performed in the address mode remains
active during subsequent data transfers, until the
TDA1546T receives a new address command. The
fundamental timing of data transfers is shown in Fig.7,
where L3DATA denotes the data from the TDA1546T to
the microcontroller (L3DATA write). The timing for the
opposite direction is essentially the same as in the address
mode (L3DATA read). The maximum input clock and data
rate is 64f
ATA TRANSFER MODE
(or 32fs when in the double-speed mode).
s
Fig.7 Timing for data transfer mode.
All transfers are bytewise, i.e. they are based on groups of
8 bits. Data will be stored in the TDA1546T after the eighth
bit of a byte has been received.
A multi-byte transfer is illustrated in Fig.8. The definition of
the L3 protocol allows for a so-called “halt” mode, as some
devices which are expected to connect to the same
microcontroller bus lines may require an indication of when
January 199511
8 bits have been transferred. This halt mode option is
implemented in the TDA1546T, meaning that subsequent
byte transfers must be separated by a period identified as
halt mode. A halt mode period is characterized by the
following conditions:
L3MODE = LOW, L3DATA = 3-state and L3CLK = HIGH.
Page 12
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
Fig.8 Multibyte transfer.
7.3.3ORGANIZATION AND PROGRAMMING OF THE
INTERNAL REGISTER FILE
Command data received from the microcontroller is stored
in an internal register file (see Table 3) which is organized
as a page of 16 registers, each containing a 4-bit
command data word (D3 to D0).
TDA1546T
Access to the words in the register file involves selection
of the address of a register location (by means of A3, A2,
A1 and A0). A second page of 4 registers is accessible by
means of the extended address register bits (EA2, EA1
and EA0) and extended data register bits (ED3, ED2, ED1
and ED0).
Table 3 Microcontroller control register file
ADDRESS
D3D2D1D0
A3A2A1A0
00 00BAL3BAL2BAL1BAL01 1 1 1balance left
01BAR3BAR2BAR1BAR01 1 1 1balance right
10VC3VC2VC1VC01 1 1 1volume control
11VC7VC6VC5VC41 1 1 0volume control
The following programming values for the various control
words in the register file are given below.
7.3.3.1Volume control register bits: BAL3 to BAL0
and BAR3 to BAR0
Balance: a 4-bit value to program left channel attenuation
(BAL3 to BAL0) and a 4-bit value to program right channel
attenuation (BAR3 to BAR0). The range is
0dBto−22.5 dB in steps of 1.5 dB (see Section 7.7.1).
7.3.3.2Volume control register bits: VC7 to VC0 and
FT3 to FT0
Volume control set number: an 8-bit value to program
volume control coefficient set (6 dB to −90 dB, in steps of
0.375 dB, VC7 to VC0); a 4-bit value to program fade time
(6 ms to 22.4 s, FT3 to FT0) (see Section 7.7.2).
7.3.3.3Volume control register bit: MUTE
ED3ED2ED1ED0
INITIAL
STATE
clear memory
7.3.3.7Sound monitor register bits: SIL3 to SIL0 and
SILT3 to SILT0
Digital silence set numbers: a 4-bit value to program digital
silence detection level −48 dB to ∞ dB (SIL3 to SIL0) and
a 4-bit value to program digital silence duration
0.2 s to 3.2 s (SILT3 to SILT0) (see Section 7.9.4).
7.3.3.8Sound monitor register bit SPOS
This bit controls the position of the spectrum analyzer.
When SPOS = 1 the position of spectrum analyzer
precedes the tone control sections. When SPOS = 0 the
position of the spectrum analyzer succeeds the tone
control sections.
7.3.3.9Sound processing register bit: DSS
Digital speaker system programming bit
(see Section 7.8.6).
USED FOR
Digital soft mute control bit: logic 1 to activate mute and
logic 0 to deactivate (see Section 7.7.3).
7.3.3.4Volume control register bit: RUNFA
Function control bit: logic 1 to activate the volume control
(after new fade time and/or volume control setting) (see
Section 7.7.2.).
7.3.3.5Sound monitor register bits: FP2 to FP0
Frequency range control bits (see Section 7.9.1).
7.3.3.6Sound monitor register bits: OVER3 to OVER0
Overload detection level (dB linear; 0 dB to −45 dB, in
steps of −3 dB) (see Section 7.9.5).
January 199513
7.3.3.10Sound processing register bits: SCT3 to SCT0
Treble coefficient set number: a 4-bit value to program
digital treble coefficient set (see Section 7.8.2).
7.3.3.11Sound processing register bits: SCB3 to SCB0
Bass coefficient set number: a 4-bit value to program
digital bass coefficient set (see Section 7.8.3).
7.3.3.12Sound processing register bits: SCBB3 to
SCBB0
Bass boost coefficient set number: a 4-bit value to program
digital bass boost coefficient set (see Section 7.8.4). This
is also used for digital speaker system configuration
(see Section 7.8.6).
Page 14
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
7.3.3.13Sound processing register bits: DEMC1 and
DEMC0
De-emphasis function enable and fs selection bits
(see Section 7.8.1).
7.3.3.14Sound processing register bit: DSM
Double-speed mode control bit: logic 1 to activate
double-speed mode, logic 0 to deactivate
(see Section 7.6).
7.3.3.15Miscellaneous register bits: ED3 to ED0
Extended microcontroller control data (see Table 4).
7.3.3.16Miscellaneous register bits: EA2 to EA0
Extended microcontroller register address (see Table 4).
7.3.3.17Miscellaneous register bits: INS1 and INS0
Input format selection control bits (see Section 7.4).
TDA1546T
7.4Multiple format input interface
Data input to the TDA1546T is accepted in four possible
formats, I
LSB fixed formats of word lengths 16, 18 and 20 bits. As
the resolution of the TDA1546T is 18 bits, input beyond
this number does not affect the audio data processing. The
general appearance of the permitted formats is given in
Fig.9. The selection of a format is achieved through
programming of the appropriate bits in the microcontroller
register file. The truth table for these bits, INS1 and INS0,
is given in Table 5. Characteristic timing for the input
interface is given in the diagram of Fig.9.
Table 5 Input format programming
2
S-bus (with word lengths of up to 20 bits), and
INS1INS0DATA INPUT FORMAT
00I
01LSB-justified format, 16 bits
10LSB-justified format, 18 bits
11LSB-justified format, 20 bits
2
S-bus format
7.3.3.18Miscellaneous register bits: PVIV1, PVIV0 and
PINM1, PINM0
These bits control the polarity (PVIV1 and PVIV0) and the
output mode (PINM1 and PINM0) of the versatile output
pins VERS1 and VERS0 (see Section 7.9.6).
7.3.3.19Miscellaneous register bit: CLRM
Clear memory register bit: logic 1 to clear entire filter delay
line (approximately 2 audio samples).
7.3.3.20Miscellaneous register bits: OUTS1 and
OUTS0
Output scaling factor control bits (see Table 10).
7.3.3.21Miscellaneous register bit: LONLY
“Left Only” programming bit for use with digital speaker
system mode (see Section 7.8.6).
7.4.1S
For correct data input to reach the central controller of the
TDA1546T, synchronization must be achieved on the
incoming 1fs I2S-bus or LSB justified format input signals.
The incoming WS signal is sampled to detect whether its
phase transitions belonging to left channel input occur at
the correct synchronous timing instants. This sampling
occurs at the TDA1546T internal clock rate. A correct
phase transition of WS is expected after a fixed delay time
of a previous correct transition, if not, the input will be
regarded as out-of-lock. When such a condition occurs,
the internal controller is instructed to wait for a period of
16 system clock cycles during which the expected WS
transition must occur to achieve synchronization. The wait
action is repeated as often as necessary until
synchronization is achieved.
To allow for slight disturbances, which would otherwise
cause unnecessarily frequent resets, the critical WS
transitions are expected within a tolerance window (rather
than at one particular timing instant) of 32 system clock
cycles. The phase, however, may vary according to the
instant upon which synchronization has been achieved.
The word select phase transition marking the start of right
channel input data is expected after a fixed delay of the left
channel synchronized WS transition, meaning that the
input WS signal should be symmetrical in time (50% duty
cycle measured in units of system clock cycles).
YNCHRONIZATION
January 199514
Page 15
January 199515
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
Fig.9 Input formats.
TDA1546T
Page 16
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
TDA1546T
Fig.10 Timing of input signals.
7.5Normal-speed mode
In the normal-speed mode the oversampling filter consists
of:
• A 75th-order half-band low-pass FIR filter which
increases the oversampling rate from 1 time to 2 times.
• An 11th-order half-band low-pass FIR filter which
increases the oversampling rate from 2 times to 4 times.
• An 7th-order half-band low-pass FIR filter which
increases the oversampling rate from 4 times to 8 times.
• A linear interpolation section which increases the
oversampling rate to 16 times. This removes the
spectral components around 8f
• A sample-and-hold section which provides another
6 times oversampling to 96 times. The zero-order hold
characteristic of this sample-and-hold section plus the
first-order analog filtering remove the spectral
components around 16fs.
.
s
7.6Double-speed mode
The double-speed is controlled by the register control bit
DSM. When this bit is active HIGH the device operates in
the double-speed mode. In the double-speed mode the
oversampling filter consists of:
• A 51st-order half-band low-pass FIR filter which
increases the oversampling rate from 1 time to 2 times.
• A 7th-order half-band low-pass FIR filter which
increases the oversampling rate from 2 times to 4 times.
• A linear interpolation section which increases the
oversampling rate to 8 times. This removes the spectral
components around 4fs.
• A sample-and-hold section which provides another
6 times oversampling to 48 times. The zero-order hold
characteristic of this sample-and-hold section plus the
first-order analog filtering removes the spectral
components around 8fs.
January 199516
Page 17
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
7.6.1DOUBLE-SPEED MODE FEATURES
In the normal-speed mode all of the sound processing
features such as those listed in the “Features” are
available. However, the use of double-speed mode cuts
down on the number of options due to the fact that a
smaller cycle budget is available to the internal feature
controller. Table 6 gives the availability of the different
features in the double-speed mode.
Table 6 Feature status in double-speed mode
FEATUREAVAILABLEREMARKS
Balanceyes
Volumeyesadapted scale: range
from −96 dB to 0 dB
Fadenovolume change will be
instantaneous
Band-pass
filter
Overload
detection
Silence
detection
Muteyes
Peak positionnofixed to before
Treble, Bassno
Bass boostyes
De-emphasisyes
Clear
memory
Versatile pinsyesalthough no detection
Peak readoutyes
Because of the shift in scale of the volume control between
normal and double-speed mode, a step in volume of 6 dB
on switchover in either way should be compensated for by
adjusting the volume during a preferably muted transition
period.
7.6.2L
The double-speed mode feature can also be used to cut
down on power requirements. When the TDA1546T is
switched to the double-speed mode using control bit DSM,
and the system clock frequency is halved simultaneously,
the filters will operate correctly on data input at
OW-POWER OPTION USING DOUBLE-SPEED MODE
nofixed to flat response
no
no
yes
takes place these pins
respond to polarity
setting
TDA1546T
normal-speed. The same feature restrictions as in the
double-speed mode apply, as does the filter performance
specified for double-speed mode. The current
consumption of the digital supply voltage is halved
because of the lower absolute clock speed. In terms of
conversion accuracy of the digital-to-analog converter
section, some performance will however be sacrificed.
7.7Volume control features
Features related to volume control are the digital balance
control, digital volume control with fade function and the
digital soft-mute. Their operation is described below.
7.7.1D
Table 7 Digital balance
The balance value from 1111 to 0000 can be obtained
using the following equation;
Balance = −1.5 dB × (15 − balance setting)
At extremely low volume settings (see Section 7.7.2) the
range of effect of the balance control will be limited. The
balance control effect will not go beyond an overall
attenuation of 89.55 dB (balance plus volume control).
7.7.2DIGITAL VOLUME CONTROL WITH FADE FUNCTION
One of the features of the TDA1546T is an advanced
digital volume control with inherent fading function. Only
the desired volume and the fade speed need to be
instructed to the TDA1546T, via the microcontroller
interface. The single-bit flag RUNFA can then be used to
inhibit or execute the volume change operation. When
RUNFA = 0, the volume control settings can be changed
without effect on the output. When RUNFA is then set to 1,
the TDA1546T autonomously performs an automatic
fade-in or fade-out to the desired volume by a natural,
exponential approach. It allows for volume control to an
accuracy of 0.375 dB from a gain of 6 dB of full-scale to
−90 dB in normal-speed, and a range of 0 dB of full-scale
to −96 dB in double-speed mode (see Tables 8 and 9).
IGITAL BALANCE
BAL3 TO BAL0
BAR3 TO BAR0
1 1 1 10
1 1 1 0
....
0 0 0 1
0 0 0 0−22.5
LEVEL (dB)
−1.5
...
−21.0
January 199517
Page 18
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
In normal-speed operation the fade time can be set over a
wide range, varying from 6 ms to over 20 seconds for a
complete fade. The fade time is completely determined by
the fade time setting and is independent of the amount of
volume change programmed. This means that a smaller
volume step will take the same amount of time but using a
less steep slope than a larger volume change with the
same fade time setting.
In the double-speed mode the fade option is not available.
Regardless of the current fade speed setting, a volume
change in double-speed mode will take effect immediately,
i.e. the next audio sample instant. Volume control data is
in 2 nibbles and can be set in 256 steps. The relationship
between command and output is shown in Tables 8 and 9.
Table 8 Volume control
VC7 TO VC0VC (DEC)
1111 11112556.020
1111 1110
....
1111 0000
1110 1111
....
0000 0001
0000 00000−∞−∞
254
...
240
239
...
1
VOLUME LEVEL
NSDS
5.64
....
0.37
0.00
....
−89.55
−0.37
....
−5.64
−6.02
....
−95.57
TDA1546T
The gain value ranging from 1111 1111 to 0000 000 can
be converted to its logarithmic counterpart by the following
equations:
Normal-speed mode:
Gvolume setting 239–()
Example: attenuate data for 1111 11110:
A254 239–()
Double speed mode:
Gvolume setting 255–()
Example: attenuate data for 1111 11110:
A254 255–()
The fade time from 0000 to 1111 can be converted by
using the following equation:
Fade time
Example: fade time for 0010 at f
fade time = 3 × 33 × 256/44100 = 0.57 s
In Fig.11, a few fading examples illustrate the operation of
the TDA1546T advanced digital volume control.
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
(1) A = fade-out to zero volume (VC = 0; RUNFA = 1).
(2) B = fade-in to maximum volume (RUNFA = 0; VC = 256; RUNFA = 1).
(3) C = volume decrease (RUNFA = 0; VC = XXX; RUNFA = 1).
(4) D = volume regulation override by resetting RUNFA to 0.
(5) E = volume regulation resumed by resetting RUNFA to 1.
(6) F = volume regulation stops at programmed level XXX.
(7) G = fade-in to maximum level (RUNFA = 0; VC = 256; RUNFA = 1).
(8) H = change in fade time (RUNFA = 0; FT = xxx; RUNFA = 1).
(9) I = fade-out to lower volume level and fade time change (RUNFA = 0; new VC; new FT; RUNFA = 1).
(10) J = volume regulation stops at programmed level.
Note: for illustration only, axes vary in scale.
TDA1546T
Fig.11 Volume control example.
7.7.3DIGITAL SOFT-MUTE
Soft mute is controlled by the microcontroller register file
bit MUTE. When the bit is active HIGH the value of the
samples is decreased smoothly to zero following a cosine
curve. To step down the value of the data 32 coefficients
are used, each one being used 32 times before stepping
onto the next. This amounts to a mute transition time of
23 ms at fs= 44.1 kHz. When the MUTE bit is LOW, the
samples are returned to the full level again following the
same cosine curve in reverse order. Mute is synchronized
to the sample clock, so that operation always takes place
on complete samples.
7.7.4S
CALING AND POLARITY OF THE DIGITAL
-SAMPLING FILTER
UP
The scaling factor of the digital up-sampling filter can be
selected by means of register file bits OUTS1 and OUTS0.
Only those modes controlled by bit OUTS0 are actually
useful, the other two are reserved modes and should not
be used.
In the configuration with the default initialization
(OUTS0 = 0), the TDA1546T is inverting, meaning that a
positive pulse contained in the digital input data is
converted to a negative pulse on the analog outputs. This
polarity and scaling is identical to that used in TDA1305T.
The TDA1546T can be made non-inverting by setting bit
OUTS0 in the microcontroller register file. The complete
truth table for these bits is shown in Table 10.
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
7.8Sound processing related features
7.8.1D
The TDA1546T incorporates selectable digital
de-emphasis filters, dimensioned to produce the
de-emphasis frequency characteristics for each of the
three possible sample rates 32, 44.1 and 48 kHz. With its
18-bit dynamic range, the digital de-emphasis of the
TDA1546T is a convenient and component-saving
alternative to analog de-emphasis.
Selection of the de-emphasis filters is performed via the
microcontroller interface, bits DEMC1 and DEMC0. The
programming is given in Table 11.
Table 11 De-emphasis mode programming
DEMC1DEMC0DE-EMPHASIS FUNCTION
E-EMPHASIS FILTER
0 0de-emphasis disabled
0 1de-emphasis for fs= 32.0 kHz
1 0de-emphasis for f
1 1de-emphasis for f
= 44.1 kHz
s
= 48.0 kHz
s
TDA1546T
7.8.4BASS BOOST
A strong bass boost effect, which is useful in
compensating for poor bass response of portable
headphone sets, is implemented digitally in the TDA1546T
and can be controlled in 14 steps using the microcontroller
bits SCBB3 to SCBB0. Valid settings range from “flat” (no
influence on audio) to +37 dB with step sizes varying from
3 dB (lower boosts) to 2.5 dB to 2 dB (higher boosts). The
SCBB value 15 is a reserved value and should not be
used. (see Table 12). The programmable bass boost filter
is a second-order shelving type with a fixed corner
frequency of 250 Hz and has a Butterworth characteristic.
Because of the exceptional amount of programmable gain,
bass boost should be used in conjunction with adequate
prior attenuation, using the volume control. The bass stage
and the bass boost stage operate independently so that
the ultimately attainable gain for low frequencies may
reach a total boost of approximately 50 dB.
7.8.5D
IGITAL DYNAMIC BASS BOOST, DIGITAL LOUDNESS
AND OTHER DYNAMIC APPLICATIONS OF TONE
CONTROL
7.8.2TREBLE
A digital treble gain (up to 12 dB in steps of 1.5 dB or cut
down to −10.5 dB in steps of 1.5 dB) can be applied to
boost or attenuate high-range signal content. The
microcontroller bits SCT3 to SCT0 select the treble
characteristic to be applied, the effect of which is shown in
Table 12. The programmable treble filter is a first-order
shelving type with a fixed corner frequency of 2.1 kHz. In
the “flat” position the treble stage has no influence on the
audio signal path. Because of the possibility of treble boost
beyond the available digital headroom causing overload of
high frequency range signals, the higher positive treble
boost values should generally be used in conjunction with
an approximately corresponding attenuation using the
volume control function.
7.8.3B
Digital bass control can be applied under control from the
microcontroller via control bits SCB3 to SCB0
(see Table 12) to achieve a moderate bass enforcement
or attenuation. The programmable bass filter is a
first-order shelving type with a fixed corner frequency of
500 Hz. In the “flat” position the bass stage has no
influence on the audio signal path. Higher bass settings
should generally be compensated by approximately equal
attenuation using the volume control to avoid digital
overload of basses.
ASS
Because of the integration of volume control, tone control
and level monitoring functions in the TDA1546T, a wide
range of dynamic tone and level control applications is
made available. These can be defined in software by the
user, thereby replacing and improving on components
formerly used to perform these functions in the analog
domain. Among these applications the most popular are
dynamic bass boost and loudness. Because the volume
setting is known in the system controller, it can, for
instance, be used directly to determine an appropriate
amount of bass boost. This avoids the signal level
dependent ‘sighing’, ‘pumping’ and distortion effects
typical of analog dynamic bass boost circuits. Depending
on the headroom made available by the current volume
setting, applying a bass boost of up to 30 dB, combined
with a slight treble boost (up to 6 dB) will achieve a typical
dynamic bass boost effect of high sound quality.
Digital loudness can be realized using the current volume
setting to determine a suitable moderate bass gain (up to
approximately 15 dB is typical of loudness) and treble gain
(up to approximately 6 dB).
A further enhancement in dynamic tone control and signal
adaptation can be achieved by using the peak monitoring
function (either with a flat response or using the band-pass
filters) or overload detection (which can also be made
frequency-selective) in your dynamic tone control
algorithm.
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
7.8.6DIGITAL SPEAKER SYSTEM MODE
The TDA1546T can be used as a two-way digital
crossover filter and digital preamplifier in a digital speaker
system. In the DSS mode, one TDA1546T is used per
loudspeaker channel. The left channel of TDA1546T
drives the amplifier for the low frequency transducer and
the right channel drives the high-frequency power
amplifier. The digital crossover filter is activated by setting
the control bit DSS to 1 and the 4-bit bass boost value to
its reserved value of 15. Figure 15 shows the frequency
transfer function of the digital crossover filter.
The auxiliary bit LONLY (left only) can be set to enable a
special internal channel-copying mode. The left-channel
data input is copied internally to the right channel via the
Fig.15 Digital crossover filter frequency response.
7.9Sound monitor block
The sound monitor block consists of a spectrum analyzer,
silence detection, peak detection, overload detection and
versatile output pins. The position of the sound monitor
block can be programmed using microcontroller bit SPOS.
When SPOS = 1 the sound monitor block precedes the
tone control sections. When SPOS = 0 the sound monitor
block succeeds the tone control sections.
January 199523
input data bus and the incoming right channel data is ‘don't
care’. This simplifies interfacing at the input data bus level.
Direct connection of the WS line to the TDA1546T
appoints the TDA1546T as the left channel processor, and
placing an inverter in series with the WS input results in the
processing of the right channel data only, thereby
appointing the TDA1546T as right channel processor.
Consequently, by using LONLY, the normal
time-multiplexed I
rather than a dedicated left or right channel bus.
Due to the nature of the digital crossover filter, the digital
speaker mode must be used with volume set to −0.375 dB
(one unit step below 0 dB) to preclude any occurrence of
digital clipping.
7.9.1SPECTRUM ANALYZER
The spectrum analyzer is constructed of a second-order
band-pass filter (where the centre frequency is selectable)
followed by a resettable peak detector, silence detector
and overload detector. The band-pass filter can be set to
7 different frequency bands plus one flat response. The
7 bands are equally spaced in the audio band with a ratio
of 1:2.3, which is slightly wider than octave bands. The
centre frequencies are given in Table 13.
TDA1546T
2
S-bus or other format can be used
Page 24
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
To scan the whole audio band with one filter, the filter must
be switched between the 7 bands. This switching causes
a transient which takes time to settle. The settling time is
dependent on the bandwidth and is slowest for the low
FREQUENCY
BAND
SETTLING TIME
TO −40 dB OR
1% (ms)
TDA1546T
frequency bands, e.g. the 189 Hz band takes
approximately 16 ms to settle to 1% or −40 dB (i.e. the
settling rate is 8 ms per 20 dB). For all bands except the
99 Hz band, the settling rate is inversely proportional to the
bandwidth and therefore to the centre frequency. The
99 Hz filter behaves differently because it is, in essence, a
first-order low-pass filter.
The settling time of the switchable band-pass filter calls for
attention to waiting times when used in a spectrum
analyzer application. A waiting time is necessary to allow
the switching transient to settle. A “dummy” peak readout
will then reset the peak detection register to zero, after
which instant new frequency-dependent peak data can be
accumulated. The time needed to accumulate valid peak
information depends on the centre frequency and
bandwidth of the band involved, thus a second waiting time
will need to be implemented. A peak read action performed
after this second waiting time will return an accurate output
value.
Fig.16 Spectrum analyzer frequency response.
January 199524
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Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
TDA1546T
digital sound processing (BCC-DAC)
7.9.2dB CONVERTER
Before peak data is output, the detected value is converted
from linear to a dB scale internally by the TDA1546T. This
has the following advantages:
• ease calculation load on the system microcontroller
• optimal use of dynamic range of the readout
• facilitate manipulation of sound processing control
levels in combination with peak readout levels, to allow
for e.g. dynamic tone control.
The internal linear peak detection occurs with a resolution
of 16 bits on the incoming left and right audio samples
individually. This linearly acquired value is converted to
dB's as shown in Table 14. Because of quantization of the
linear code, accuracy is lower for the very lowest detected
peak values. Some values in the lower range of the dB
scale have no counterpart in the linear scale, consequently
these values never occur as output peak words. This is
also illustrated in Table 14). The dB conversion block
converts only positive linear values to a a useful dB value.
All negative input values will be converted to an output
value of 3 for recognition.
PEAK
DATA
PEAK V ALUE
(dB)
PEAK
DA TA
PEAK VALUE
(dB)
Note
1. The peak level dB conversion block relates according to the following transfer formula from linear to dB scale:
a) Peak value (dB) = (peak data − 63.5) × 5 × log 2
b) The table should be read as follows. The maximum value of 63 (111111) is returned when the detected value
resides between −1.48 dB and 0 dB, the next lower value of 62 is returned when the detected value resides
between −2.87 dB and −1.48 dB etc. Only true digital silence will return a peak readout value of 000000.
c) For peak data > 010011 (= 19) the error in peak level is <(11 × log 2)/4
d) For peak data <010100 (= 20) the error will be larger due to 16 bits accuracy.
7.9.3PEAK DETECTION
The TDA1546T provides a convenient way to monitor the
peak value of the audio data, for left and right channels
individually, by way of readout via the microcontroller
interface. Peak value monitoring has its applications
mainly in digital volume unit measurement and display,
and in automatic recording level control. The peak level
measurement of the TDA1546T occurs with a resolution of
16 bits thus providing a dynamic range amply suitable for
all practical applications.
The output of the peak detection block is a register of two
6-bit words (one for each channel) which represents the
dB linear value of the positive peak value and is accessible
via the microcontroller interface. The peak detection block
continuously monitors the audio information arriving from
the spectrum analyzer, comparing its actual dB value to
the value currently stored in the peak register. Any new
value greater than the currently held peak value will cause
the register to assume the new, greater value. On a peak
request (see Section 7.3) the contents of the peak register
are transferred to the microcontroller interface. After a
read action the peak register will be reset and the
collection of new peak data started. The end of a peak
read action should be marked by an address mode
sequence so that the output peak register is able to latch
new data.
The peak detection block receives data that has been
processed by the de-emphasis block, so if peak data is
read when applying digital de-emphasis, the de-emphasis
frequency characteristic will be noticeable in the peak
output value.
January 199525
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Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
The peak data readout protocol is illustrated in Fig.7. A
peak request is performed by activating the address mode
of the microcontroller interface (see Table 2). Upon the
peak request, the microcontroller will commence collecting
data from the internal peak data output register (dB linear,
6-bit left, 6-bit right) on the LOW-to-HIGH transition of
L3CLK by sending a clock onto the L3CLK line. The first
and last bits of the byte (bit 0 and bit 7 in Fig.7) are
padding bits with default set to zero. The first peak bit
(bit 1), is the LSB of the channel peak value. The contents
of the peak data output register will not change during the
peak request. The peak data readout procedure may be
aborted at any instant by returning to the address mode,
thereby marking the end of the peak request.
7.9.4S
The TDA1546T is designed to detect silence conditions in
the left and right channels, separately or combined, and
report this via the versatile outputs VERS1 and VERS0
(see Section 7.9.6). The function is programmable in
silence level (dB linear via microcontroller register bits
SIL3 to SIL0) and silence duration (SILT3 to SILT0) and is
implemented to allow external manipulation of the audio
signal upon absence of program material, such as muting
or recorder control. The silence levels and silence duration
timings are given in Table 15.
The TDA1546T itself does not influence the audio signal
as a result of digital silence. The sole function of this block
is detection, and any further treatment must be
accomplished by other means. Silence detected is TRUE
when the corresponding channel carries samples smaller
than the programmed value for at least the duration of the
programmed time. As a separated left/right digital silence
detection is not always needed, the logic “AND” function of
both left and right digital detection circuits can be logically
combined to a mono digital silence indication on pin
VERS0, programmed via register control bits PINM1 and
PINM0.
7.9.5O
A level programmable overload detection is present to
facilitate applications in digital volume unit measurement
and display, and in automatic recording level control. The
overload condition of the audio data for left and right
channels, individually or combined, is reported via the
versatile outputs VERS1 and VERS0 (see Section 7.9.6).
The overload levels are given in Table 16.
Table 16 Overload detection level
OVER3 TO OVER0DETECTION LEVEL (dB)
The overload detection level from 0000 to 1111 can be
obtained using the following equation:
Overload if peak level > (2 × OVER − 31) × 5log 2
Overload detected is TRUE when the corresponding
channel carries samples greater than the programmed
value. A condition of detected overload will be held until
peak data is read out from the TDA1546T. This implies that
a continuous overload indication (also via the versatile
outputs) will function properly only with periodic peak
readout taking place. As a separated left/right digital
overload detection is not always needed, the logic “OR”
function of both left and right digital detection circuits can
be logically combined to a mono digital overload indication
on pin VERS1, programmed via register control bits
PINM1 and PINM0.
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
7.9.6VERSATILE OUTPUTS
Table 17 Versatile output pin control
REGISTER BITOUTPUT MODE
PINM1PINM0VERS1VERS0
00mono overload detectionmono silence detection
01left overload detectionright overload detection
10left digital silence detectionright digital silence detection
11no detectionno detection
PVIV1 = 0VERS1 is active HIGH
PVIV1 = 1VERS1 is active LOW
PVIVO = 0VERS0 is active HIGH
PVIV0 = 1VERS0 is active LOW
7.10Noise shaper
In the normal-speed mode the second-order noise shaper
operates at 96fs (f
double-speed mode the noise shaper operates at 48f
(f
= 384fs) or 64fs (f
sys
= 384fs) or 128fs (f
sys
= 256fs). It shifts in-band
sys
= 256fs). In the
sys
s
quantization noise to frequencies well above the audio
band. This noise shaping technique used in combination
with a special data coding enables extremely high
signal-to-noise ratios to be achieved. The noise shaper
outputs a 5-bit PDM bitstream signal to the DAC.
7.12Operational amplifiers
The operational amplifiers and the internal conversion
resistors R
CONV1
and R
CONV2
an output voltage which is made available at pins VOL and
VOR (typ 1.5 V RMS). Connecting an external capacitor
between FILTCL and VOL, FILTCR and VOR respectively
provides the required first-order post filtering for the left
and right channels.
The dual 5-bit DAC uses the continuous calibration
technique. This method, based on charge storage,
involves exact duplication of a single reference current
source. In the TDA1546T, 32 such current sources plus
one spare source are continuously calibrated. The spare
source is included to allow continuous converter operation.
The DAC receives a 5-bit data bitstream from the noise
shaper. This data is then converted so that only small
currents are switched to the output during digital silence
(input 00000H). In this way extremely high-noise
performance is achieved.
The Internal reference circuitry ensures that the output
voltage signal is proportional to the supply voltage, thereby
maintaining maximum dynamic range for supply voltages
from 3.8 to 5.5 V. The reference voltage output (pin 26) is
intended for external decoupling of the reference voltage.
It is a high-impedance output and should not be used to
drive external loads, otherwise the performance of the
TDA1546T's analog circuitry will be impaired. The voltage
at V
is typically 50% of the analog supply voltage (V
ref
DDA
).
January 199527
Page 28
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
TDA1546T
digital sound processing (BCC-DAC)
8LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOLPARAMETERCONDITIONSMIN.MAX.UNIT
V
DD
T
xtal
T
stg
T
amb
V
es
Notes
1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.
2. Equivalent to discharging a 200 pF capacitor through a 2.5 µH inductor.
word select input frequencynormal-speed2544.148kHz
double-speed5088.296kHz
rise time−−20ns
fall time−−20ns
bit clock time HIGH55−− ns
bit clock time LOW55−− ns
data set-up time40−− ns
data hold time10−− ns
word select set-up time40−− ns
word select hold time10−− ns
= 1% of the supply voltage; f
ripple
= 100 Hz.
V
MHz
MHz
January 199530
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Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
TDA1546T
digital sound processing (BCC-DAC)
12 ANALOG CHARACTERISTICS
V
=5V; VSS=0V; T
DD
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
Reference values
V
R
ref
CONV
reference voltage level2.452.52.55V
current-to-voltage
conversion resistor
Analog outputs
RESresolution−−18bit
t
dg
V
FS(rms)
group delayfs= sample rate;
full-scale output voltage
(pins 22 and 25) (RMS
value)
V
DC(os)
output voltage DC offset
with respect to reference
voltage level V
Table 20 De-emphasis: deviation from ideal 50 ms to 15 ms characteristic
ITEMSAMPLE FREQUENCYRANGECHARACTERISTICS
Gain deviation44.1 and 48 kHz0 to 18 kHz0 ±0.05 dB
18 to 20 kHz<0.12 dB
32 kHz0 to 13 kHz0 ±0.06 dB
13 to 15 kHz<0.22 dB
Phase deviation44.1 and 48 kHz0 to 15 kHz<10 deg
15 to 20 kHz<15 deg
32 kHz0 to 9 kHz<10 deg
9 to 15 kHz<16 deg
13.2Example application circuit
An example of an application circuit, the schematic for a
printed-circuit board available for evaluation, is shown in
Fig.20. The following are shown:
• the typical connection of the power-on reset pin using a
timing capacitor
• circuitry surrounding the XTAL1 and XTAL2 pins which
can be configured to either crystal oscillator mode
(master mode) or external system clock input mode
(slave mode)
• an example connection for LED indication of digital
silence and overload detection (the inverters are
optional, used as buffers. The polarity of the versatile
output pins programmed via PVIV1 and PVIV0 should
reflect the connection polarity of the indicator LEDs)
• typical decoupling connection for the V
• typical low component count stereo line output stage (no
additional filtering and therefore no external operational
amplifiers needed).
ref
pin
January 199534
Page 35
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
14 PACKAGE OUTLINE
handbook, full pagewidth
S
pin 1
index
114
0.9
0.4
(4x)
18.1
17.7
0.1 S
TDA1546T
7.6
7.4
10.65
10.00
1528
1.1
2.45
2.25
0.3
0.1
detail A
1.0
0.32
0.23
1.1
0.5
0 to 8
MBC236 - 1
A
2.65
2.35
o
Dimensions in mm.
1.27
0.49
0.36
0.25 M
(28x)
Fig.21 Plastic small outline package; 28 leads; body width 7.5 mm (SO28; SOT136-1).
January 199536
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Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
15 SOLDERING
15.1Plastic small-outline packages
15.1.1B
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
YWAVE
TDA1546T
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
15.1.3R
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.).
EPAIRING SOLDERED JOINTS (BY HAND-HELD
SOLDERING IRON OR PULSE
-HEATED SOLDER TOOL)
15.1.2B
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
16 DEFINITIONS
Data sheet status
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
17 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Y SOLDER PASTE REFLOW
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement
January 199537
Page 38
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
NOTES
TDA1546T
January 199538
Page 39
Philips SemiconductorsPreliminary specification
Bitstream Continuous Calibration DAC with
digital sound processing (BCC-DAC)
NOTES
TDA1546T
January 199539
Page 40
Philips Semiconductors – a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)
BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. (02)805 4455, Fax. (02)805 4466
Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,
Tel. (01)60 101-1236, Fax. (01)60 101-1211
Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,
CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556
Uruguay: Coronel Mora 433, MONTEVIDEO,
Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
513061/1500/01/pp40Date of release: January 1995
Document order number:9397 746 30011
Philips Semiconductors
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