Datasheet TDA1548TZ, TDA1548T Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA1548T

Bitstream continuous calibration
filter-DAC with headphone driver
and DSP

Product specification
Supersedes data of 1995 Aug 02
File under Integrated Circuits, IC01

1995 Nov 15

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC
with headphone driver and DSP

FEATURESPRODUCT SPECIFICATION
Easy application

• Only first-order analog post-filtering required

• Headphone amplifiers and digital filter integrated

• Component saving common headphone output

• Selectable system clock (SYSCLK) 64f

• 16, 18 or 20 bits I2S-bus or LSB justified serial input

format

• Input pins suitable with 5 V low supply voltage
interfacing

• Small package (SSOP28)

• Single rail supply (3 V).

High performance

• Superior signal-to-noise ratio

• Wide dynamic range

• Continuous calibration digital-to-analog conversion

combined with noise shaping technique.

Features

• Low power dissipation

• Digital volume control

• Soft mute

• Digital tone control (Bass Boost and Treble)

• Digital de-emphasis

• Analog control of digital sound control functions.

GENERAL DESCRIPTION

The TDA1548T is a dual CMOS digital-to-analog converter
(DAC) with up-sampling filter and noise shaper and

, 256fs or 384f

s

s

TDA1548T

integrated headphone driver featuring unique signal
processing functions. The digital processing features are
of high sound processing quality due to the wide dynamic
range of the bitstream conversion technique.

The TDA1548T supports the I2S-bus data input mode with
word lengths of up to 20 bits and the LSB justified serial
data input format with word lengths of 16, 18 or 20 bits.
The clock system is selectable (64fs, 256fs or 384fs) by
means of selection pins. Two cascaded half band filters,
linear interpolator and a sample-and-hold function
increase the oversampling rate from 1fs to 64fs.
A second-order noise shaper converts this oversampled
data into a bitstream for the 5-bit continuous calibration
DACs.

On board amplifiers convert the output current to a voltage
signal capable of driving a headphone or line output.
The common operational amplifier application eliminates
the need for capacitors.

The TDA1548T has some sound processing functions
which are controllable by a potentiometer. These functions
are volume, bass boost and treble. The flat/min/max
switch can also be controlled by a potentiometer.
The analog values are converted to a digital code, which is
then further translated internally to a set of coefficients for
either volume, bass boost or treble.

ORDERING INFORMATION

TYPE

NUMBER

TDA1548T SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1

TDA1548TZ SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

1995 Nov 15 2

NAME DESCRIPTION VERSION

PACKAGE

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC

TDA1548T

with headphone driver and DSP

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

I

DD

V

oFS(rms)

(THD+N)/S total harmonic distortion

S/N signal-to-noise ratio A-weighted;

BR input bit rate at data input f

f

sys

TC

FS

T

amb

supply voltage note 1 2.7 3.0 4.0 V
supply current note 2 − 15 − mA
full-scale output voltage VDD= 3 V 0.57 0.64 0.71 V

0 dB signal −−65 −60 dB
plus noise as a function of
signal

0 dB signal; R

=5kΩ− −85 −78 dB

OL

− 0.056 0.1 %

− 0.006 0.013 %

−60 dB signal; R

or ROL=5kΩ

OL

=32Ω

−−35 −30 dBA

− 1.778 3.162 %

90 95 − dBA

at code 00000H

f

f

sys
sys
sys

= 384f
= 256f
= 64f

s

s

s

− 48f

− 64f

− 64f

s

s

s

−

−

−

system clock frequency 2.048 − 18.432 MHz
full-scale temperature

−±100 × 10−6−
coefficient at analog
outputs (VOL and VOR)

operating ambient

−20 − +70 °C
temperature

Notes

1. All VDD and VSS pins must be connected to the same supply or ground respectively.

2. Measured at input code 00000H and VDD=3V.

1995 Nov 15 3

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC
with headphone driver and DSP

BLOCK DIAGRAM

handbook, full pagewidth

SYSCLK

CLSEL

MODE0

MODE1

12

TIMING

17

5

6

IF1 IF2 DATA WS BCK

13

14 9 8 7

SERIAL DATA INPUT

VOLUME CONTROL

SOFT MUTE CONTROL

SOUND CONTROL

FILTER STAGE 1

FILTER STAGE 2

LINEAR INTERPOLATOR

8 x OVERSAMPLING

(SAMPLE-AND-HOLD)

1 f

s

2 f

s

4 f

s

8 f

s

8 x OVERSAMPLING

(SAMPLE-AND-HOLD)

V

DDA

V

SSA

VOLUME

AND

SOUND

CONTROL

−

OP4

+

TDA1548T

16

MUTE

15

DEEM

22

AD3S

21

ADVC

20

ADBB

19

ADTR

18

AD

ref

1.8 nF

CEXT1

10

µF

V

VOL

V

ref

SSA

2nd ORDER

NOISE SHAPER

DATA

ENCODER

4

R

CONV1

1.2 kΩ 1.2 kΩ

3

V

DDA

25

V

SSA

OP1

6 kΩ

6 kΩ

V

−
+

SSO

16 (4-bit)

CALIBRATED

CURRENT
SOURCES

LEFT

OUTPUT

SWITCHES

16 (4-bit)

CALIBRATED

CURRENT

SINKS

V

DDO

REFERENCE

SOURCE

+

V

NOISE SHAPER

−

OP3

COM

2nd ORDER

DATA

ENCODER

16 (4-bit)

CALIBRATED

CURRENT
SOURCES

RIGHT

OUTPUT

SWITCHES

16 (4-bit)

CALIBRATED

CURRENT

SINKS

V

232281

DDA

R

CONV2

−

OP2

+

TDA1548T

24

V

SSA

11

10

26

27

MGC668

FILTCRFILTCL

VOR

V

SSD

V

DDD

1.8 nF
CEXT2

Fig.1 Block diagram.

1995 Nov 15 4

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC
with headphone driver and DSP

PINNING

SYMBOL PIN DESCRIPTION

V

SSO

V

COM

VOL 3 left channel audio voltage output
FIL TCL 4 capacitor for left channel first-order

MODE0 5 mode 0 selection pin
MODE1 6 mode 1 selection pin
BCK 7 bit clock input
WS 8 word select input
DATA 9 data input
V

DDD

V

SSD

SYSCLK 12 system clock 64f
IF1 13 input format selection 1
IF2 14 input format selection 2
DEEM 15 de-emphasis input (f

MUTE 16 soft-mute input (active HIGH)
CLSEL 17 system clock selection input
AD

ref

ADTR 19 analog sense input for treble

ADBB 20 analog sense input for bass boost

ADVC 21 analog sense input for volume

AD3S 22 3-position switch input for

V

DDA

V

SSA

V

ref

FILTCR 26 capacitor for right channel

VOR 27 right channel audio voltage output
V

DDO

1 operational amplifier ground
2 common output pin

filter function should be connected
between this pin and VOL (pin 3)

10 digital supply voltage
11 digital ground

, 256fs or 384f

s

= 44.1 kHz)

s

(active HIGH)

18 reference voltage output to

external potentiometer

setting

setting

control setting

flat/min/max setting
23 analog supply voltage
24 analog ground
25 internal reference voltage

(0.5V

DDA

typ)

first-order filter function should be

connected between this pin and

VOR (pin 27)

28 operational amplifier supply

voltage

s

handbook, halfpage

1

V

SSO

2

V

COM

3

VOL

BCK

4
5
6
7

FILTCL

MODE0

MODE1

TDA1548T

8

WS

9

DATA

10

V

DDD

11

V

SSD

IF1
IF2

12
13
14

MGC669

SYSCLK

Fig.2 Pin configuration.

TDA1548T

28

V

DDO

27

VOR

26

FILTCR

25

V

ref

24

V

SSA

23

V

DDA

22

AD3S

21

ADVC

20

ADBB

19

ADTR

18

AD

ref

17

CLSEL

16

MUTE

15

DEEM

1995 Nov 15 5

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC
with headphone driver and DSP

FUNCTIONAL DESCRIPTION

The TDA1548T CMOS DAC incorporates an up-sampling
digital filter, a linear interpolator, a noise shaper,
continuous calibrated current sources and headphone
amplifiers. The 1fs input data is increased to an
oversampling rate of 64fs. This high-rate oversampling,
together with the 5-bit DAC, enables the filtering required
for waveform smoothing and out-of-band noise reduction
to be achieved by simple first-order analog post-filtering.

System clock and data input format

The TDA1548T accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable at pins CLSEL, MODE0 and MODE1
(see Table 1).

The TDA1548T supports the following data input modes
(see Table 2):

2

S-bus with data word length of up to 20 bits

I
LSB justified serial format with data word length of 16,

18 or 20 bits.

TDA1548T

For each multiplexed timeslot the full approximation cycle
is completed, immediately after which the next input will
start being sampled.

The time slot for one input lasts 64 steps at a step advance
rate of 8 × f
Because four inputs are multiplexed, the sample rate for
each analog input is 1.38 kHz.

A buffered version of an internally generated reference
voltage is available at output pin AD
internal AD derives from the same reference voltage, this
allows for optimum mapping of the external analog control
value onto the useful AD input voltage range. The idea is
to bias a potentiometer to AD
the input voltage between 0 V and AD
implemented to improve noise immunity of the AD in order
to prevent a stable setting of the potentiometer, to a point
near a quantization threshold, from producing two
alternating digital codes which could give rise to audible
volume or boost changes. An hysteresis of 1 LSB is
implemented digital. A shift in code must be at least 2 LSB
either up or down from the current value, otherwise the
internal digital code will remain at the current value.

, which amounts to 181 µs at fs= 44.1 kHz.

s

. Because the

ref

, using a wiper to control

ref

. Hysteresis is

ref

The input formats are illustrated in Fig.4. Left and right
data-channel words are time multiplexed.

Analog control of digital sound processing features

Digital sound processing settings are controlled via analog
sense inputs that translate an analog voltage from, for
example, a potentiometer wiper to a digital code, which is
then further translated internally to a set of coefficients for
either treble, bass boost or volume.

The analog input value is acquired by an internal 6-bit
ADC, sampling the three input pins ADVC, ADBB and
ADTR and the three-mode selection pin ADS3 (see
Section “Single pin three mode selection”) in a multiplexed
fashion. Sampling of the input voltage is performed by a
straight forward technique of linear approximation; from
the starting value of 0 V, an internal linear approximation
voltage is incremented periodically in steps of 1/66th of the
scale, with an internal comparator detecting when the
approximation value oversteps the input value. Tolerance
is built in at the top and bottom end of the scale by
dimensioning the resistive elements at the top and bottom
of the ladder equals 1R. Thus the ladder is built up of
64 elements of value R, two of value R, making a typical
quantization step size of approximately 1.5 V (AD

ref

)

divided-by-66 (amount of Rs), equals 22.7 mV.

S

INGLE PIN THREE MODE SELECTION

A special input pin AD3S (pin 22), controls the mode in
which the sound processing block operates. Not between
two but three modes; whether the DSP should follow the
AD inputs applying maximum effect, the minimum effect or
overrule the boost effects thereby resulting in a flat
frequency characteristic in the treble and bass boost
sections.

Internally the same AD is used to detect the input level
present at this pin as is used for the three sound control
pins. An internal bias circuit containing of two MOSTs
supplies a mid-range voltage so that this input can be
operated with a minimum of external components. A HIGH
or LOW input level is created by tying the pin to AD

ref

or
ground respectively, the intermediate value is achieved by
leaving the pin open-circuit.

Volume control

Since there is no headroom included into the sound control
section, the volume control precedes the sound control.
Full volume and neutral setting (flat) of the sound control
results in a full-scale output. Any tone boost will
immediately cause clipping, which can be avoided by
reducing the volume setting.

1995 Nov 15 6

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC
with headphone driver and DSP

Soft mute

Soft mute is controlled by MUTE (pin 16). When the input
is active HIGH the value of the sample is decreased
smoothly to zero following a raised cosine curve.
32 coefficients are used to step down the value of the data,
each one being used 32 times before stepping on to the
next. This amounts to a mute transition time of 23 ms at
fs= 44.1 kHz. When MUTE is released (LOW), the
samples are returned to the full level again following a
raised cosine curve with the same coefficients being used
in the reverse order. Mute is synchronized to the sample
clock, so that the operation always takes place on
complete samples.

Digital sound processing features

BASS BOOST
A strong bass boost effect, which is useful in

compensating for poor bass response of portable
headphone sets, is implemented digitally in the TDA1548T
and can be controlled by ADBB (pin 20) and AD3S
(pin 22). Table 3 shows the bass boost values at different
input voltages. Table 4 shows the selection mode status
(flat/min/max) at different input voltages. Valid settings
range from “flat” (no influence on audio) to +18 dB with
step sizes of 2 dB in “minimum” and to +24 dB with step
sizes of 2 dB in “maximum”. The programmable bass
boost filter is a second-order shelving type with a fixed
corner frequency of 130 Hz for the “minimum” setting and
a fixed corner frequency of 230 Hz for the “maximum”
setting and has a Butterworth characteristic. Because of
the exceptional amount of programmable gain, bass boost
should be used in conjunction with adequate prior
attenuation, using the volume control.

T

REBLE

A treble effect is implemented digitally in the TDA1548T
and can be controlled by ADTR (pin 19) and AD3S
(pin 22). Table 3 shows the treble values at different input
voltages. Table 4 shows the selection mode status
(flat/min/max) at different input voltages. Valid settings
range from “flat” (no influence on audio) to +6 dB with step
sizes of 2 dB in “minimum” and to +6 dB with a step size of
2 dB in “maximum”. The programmable treble filter is a
first-order shelving type with a fixed corner frequency of

2.8 kHz for the “minimum” setting and a fixed corner
frequency of 5.0 kHz for the “maximum” setting.

D

E-EMPHASIS

De-emphasis is controlled by DEEM (pin 15). The digital
de-emphasis filter is dimensioned to produce the

TDA1548T

de-emphasis frequency characteristics for the sample rate

44.1 kHz. With its 18-bit dynamic range, the digital
de-emphasis of the TDA1548T is a convenient and
component-saving alternative to analog de-emphasis.

When the DEEM pin is active HIGH, de-emphasis is
enabled. De-emphasis is synchronized to the sample
clock, so that operation always takes place on complete
samples.

Oversampling filter and noise shaper

The digital filter is a four times oversampling filter.
It consists of two sections which each increase the sample
rate by 2.

The second order noise shaper operates at 64f
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique, used in
combination with a sign-magnitude coding, enables high
signal-to-noise ratios to be achieved. The noise shaper
outputs a 5-bit PDM bitstream signal to the DAC.

Continuous calibration DAC

The dual 5-bit DAC uses the continuous calibration
technique. This method, based on charge storage,
involves exact duplication of a single reference current
source. In the TDA1548T, 32 such current sources
plus 1 spare source are continuously calibrated.
The spare source is included to allow continuous converter
operation.

The DAC receives a 5-bit data bitstream from the noise
shaper. This data is converted to a sign-magnitude code
so that no current is switched to the output during digital
silence (input 00000H). In this way very high
signal-to-noise performance is achieved.

Component-saving stereo headphone driver

High precision, low-noise amplifiers together with the
internal conversion resistors R

CONV1

and R
the converter output current to a voltage capable of driving
a line output or headphone. The voltage is available at
VOL and VOR (0.64 V RMS typical).

A major component saving feature of the TDA1548T is that
no DC-blocking capacitors are needed in the application,
despite the asymmetrical supply. The V

COM

is biased to the same voltage that the right and left channel
voltage outputs are, V

, and is capable of sinking the sum

ref

of left and right channel load currents. Therefore,
connecting a load between one of the outputs and V
only gives rise to a negligible amount of DC current
through the load.

. It shifts

s

convert

CONV2

output, pin 2,

COM

1995 Nov 15 7

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC
with headphone driver and DSP

Table 1 System clock selection

PINS

CLSEL MODE0 MODE1

0 0 0 256f
0 0 1 64f
0 1 X reserved 1
1 0 0 384f
1 0 1 reserved 2
1 1 X reserved 3

Table 3 Relationship between VC, BB and TR

ANALOG INPUT VALUES (V);

PINS ADTR, ADBB AND ADVC

× 65/66 −00000

AD

ref

AD

× 64/66 −00000

ref

× 63/66 −10000

AD

ref

AD

× 62/66 −20002

ref

AD

× 61/66 −32222

ref

AD

× 60/66 −42222

ref

AD

× 59/66 −54422

ref

AD

× 58/66 −64422

ref

AD

× 57/66 −76644

ref

AD

× 56/66 −86644

ref

AD

× 55/66 −98844

ref

AD

× 54/66 −10 8 8 4 4

ref

× 53/66 −11 10 10 6 6

AD

ref

AD

× 52/66 −12 10 10 6 6

ref

AD

× 51/66 −13 12 12 6 6

ref

AD

× 50/66 −14 12 12 6 6

ref

× 49/66 −15 14 14 .... ....

AD

ref

AD

× 48/66 −16 14 14 .... ....

ref

× 47/66 −17 16 16 .... ....

AD

ref

AD

× 46/66 −18 16 16 .... ....

ref

AD

× 45/66 −19 18 18 .... ....

ref

AD

× 44/66 −20 18 18 .... ....

ref

AD

× /4366 −21 20 18 .... ....

ref

× 42/66 −22 20 18 .... ....

AD

ref

AD

× 41/66 −23 22 .... .... ....

ref

AD

× 40/66 −24 22 .... .... ....

ref

AD

× 39/66 −25 24 .... .... ....

ref

DESCRIPTION

s

s

s

VOLUME

(ADVC)

Table 2 Data input formats

PINS

IF1 IF2

00I
0 1 LSB justified, 16 bits
1 0 LSB justified, 18 bits
1 1 LSB justified, 20 bits

BASS BOOST

(ADBB)

MAX. MIN. MAX. MIN.

TDA1548T

FORMAT

2

S-bus

TREBLE (ADTR)

1995 Nov 15 8

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC
with headphone driver and DSP

ANALOG INPUT VALUES (V);

PINS ADTR, ADBB AND ADVC

AD

× 38/66 −26 24 .... .... ....

ref

× 37/66 −27 .... .... .... ....

AD

ref

AD

× 36/66 −28 .... .... .... ....

ref

.... .... .... .... .... ....

.... .... .... .... .... ....

AD

× 5/66 −59 24 18 6 6

ref

AD

× 4/66 −60 24 18 6 6

ref

× 3/66 −∞ 24 18 6 6

AD

ref

AD

× 2/66 −∞ 24 18 6 6

ref

Table 4 Relationship mode selection

ANALOG INPUT VALUE (V);

PIN AD3S

AD

× 65/66 flat

ref

AD

× 64/66 flat

ref

.... ....

.... ....

AD

× 51/66 flat

ref

AD

× 50/66 flat

ref

× 49/66 minimum

AD

ref

AD

× 48/66 minimum

ref

.... ....

.... ....

AD

× 19/66 minimum

ref

AD

× 18/66 minimum

ref

AD

× 17/66 maximum

ref

AD

× 16/66 maximum

ref

.... ....

.... ....

AD

× 3/66 maximum

ref

AD

× 2/66 maximum

ref

VOLUME

(ADVC)

TDA1548T

BASS BOOST

(ADBB)

MAX. MIN. MAX. MIN.

FLAT, MINIMUM OR MAXIMUM

TREBLE (ADTR)

1995 Nov 15 9

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC

TDA1548T

with headphone driver and DSP

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

T

xtal

T

stg

T

amb

V

es

Notes

1. All V

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor. Pin 18 = −1500 V (min) and +1500 V
(max).

3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.

THERMAL CHARACTERISTICS

supply voltage note 1 − 4.5 V
maximum crystal temperature − +150 °C
storage temperature −65 +125 °C
operating ambient temperature −20 +70 °C
electrostatic handling note 2 −3000 +3000 V

note 3 −300 +300 V

and VSS connections must be made to the same power supply.

DD

SYMBOL DESCRIPTION VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air

SO28 60 K/W
SSOP28 80 K/W

QUALITY SPECIFICATION

In accordance with UZW-BO/FQ-0601. The numbers of the quality specification can be found in the

Handbook”

. The Handbook can be ordered using the code 9397 750 00192.

“Quality Reference

1995 Nov 15 10

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC

TDA1548T

with headphone driver and DSP

DC CHARACTERISTICS

All voltages referenced to ground (pins 1, 11 and 24); V

DDD=VDDA=VDDO

common operational amplifier application; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
V
V
I

DDD

I

DDA

I

DDO

P

DDD
DDA
DDO

tot

digital supply voltage pin 10 note 2 2.7 3.0 4.0 V
analog supply voltage pin 23 note 2 2.7 3.0 4.0 V
opamp supply voltage pin 28 note 2 2.7 3.0 4.0 V
digital supply current at digital silence − 4.5 − mA
analog supply current at digital silence − 4.5 − mA
opamp supply current at digital silence; note 3 − 6.0 − mA
total power dissipation note 3 − 50 − mW

Digital inputs

V

IH

HIGH level input voltage on
pins 5 to 9 and 12 to 17

V

IL

LOW level input voltage on
pins 5 to 9 and 12 to 17

|I

| input leakage current on

LI

pins 7 to 9 and 12 to 17

C

I

input capacitance on
pins 5 to 9 and 12 to 17

=3V; T

0.7V

−−0.3V

=25°C, RL=32Ω (note 1);

amb

DDD

−− V

DDD

V

−−10 µA

−−10 pF

Analog inputs pins ADVC, ADBB, ADTR and AD3S

RES input resolution −−6 bit
C

I

R

I

input capacitance − 10 − pF
input resistance pins ADBB, ADTR and ADVC 1 −− MΩ

pin AD3S − 20 − kΩ

Analog reference pin AD

V

ADref

R

L(ADref

reference voltage pin 18 0.45V

) reference output load pin 18 3.0 −− kΩ

ref

DDA

0.5V

DDA

0.55V

DDA

V

Analog audio pins

V
R
R

ref

O
CONV

reference voltage pin 25 with respect to V

SSO

output resistance pin 25 − 3 − kΩ
current-to-voltage

0.45V

DDA

0.5V

DDA

0.55V

DDA

V

− 1.2 − kΩ

conversion resistor

I

O(max)

C

L

maximum output current (THD + N)/S < 0.1% − 35 − mA
output load capacitance note 4 −−50 pF

Notes

is the AC impedance of the external circuitry connected to the audio outputs of the application circuit.

1. R

L

2. All power supply pins (VDD and VSS) must be connected to the same external power supply unit.

3. No operational amplifier load resistor.

4. Load capacitance greater than 50 pF, an inductor of 22 µH connected in parallel with a resistor of 270 Ω must be
inserted between the load and the operational amplifier output.

1995 Nov 15 11

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC

TDA1548T

with headphone driver and DSP

AC CHARACTERISTICS (ANALOG)

All voltages referenced to ground (pins 2, 9 and 23); V

DDD=VDDA=VDDO

(note 1); common operational amplifier application; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

RES input resolution −− 18 bit
f

sAD

V

ADref

V

FS(rms)

AD sample frequency − fs/32 − kHz
input voltage range 0 − V
output voltage swing (RMS

value) (pins 3 and 27)

V

DC(os)

DC offset output voltage
w.r.t. reference voltage
level V

ref

TC

FS

full scale temperature
coefficient

SVRR supply voltage ripple

rejection V

DDA

and V

DDO

UNBAL unbalance between the 2

C25=10µF; f
V

= 100 mV (peak)

ripple

ripple

= 1 kHz;

maximum volume − 0.1 − dB
DAC voltage outputs
(pins 3 and 27)

α

ct

crosstalk between the 2
DAC voltage outputs
(pins 3 and 27)

one output digital silence the

other maximum volume

one output digital silence the

other maximum volume

R

=5kΩ

L

crosstalk between the 2
DAC voltage outputs
(pins 3 and 27) with R
connected to ground

(THD+N)/S total harmonic distortion

one output digital silence the

other maximum volume

L

one output digital silence the

other maximum volume

R

=5kΩ

L

0 dB signal −−65 −60 dB
plus noise as a function of
signal

0 dB signal; R

−60 dB signal; R

=5kΩ− −85 −78 dB

L

=32Ω or

L

RL=5kΩ

S/N signal-to-noise ratio at

A-weighted at code 00000H 90 95 − dBA
bipolar zero

=3V; fi= 1 kHz; T

=25°C, RL=32Ω

amb

ADref

V

0.57 0.64 0.71 V

− 20 − mV

−±100 × 10−6−

− 40 − dB

− 50 − dB

− 90 − dB

− 70 − dB

− 100 − dB

− 0.056 0.1 %

− 0.006 0.013 %

−−35 −30 dBA

− 1.778 3.162 %

Note

1. RL is the AC impedance of the external circuitry connected to the audio outputs of the application circuit.

1995 Nov 15 12

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC

TDA1548T

with headphone driver and DSP

AC CHARACTERISTICS (DIGITAL)

All voltages referenced to ground (pins 2, 9 and 23); V

DDD=VDDA=VDDO

(note 1); unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

T

cy

t

CW(L)

t

CW(H)

clock cycle f

f

LOW level pulse width 22 −−ns

sys

f

HIGH level pulse width 22 −−ns

sys

f
f

sys
sys
sys

= 384f
= 256f
= 64f

s
s

s

Serial input data timing (see Fig.3)

f
f

sys
sys
sys

= 384f
= 256f
= 64f

s
s

s

BR clock input = data input rate f

f

sys

f

WS

t

r

t

f

t

BCK(H)

t

BCK(L)

t

s;DAT

t

h;DAT

t

s;WS

t

h;WS

system clock frequency 2.048 − 18.432 MHz
word select input frequency − 44.1 48.0 kHz
rise time −−20 ns
fall time −−20 ns
bit clock HIGH time 55 −−ns
bit clock LOW time 55 −−ns
data set-up time 20 −−ns
data hold time 10 −−ns
word select set-up time 20 −−ns
word select hold time 10 −−ns

= 2.7 to 4.0 V; T

= +70 °C, RL=32Ω

amb

54.2 59.1 81.3 ns

81.3 88.6 122 ns

325.5 354.3 488.3 ns

− 48f

− 64f

− 64f

s
s
s

−

−

−

handbook, full pagewidth

WS

t

BCK(H)

BCK

t

r

DATA LSB MSB

RIGHT

t

t

BCK(L)

t

r

T

cy

h;WS

Fig.3 Timing of input signals.

1995 Nov 15 13

t

s;WS

SAMPLE OUT

t

s;DAT

LEFT

t

h;DAT

MGC670

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC
with headphone driver and DSP

16 15 2 1

RIGHT

RIGHT

TDA1548T

MGC671

16 1518 17 2 1

B3 B4MSB B2 B17 LSB

16 1518 1720 19 2 1

RIGHT

> = 8

RIGHT

3

21> = 812 3

LEFT

S

2

INPUT FORMAT I

MSB MSBB2

15 2 1

16

LEFT

B15 LSB MSB B2 B15 LSB

LSB JUSTIFIED FORMAT 16 BITS

1518 17 2 1

16

MSB B2

LEFT

B3 B4

MSB B2 B17 LSB

LSB JUSTIFIED FORMAT 18 BITS

1518 1720 19 2 1

16

LEFT

LSB JUSTIFIED FORMAT 20 BITS

B5 B6

B3 B4MSB B2 B19 LSB B5 B6B3 B4MSB B2 B19 LSB

handbook, full pagewidth

Fig.4 Data input formats.

MSB B2

BCK

DATA

WS

BCK

DATA

WS

1995 Nov 15 14

WS

BCK

DATA

WS

BCK

DATA

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC
with headphone driver and DSP

TEST AND APPLICATION INFORMATION
Filter characteristics

Table 5 Digital filter characteristics (f

The band frequencies scale with the sample frequency.

BAND ATTENUATION

0to20kHz <0.001 dB
24 to 64 kHz > 39 dB
64 to 69 kHz > 33 dB
69 to 88 kHz > 37 dB

SYSTEM

CLOCK

INPUT

+3 V

10 kΩ

SYSCLK

BCK

WS

DATA

MODE0
MODE1

IF1

IF2
DEEM
MUTE

CLSEL

AD3S

handbook, full pagewidth

2

S-BUS OR

I

LSB-JUSTIFIED

SERIAL INPUT DATA

+3 V

FLAT
MID

MAX

= 44.1 kHz)

s

100 µF

100 nF

V

11

12

7
8
9

5
6
13
14
15
16
17

22

AD

L3

SSDVDDD

10

ref

100 nF 100 nF

(1)
(2)

V

V

SSA

DDA

24

23

TDA1548T

100 µF

V

SSO

TDA1548T

V

DDO

281

V

ref

25

100 nF

FILTCR

26

VOR

27

V

COM

2

VOL

3

4

FILTCL

21201918

ADVCADBBADTR

4.7 µF

47 µF

100 Ω

(1)

R2

330 Ω

1

nF

1

nF

(1)

L2

22 µH

(1)

L1

22 µH

(1)

R1

330 Ω

100 Ω

47 µF

RIGHT

LEFT

1

(1)

kΩ

C

5

5

kΩ

kΩ

1

kΩ

2

6

kΩ

kΩ

(1) Optional.
(2) Chip inductor BLM32A07.

Fig.5 Application diagram.

1995 Nov 15 15

10
kΩ

1

kΩ

MGB709

(1)

C

(1)

C

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC
with headphone driver and DSP

PACKAGE OUTLINES

SO28: plastic small outline package; 28 leads; body width 7.5 mm

D

c

y

Z

28

15

TDA1548T

SOT136-1

E

H

E

A

X

v M

A

pin 1 index

1

e

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

A

max.

2.65

0.10

A

0.30

0.10

0.012

0.004

1

A2A3b

2.45

0.25

2.25

0.096

0.01

0.089

0.49

0.36

0.019

0.014

p

0.32

0.23

0.013

0.009

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

cD

18.1

7.6

17.7

7.4

0.71

0.30

0.69

0.29

14

w M

b

p

scale

eHELLpQ

1.27

0.050

10.65

10.00

0.419

0.394

1.4

0.055

Q

A

2

A

1

1.1

0.4

0.043

0.016

1.1

1.0

0.043

0.039

detail X

0.25

0.01

L

p

L

0.25 0.1

0.01

(A )

A

3

θ

ywv θ

Z

0.9

0.4

0.035

0.004

0.016

o

8

o

0

OUTLINE
VERSION

SOT136-1

IEC JEDEC EIAJ

075E06 MS-013AE

REFERENCES

1995 Nov 15 16

EUROPEAN

PROJECTION

ISSUE DATE

95-01-24
97-05-22

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC
with headphone driver and DSP

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

D

c

y

Z

28 15

TDA1548T

SOT341-1

E

H

E

A

X

v M

A

pin 1 index

114

w M

b

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.0

1

0.21

0.05

A2A3b

1.80

0.25

1.65

0.38

0.25

p

cD

0.20

0.09

UNIT A

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

p

0 2.5 5 mm

scale

(1)E(1) (1)

10.4

10.0

eHELLpQZywv θ

5.4

0.65 1.25

5.2

7.9

7.6

Q

A

2

A

1

detail X

1.03

0.9

0.63

0.7

(A )

L

p

L

0.13 0.10.2

A

3

θ

1.1

0.7

o

8

o

0

OUTLINE
VERSION

SOT341-1 MO-150AH

IEC JEDEC EIAJ

REFERENCES

1995 Nov 15 17

EUROPEAN

PROJECTION

ISSUE DATE

93-09-08
95-02-04

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC
with headphone driver and DSP

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“IC Package Databook”

our

Reflow soldering

Reflow soldering techniques are suitable for all SO and
SSOP packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

(order code 9398 652 90011).

TDA1548T

SSOP
Wave soldering is not recommended for SSOP packages.

This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The longitudinal axis of the package footprint must

be parallel to the solder flow and must incorporate
solder thieves at the downstream end.

Even with these conditions, only consider wave
soldering SSOP packages that have a body width of

4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).

METHOD (SO AND SSOP)
During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.
SO
Wave soldering techniques can be used for all SO

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be

parallel to the solder flow.

• The package footprint must incorporate solder thieves at

the downstream end.

1995 Nov 15 18

Repairing soldered joints

Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron

(less than 24 V) applied to the flat part of the lead. Contact

time must be limited to 10 seconds at up to 300 °C. When

using a dedicated tool, all other leads can be soldered in

one operation within 2 to 5 seconds between

270 and 320 °C.

Philips Semiconductors Product specification

Bitstream continuous calibration filter-DAC

TDA1548T

with headphone driver and DSP

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1995 Nov 15 19

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]

Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,

Tel. [phone], Fax. [phone]

Brazil: Rua do Rocio 220 - 5

CEP: 04552-903-SÃO PAULO-SP, Brazil.
P.O. Box 7383 (01064-970),
Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

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72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
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77621 BOGOTA, Tel. [phone],
Fax. [phone]

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COPENHAGEN S, Tel. [phone], Fax. [phone]

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92156 SURESNES Cedex,
Tel. [phone], Fax. [phone]

Germany: P.O. Box 10 63 23, 20043 HAMBURG,

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Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. [phone] 911, Fax. [phone]

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Dr. Annie Besant Rd. Worli, Bombay 400 018
Tel. [phone], Fax. [phone]

Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,

P.O. Box 4252, JAKARTA 12950,
Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

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Piazza IV Novembre 3, 20124 MILANO,
Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37 , Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905,

Tel. [phone], Fax. [phone]

th

floor, Suite 51,

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,

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Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. [phone],
Fax. [phone]

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Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,

International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD45 © Philips Electronics N.V. 1995

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
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other industrial or intellectual property rights.

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