Datasheet TDA10021HT Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA10021HT

DVB-C channel receiver

Product specification
Supersedes data of 2000 Jun 21
File under Integrated Circuits, IC02

2001 Oct 01

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

FEATURES

• 4, 16, 32, 64, 128 and 256 Quadrature Amplitude
Modulation (QAM) demodulator (DVB-C compatible:
ETS 300-429/ITU-T J83 annex A/C)

• High performance for 256 QAM, especially for direct
IF applications

• On-chip 10-bit Analog-to-Digital Converter (ADC)

• On-chip Phase-LockedLoop (PLL) for crystal frequency

multiplication (typically 4 MHz crystal)

• Digital downconversion

• Programmable half Nyquist filter (roll off = 0.15 or 0.13)

• Two Pulse Width Modulated (PWM) AGC outputs with

programmable take over point (for tuner and
downconverter control)

• Clock timing recovery, with programmable 2nd-order
loop filter

• Variable symbol rate capability from SACLK/64 to
SACLK/4 (SACLK = 36 MHz maximum)

• Programmable anti-aliasing filters

• Full digital carrier recovery loop

• Carrier acquisition range up to 18% of symbol rate

• Integrated adaptive equalizer (linear transversal

equalizer or decision feedback equalizer)

• On-chip Forward Error Correction (FEC) decoder
(de-interleaver and RS decoder) and fully DVB-C
compliant

• DVB compatible differential decoding and mapping

• Parallel and serial transport stream interface

simultaneously

• I2C-bus interface, for easy control

• CMOS 0.2 µm technology.

GENERAL DESCRIPTION

The TDA10021HT is a single-chip DVB-C channel
receiver for 4, 16, 32, 64, 128 and 256 QAM modulated
signals. The device interfaces directly to the IF signal,
which is sampled by a 10-bit ADC.

The TDA10021HT performs the clock and the carrier
recovery functions. The digital loop filters for both clock
and carrier recovery are programmable in order to
optimize their characteristics according to the current
application.

After baseband conversion, equalization filters are used
for echo cancellation in cable applications. These filters
are configured as either a T-spaced transversal equalizer
or a Decision Feedback Equalizer (DFE), so that the
system performance can be optimized according to the
network characteristics. A proprietary equalization
algorithm, independent of carrier offset, is achieved in
order to assist carrier recovery. A decision directed
algorithm then takes place, to achieve final equalization
convergence.

The TDA10021HT implements a FORNEY convolutional
de-interleaver of depth 12 blocks and a Reed-Solomon
decoder which corrects up to 8 erroneous bytes. The
de-interleaver and the RS decoder are automatically
synchronized by the frame synchronization algorithm
which uses the MPEG-2 sync byte. Finally descrambling
according to DVB-C standard, is achieved at the Reed
Solomon output. This device is controlled via an I2C-bus.

APPLICATIONS

• Cable set-top boxes

• Cable modems

• MMDS (ETS 300-749) set-top boxes.

ORDERING INFORMATION

TYPE

NUMBER

TDA10021HT TQFP64 plastic thin quad flat package; 64 leads; body 10 × 10 × 1.0 mm SOT357-1

2001 Oct 01 2

NAME DESCRIPTION VERSION

Designed in 0.2 µm CMOS technology and housed in a
64 pin TQFP package, the TDA10021HT operates over
the commercial temperature range.

PACKAGE

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2001 Oct 01 3

handbook, full pagewidth

BLOCK DIAGRAM

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

SACLK

GPIO

CTRL

ENSERI

TEST
CLR#

V
V

IICDIV

SDA

SCL

V

CCD(PLL) PLLGND

DGND

XIN XOUT

2 3 62 61 64 63 1, 24,

PLL

5

10

IF

ADC

29

32

21
6
16
58

IP

57

IM

10

18
17

GPIO

BASEBAND

CONVERSION

V

CCA (PLL)

DECIMATION

FILTERS

V

SSD18

V

DDD18

4 4 3 3 2 2

4, 8,

7, 41

25, 42

CLOCK

RECOVERY

TIMING

INTERPOLATOR

TDA10021HT

I

INTERFACE

V

SSD33

V

DDD33

14, 30,4315, 31,4450 49 52 51 55, 60 56, 59 13

HALF

NYQUIST

RS

DECODER

2

C-BUS

V

DDD1

V

SSD1

AGC

EQUALIZER

DE-SCRAMBLERDE-INTERLEAVER

V

DDA2

V

SSA2

PWM

PWM

CARRIER

RECOVERY

V

DDA3

OUTPUT

INTERFACE

JTAG

V

SSA3

DECISION

DIFFERENTIAL

DECODER

V

DDD50

8

37 to 40,
45 to 48

9

AGCTUN

11

AGCIF

]

DO[7:0

36

DEN

35

OCLK

34

PSYNC

33

UNCOR

28

TDO

27

TMS

22

TCK

23

TDI

26

TRST

21

ENSERI

19

SDAT

20

SCLT

programmable

interface

serial

interface

V

ref(neg)

54

V

ref(pos)

53

12

MGW343

SADDR

Fig.1 Block diagram.

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

PINNING

SYMBOL PIN TYPE

V

DDD18

1 S digital supply voltage for the core (1.8 V typ.)

(1)

DESCRIPTION

XIN 2 I XTAL oscillator input pin: a fundamental XTAL oscillator is connected between the

XIN and XOUT pins. The XTAL frequency must be chosen so that the system
frequency SYSCLK (XIN × multiplying factor of the PLL) equals 1.6 times the tuner
output intermediate frequency; i.e. SYSCLK = 1.6 × IF.

XOUT 3 O XTAL oscillator output pin: a fundamental XTAL oscillator is connected between the

XIN and XOUT pins

V

SSD18

4 G digital ground for the core

SACLK 5 O sampling clock: this output clock can be fed to an external 10-bit ADC as the

sampling clock; SACLK = SYSCLK/2
TEST 6 I test input pin: in normal mode, pin TEST must be connected to ground
V

DDD18

V

SSD18

7 S digital supply voltage for the core (1.8 V typ.)
8 G digital ground for the core

AGCTUN 9 O/OD first PWM encoded output signal for AGC tuner: this signal is fed to the AGC

amplifier through a single RC network. The maximum signal frequency on the

VAGC output is XIN/16. AGC information is refreshed every 1024 symbols.
IICDIV 10 I IICDIV: this pin allows the frequency of the I2C-bus internal system clock to be

selected, depending on the crystal frequency. The internal I2C-bus clock is a

division of XIN by 4

IICDIV

.

AGCIF 11 O/OD second PWM encoded output signal for the AGC IF: This signal is fed to the AGC

amplifier through a single RC network. The maximum signal frequency on the

VAGC output is XIN/16. AGC information is refreshed every 1024 symbols.

However AGCIF can also be configured to output a PWM signal, the valueof which

can be programmed through the I
SADDR 12 I SADDR is the LSB of the I

2

2

C-bus interface.

C-bus address of the TDA10021HT. The MSBs are
internally set to 000110. Therefore the complete I2C-bus address of the
TDA10021HT is (MSB to LSB) 0, 0, 0, 1, 1, 0 and SADDR.

V

DDD50

V

DDD33

V

SSD33

13 S digital supply voltage for the pad 5.0 V (necessary for 5 V tolerant inputs)
14 S digital supply voltage for the pads (3.3 V typ.)
15 G digital ground for the pads

CLR# 16 I the CLR# input is asynchronous and active LOW, and clears the TDA10021HT:

When CLR# goes LOW, the circuit immediately enters its reset mode and normal
operation will resume 4 XIN falling edges after CLR# returns HIGH. The I

2

C-bus
register contents are all initialized to their default values. The minimum width of
CLR# at LOW level is 4 XIN clock periods.

SCL 17 I I

2

C-bus clock input: SCL should nominally be a square wave with a maximum

frequency of 400 kHz. SCL is generated by the system I2C-bus master.

SDA 18 I/OD SDA isa bidirectional signal:it is theserial input/output of the I

A pull-upresistor (typically 4.7 kΩ)must be connectedbetween SDAand V

2

C-bus internalblock.

DDD50

for

proper operation (open-drain output).

2

SDAT 19 I/OD SDAT is equivalent to SDA I/O of the TDA10021HT but can be 3-stated by I

C-bus
programming. It is actually the output of a switch controlled byparameter BYPIIC of
register TEST (index 0F). SDAT is an open-drain output and therefore requires an
external pull-up resistor.

2001 Oct 01 4

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

SYMBOL PIN TYPE

(1)

DESCRIPTION

SCLT 20 OD SCLT can be configured to be a control line output or to output the SCL input. This

is controlled by parameter BYPIIC and CTRL_SCLT of register TEST (index 0F).
SCLT is an open-drain output and therefore requires an external pull-up resistor.

ENSERI 21 I when HIGH this pin enables the serial output transport stream through the

boundary scan pins TRST, TDO, TCK, TDI and TMS (serial interface). Must be set
LOW in bist and boundary scan mode.

TCK 22 I/O test clock: an independent clock used to drive the TAP controller in boundary scan

mode. In normal mode of operation, TCK must be set LOW. In serial stream mode,
TCK is the clock output (OCLK).

TDI 23 I/O test data input: the serial input for test data and instruction in boundary scan mode.

In normal mode of operation, TDI must be set LOW. In serial stream mode, the TDI
is the PSYNC output.

V

DDDI8

V

SSDI8

24 S digital supply voltage for the core (1.8 V typ.)
25 G digital ground for the core

TRST 26 I/O test reset: this active LOW input signal is used to reset the TAP controller in

boundary scan mode. In normal mode of operation, TRST must be set LOW. In
serial stream mode, TRST is the uncorrectable output (UNCOR).

TMS 27 I/O test mode select: this input signal provides the logic levels needed to change the

TAP controller from state to state. In normal mode of operation,TMS must be set to
HIGH. In serial stream mode, TMS is the DEN output.

TDO 28 O test data output: this is the serial test output pin used in boundary scan mode.

Serial data is provided on the falling edge of TCK. In serial stream mode, TDO is
the data output (DO).

GPIO 29 OD GPIO can be configured by the I

2

C-bus either as:

• A Front-End Lock indicator (FEL) (default mode)

2

• An active LOW output interrupt line (IT) which can be configured by the I

C-bus

interface

• A control output pin programmable by I2C-bus.
GPIO is an open-drain output and therefore requires an external pull-up resistor.

V

DDD33

V

SSD33

CTRL 32 OD CTRL is a control output pin programmable by the I

30 S digital supply voltage for the pads (3.3 V typ.)
31 G digital ground for the pads

2

C-bus. CTRL is an open-drain

output and therefore requires an external pull-up resistor.

UNCOR 33 O uncorrectable packet: this output signal is HIGH when the provided packet is

uncorrectable (during the 188 bytes of the packet). The uncorrectable packet is not
affected by the Reed Solomon decoder, but the MSB of the byte following the sync
byte is forced to logic 1 for the MPEG-2 process: error flag indicator (if RSI and IEI
are set LOW in the I

2

C-bus table).

PSYNC 34 O pulse synchro: thisoutput signal goes HIGH when the sync byte (0x47) is provided,

then it goes LOW until the next sync byte

OCLK 35 O output clock: thisis the output clock for the DO[7:0] data outputs. OCLK is internally

generated depending on which interface is selected.

DEN 36 O data enable: this output signal is HIGH when there is valid data on the output bus

DO[7:0]

2001 Oct 01 5

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

SYMBOL PIN TYPE

(1)

DESCRIPTION

DO[7:4] 37 to 40 O data output bus: this 8-bit parallel data is the output from the TDA10021HT after

demodulation, de-interleaving, RS decoding and de-scrambling. When one of the
two possible parallel interfaces is selected (parameter SERINT = 0, index 20) then
DO[7:0] is the transport stream output. When the serial interface is selected
(parameter SERINT = 1, index 20) then the serial output is on pin DO[0].

V

DDDI8

V

SSD18

V

DDD33

V

SSD33

41 S digital supply voltage for the core (1.8 V typ.)
42 G digital ground for the core
43 S digital supply voltage for the pads (3.3 V typ.)
44 G digital ground for the pads

DO[3:0] 45 to 48 O data output bus: this 8-bit parallel data is the output from the TDA10021HT after

demodulation, de-interleaving, RS decoding and de-scrambling. When one of the
two possible parallel interfaces is selected then DO[7:0] is the transport stream
output. When the serial interface is selected then the serial output is on pin DO[0].

V

SSD1

V

DDD1

V

SSA2

V

DDA2

V

ref(pos)

49 G ground return for the digital switching circuitry (ADC)
50 S power supply input for the digital switching circuitry 1.8 V (ADC)
51 G ground return for the analog clock drivers (ADC)
52 S power supply input for the analog clock drivers 3.3 V (ADC)
53 O this is a positive voltage reference for the ADC. It is derived from the internal band

gap voltage, VBG, with an on-chip fully differential amplifier.

V

ref(neg)

54 O this is the negative voltage reference for the ADC. It is derived from the internal

band gap voltage, VBG, with an on-chip fully differential amplifier.

V
V
V

DDA3
SSA3
IM

55 S power supply input for the analog circuits 3.3 V (ADC)
56 G ground return for analog circuits (ADC)
57 I negative input to the ADC: this pin is DC biased to half-supply through an internal

resistor divider (2 × 20 kΩ resistors). In order to stay in the range of the ADC,
VIP− VIM should remain between the input range corresponding to the SW
register (index 1B − default value = 0.5 V).

V

IP

58 I positive input to the ADC: this pin is DC biased to half-supply through an internal

resistor divider (2 × 20 kΩ resistors). In order to stay in the range of the ADC,
VIP− VIM should remain between the input range corresponding to the SW
register (index 1B − default value = 0.5 V).

V

SSA3

V

DDA3

V

CCD(PLL)

59 G ground return for analog circuits (ADC)
60 S power supply input for the analog circuits 3.3 V (ADC)

61 S power supply for the PLL digital section 1.8 V
DGND 62 G ground connection for the PLL digital section
PLLGND 63 G ground connection for the PLL analog section
V

CCA(PLL)

64 S power supply for the PLL analog section 3.3 V

Note

1. All inputs (I) are TTL, 5 V tolerant (except pins XIN, VIP and VIM). OD are open-drain outputs, so they must be
connected by a pull-up resistor to either V

DDD33

or V

DDD50

.

2001 Oct 01 6

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

handbook, full pagewidth

IM

CCA(PLL)

PLLGND

V
64

63

DGND

62

CCD(PLL)

DDA3

V

V

61

60

SSA3

V
59

SSA3

IP

V

V
58

57

DDA3

V
56

ref(neg)

V

V

55

54

ref(pos)

V

53

DDA2

SSA2VDDD1VSSD1

V

V

52

51

50

49

V

DDD18

XIN

XOUT

V

SSD18

SACLK

TEST

V

DDD18

V

SSD18

AGCTUN

IICDIV
AGCIF

SADDR

V

DDD50

V

DDD33

V

SSD33

CLR#

10
11
12
13
14
15
16

1
2
3
4
5
6
7
8

48
47
46
45
44
43
42
41

TDA10021HT

9

40
39
38
37
36
35
34
33

]

DO[0

]

DO[1

]

DO[2

]

DO[3
V

SSD33

V

DDD33

V

SSD18

V

DDD18

]

DO[4

]

DO[5

]

DO[6

]

DO[7
DEN
OCLK
PSYNC
UNCOR

17

SCL

18

SDA

19

SDAT

20

SCLT

22

TCK

ENSERI

23

TDI

24

V

21

Fig.1 Pin configuration.

2001 Oct 01 7

25

DDD18

V

26

TRST

SSD18

27

TMS

28

TDO

29

GPIO

30

DDD33

V

31

SSD33

V

32

MGW344

CTRL

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDD33

V

DDD18

V

DDD50

V

IH

V

IL

V

OH

V

OL

I

DDD33

I

DDD18

P

tot

C

i

T

amb

XTAL; pin XIN

V

IH

V

IL

PLL

V

DDD(PLL)

V

DDA(PLL)

ADC

V

DDA1

V

DDA2,VDDA3

VIP,V

IM

V

i

V

ref(pos)

V

ref(neg)

V

offset

R

i

C

i

B input full power bandwidth 3 dB bandwidth 40 50 − MHz

digital supply voltage for the

V

= 3.3 V ±10% 2.97 3.3 3.63 V

DDD

pads
digital supply voltage for the

V

= 1.8 V ±5% 1.7 1.8 1.9 V

DDD

core
digital supply voltage only for 5 V

4.75 5.0 5.25 V

requirements; note 1

HIGH-level input voltage TTL input; note 2 2 − V

DDD50

V
LOW-level input voltage TTL input 0 − 0.8 V
HIGH-level output voltage note 3 2.4 −− V
LOW-level output voltage −−0.4 V
digital supply current for the

pads
digital supply current for the

core
total power dissipation fs= 28.92 MHz;

fs= 28.92 MHz;
symbol rate = 7 Mbaud

fs= 28.92 MHz;
symbol rate = 7 Mbaud

− 46 − mA

− 120 − mA

− 540 − mW

symbol rate = 7 Mbaud
input capacitance −−5pF
ambient temperature 0 − 70 °C

HIGH-level input voltage 0.7V

DDD33

LOW-level input voltage 0 − 0.3V

digital PLL supply voltage V
analog PLL supply voltage V

analog ADC supply voltage V
analog ADC supply voltage V

= 1.8 V ±5% 1.7 1.8 1.9 V

DDD

= 3.3 V ±10% 2.97 3.3 3.63 V

DDA

= 1.8 V ±5% 1.7 1.8 1.9 V

DDA

= 3.3 V ±10% 2.97 3.3 3.63 V

DDA

analog ADC inputs −0.5 − V
signal input range IR=VIP− V

IM

−0.5 to −1.0 − +0.5 to +1.0 V

− V

DDD33

DDD33

DDA3

V
V

+ 0.5 V

positive reference voltage 1.95 2.15 2.35 V
negative reference voltage 0.95 1.15 1.35 V
input offset voltage −25 − +25 mV
input resistance (VIPor VIM) − 10 − kΩ
input capacitance (VIPor VIM) − 510 pF

Notes

1. The voltagelevel of the 5 V supplymust always exceed or at least equal the voltage level of the 3.3 V supplyduring
power-up and power-down in order to guarantee protection against latch-up.

2. All digital inputs are 5 V tolerant except pin XIN.

3. IOH,IOL= ±4 mA for pins SACLK, SCL, SDA, SDAT, SCLT, TCK, TDI, TRST, TMS, TDO, GPIO, UNCOR, PSYNC,
OCLK, DEN and DO[7:0]. For all other pins, IOH, IOL= ±2 mA.

2001 Oct 01 8

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

APPLICATION INFORMATION

handbook, full pagewidth

RF
input

(1) Output 1 can be either a parallel output mode A, a parallel output mode B or a serial output (programmable interface).
(2) Output 2 is a serial output (serial interface).

TUNER

AGC1

CIRCUITRY

IF

2

I

C-bus tuner

ANALOG

CIRCUITRY

AGC2

CIRCUITRY

V
V

SCLT, SDAT

AGCIF AGCTUN XIN XOUT

OUTPUT1

IP
IM

TDA10021HT

2

I

C-BUS

OUTPUT2

(1)

(2)

SCL, SDA

]

DO[7:0
DEN
OCLK
PSYNC
UNCOR

TDO (DO)
TMS (DEN)
TCK (OCLK)
TDI (PSYNC)
TRST (UNCOR)

MGW346

Fig.2 Front-end receiver schematic.

2001 Oct 01 9

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

R

XTAL

C1

TDA10021HT

XOUTXIN

C2

MGW347

handbook, halfpage

23

(1) Typical XTAL is at fundamental frequency (typically 4 Mhz).
(2) Values of passive components are dependant on XTAL manufacturer (typically R = 1 MΩ, C1 = C2 = 56pF).

Fig.3 Typical XTAL connection.

handbook, halfpage

TDA10021HT

R

AGCTUN/
AGCIF

R and C are chosen to verify < fc< with R = 1.5 kΩ and C = 1 nF, fc= 100 kHz.

SR

------------­1024

XIN

--------- ­16

9
11

Fig.4 External AGC connection.

2001 Oct 01 10

GND

to TUNER/IF

C

MGW348

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

handbook, full pagewidth

TDA10021HT

V

CCA(PLL)

PLLGND

DGND

V

CCD(PLL)

V

DDA3

V

SSA3

V

ref(pos)

V

ref(neg)

V

DDA2

V

SSA2

V

DDD1

V

SSD1

10
µF

10
µF

10
µF

10
µF

10
µF

1 Ω

1 Ω

1 Ω

VINP

VINM

1 Ω

1 Ω

MGW349

+

+

+

+

+

3.3 V

1.8 V

3.3 V

3.3 V

1.8 V

64

10
nF

63

62

61

10
nF

60

10
nF

59

100

nF

100

nF

10
nF

10
nF

0.1 µF

0.1 µF

58

V

IP

57

V

IM

53

54

52

51

50

49

Fig.5 PLL and ADC connections.

2001 Oct 01 11

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

PACKAGE OUTLINE

TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm

c

y

X

A

48 33

49

Z

32

E

SOT357-1

e

w M

pin 1 index

64

1

e

DIMENSIONS (mm are the original dimensions)

mm

A

A1A2A3bpcE

max.

0.15

0.05

1.05

0.95

0.25

1.2

UNIT

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

w M

b

p

D

H

D

0.27

0.17

16

Z

D

(1) (1)(1)

D

0.18

10.1

0.12

9.9

b

p

17

v M

B

v M

B

0 2.5 5 mm

scale

(1)

eH

H

D

10.1

9.9

0.5

12.15

11.85

E

A

12.15

11.85

H

E

E

A

2

A

A

LL

1

p

0.75

0.45

0.08 0.11.0 0.2

detail X

Z

1.45

1.05

D

(A )

3

L

p

L

Zywv θ

E

1.45

1.05

o

7

o

0

θ

OUTLINE
VERSION

SOT357-1 137E10 MS-026

IEC JEDEC EIAJ

REFERENCES

2001 Oct 01 12

EUROPEAN

PROJECTION

ISSUE DATE

99-12-27
00-01-19

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

SOLDERING
Introduction to soldering surface mount packages

Thistext givesavery briefinsight to acomplex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for
certainsurface mountICs,but itisnot suitableforfine pitch
SMDs. In these situations reflow soldering is
recommended.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuitboard byscreen printing, stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.

Wave soldering

Conventional single wave soldering is not recommended
forsurface mountdevices(SMDs) orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

• Use a double-wave soldering method comprising a
turbulent wavewith high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackages withleadson foursides,the footprintmust
be placedat a 45° angleto the transport directionof the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and beforesoldering, thepackage must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

If wave soldering isused the following conditions must be
observed for optimal results:

2001 Oct 01 13

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable

SOLDERING METHOD

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packagesare not suitable for wave solderingas a solder joint betweenthe printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering isonly suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to orlarger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wavesoldering is onlysuitable for SSOPand TSSOP packageswith a pitch (e) equalto or largerthan 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DATA SHEET STATUS

PRODUCT

DATA SHEET STATUS

(1)

STATUS

(2)

DEFINITIONS

Objective specification Development This data sheet contains data from the objective specification for product

development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Preliminary specification Qualification This data sheet contains data from the preliminary specification.

Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

Product specification Production This data sheet contains data from the product specification. Philips

Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

2001 Oct 01 14

Philips Semiconductors Product specification

DVB-C channel receiver TDA10021HT

DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting valuesdefinition Limiting values givenare in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
atthese orat any otherconditions abovethosegiven inthe
Characteristics sectionsof the specification isnot implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentation orwarranty thatsuch applications willbe
suitable for the specified use without further testing or
modification.

DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result inpersonal injury.Philips
Semiconductorscustomers usingor sellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuse ofanyof theseproducts,conveys nolicenceor title
under any patent, copyright, or mask work right to these
products,and makesno representationsorwarranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

ICs with MPEG-2 functionality  Use of this product in
any manner that complies with the MPEG-2 Standard is
expressly prohibited without a license under applicable
patents in the MPEG-2 patent portfolio, which license is
available from MPEG LA, L.L.C., 250 Steele Street, Suite
300, Denver, Colorado 80206.

PURCHASE OF PHILIPS I

Purchase of Philips I
components inthe I2C systemprovided the systemconforms to the I2C specificationdefined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

2001 Oct 01 15

Philips Semiconductors – a w orldwide compan y

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: [phone]
For sales offices addresses send e-mail to: [e-mail].

© Koninklijke Philips Electronics N.V. 2001
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in thisdocument does not form partof any quotation or contract,is believed to be accurateand reliable and may bechanged
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Printed in The Netherlands 753504/04/pp16 Date of release: 2001 Oct 01 Document order number: 9397 750 08497

SCA73