This series of POWER MOSFETS represents the
most advanced high voltage technology. The optimized cell layout coupled with a new proprietary
edge termination concur to give the device low
R
and gate charge, unequalled ruggedness
DS(on)
and superior switching performance.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SWITCH MODE POWERSUPPLIES (SMPS)
■ DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
3
2
1
TO-247
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symb o lParamet erVal u eUnit
V
V
V
I
DM
P
T
(•) Pulsewidth limited bysafe operating area
December 1995
Drain - s ource Voltage (VGS= 0)500V
DS
Drain- gate Voltage (RGS=20kΩ)500V
DGR
Gate-source Voltage± 30V
GS
Drain Current (continuous) at Tc=25oC11.6A
I
D
Drain Current (continuous) at Tc=100oC7.3A
I
D
(•)Drain Current (pulsed)46.4A
Total Di ssipation a t Tc=25oC170W
tot
Derat ing Factor1.36W/
St or a ge Tem perature-65 t o 150
stg
Max. Operating Jun ction T emperature150
T
j
o
C
o
C
o
C
1/9
Page 2
STW12NA50
THERMAL DATA
R
thj-case
R
thj-amb
R
thj-amb
T
AVALANCHE CHARACTERISTICS
SymbolParameterMax Valu eUni t
I
AR
E
E
I
AR
Thermal Resistance Junction - cas eMax
Thermal Resistance Junction- ambientMax
Thermal Resistance Case-sinkTyp
Maximum L ead Temperat ur e For Soldering Purpos e
l
Avalanc h e Cu rr ent , Repet itive or Not-Rep etitive
(pulse width limited by Tjmax, δ <1%)
Single Pul se Avalanche Ener gy
AS
(starti ng Tj=25oC, ID=IAR,VDD=50V)
Repetitive Avalanc he Energ y
AR
(pulse width limited by Tjmax, δ <1%)
Avalanc h e Cu rr ent , Repet itive or Not-Rep etitive
(Tc= 100oC, pulse width l imited by Tjmax, δ <1%)
0.73
30
0.1
300
11.6A
670mJ
26.5mJ
7.3A
o
C/W
o
C/W
o
C/W
o
C
ELECTRICAL CHARACTERISTICS (T
=25oC unless otherwisespecified)
case
OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
(BR)DSS
Drain - s ource
ID=250µAVGS= 0500V
Break d own Volta ge
I
DSS
I
GSS
Zer o G at e V oltage
Drain Current (V
GS
Gat e- body Leakage
=0)
=MaxRating
V
DS
V
= Max Rating x 0.8 Tc=125oC
DS
25
250
VGS= ± 30 V± 100nA
Current (VDS=0)
ON (∗)
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage VDS=VGSID=250µA2.2533.75V
St at ic Drain-s our ce O n
VGS=10V ID=6A0.50.6Ω
Resistance
I
D(on)
On State Drain Current VDS>I
D(on)xRDS(on)max
12A
VGS=10V
DYNAMIC
SymbolParameterTest ConditionsMin.Typ.Max.Unit
(∗)Forward
g
fs
Tr ansconductance
C
C
C
Input Capacitance
iss
Out put Capacitance
oss
Reverse Transfer
rss
Capacitance
VDS>I
D(on)xRDS(on)maxID
=6A69S
VDS=25V f=1MHz VGS= 01750
250
80
2500
370
130
µA
µA
pF
pF
pF
2/9
Page 3
STW12NA50
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
d(on)
(di/dt)
Q
Q
Q
Turn-on T ime
t
Rise Time
r
Turn-on Current S lopeVDD=400V ID=12A
on
Total Gate Charge
g
Gat e- Source Charge
gs
Gate-Drain Charge
gd
SWITCHING OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
r(Voff)
t
Off -voltage Rise Time
t
Fall Time
f
Cross-over Time
c
SOURCE DRAINDIODE
VDD=250V ID=6A
RG=4.7 ΩVGS=10V
20
32
(see test circuit, figure 3)
190A/µs
RG=47 ΩVGS=10V
(see test circuit, figure 5)
VDD= 400 V ID=12A VGS=10V80
12
37
VDD=400V ID=12A
RG=4.7 Ω VGS=10V
(see test circuit, figure 5)
16
12
30
28
45
110nC
22
18
42
ns
ns
nC
nC
ns
ns
ns
SymbolParameterTest ConditionsMin.Typ.Max.Unit
I
I
SDM
SD
Source-drain C urrent
(•)
Source-drain C urrent
11.6
46.4
(pulsed)
V
(∗)Forward On VoltageISD=12A VGS=01.6V
SD
t
Reverse Recovery
rr
Time
Q
Reverse Recovery
rr
ISD= 12 Adi/dt = 100 A/µs
VDD= 100 VTj=150oC
(see test circuit, figure 5)
600
10.2
Charge
I
RRM
Reverse Recovery
34
Current
(∗) Pulsed:Pulse duration = 300 µs, dutycycle 1.5 %
(•) Pulse widthlimited by safeoperating area
Safe Operating AreasThermal Impedance
A
A
ns
µC
A
3/9
Page 4
STW12NA50
Derating Curve
Transfer Characteristics
Output Characteristics
Transconductance
Static Drain-source On Resistance
4/9
Gate Charge vs Gate-source Voltage
Page 5
STW12NA50
Capacitance VariationsNormalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs TemperatureTurn-on Current Slope
Cross-over TimeTurn-off Drain-source Voltage Slope
5/9
Page 6
STW12NA50
Switching SafeOperating AreaAccidental Overload Area
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge Test Circuit
7/9
Page 8
STW12NA50
TO-247 MECHANICAL DATA
DIM.
MIN.TYP.MAX.MIN.TYP.MAX.
A4.75.30.1850.208
A12.870.113
A21.52.50.0590.098
b11.40.0390.055
b12.250.088
b23.053.430.1200.135
C0.40.80.0150.031
D20.421.180.8030.833
e5.435.470.2130.215
E15.315.950.6020.628
L15.570.613
L13.74.30.1450.169
Q5.35.840.2080.230
ØP3.53.710.1370.146
mminch
8/9
C
A
b1
A1
b
e
b2
A2
Q
D
L1
L
ø
E
Page 9
STW12NA50
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rightsof third parties which mayresults fromits use. No
licenseis granted by implication or otherwise under any patentor patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in thispublication are subject to change withoutnotice. Thispublication supersedes andreplacesall information previously supplied.
SGS-THOMSONMicroelectronics products are not authorizedfor use ascriticalcomponents in lifesupport devices or systems withoutexpress
writtenapproval ofSGS-THOMSONMicroelectonics.
1996 SGS-THOMSON Microelectronics -Printed in Italy- AllRightsReserved
Australia- Brazil -Canada -China - France- Germany - HongKong- Italy - Japan- Korea- Malaysia - Malta- Morocco - The Netherlands -