Using the latest high voltage MESH OVERLAY
process, STMicroelectronics has designed an
advanced family ofpowerMOSFETs with
outstanding performances. Thenew patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest R
per area, exceptional avalanche
DS(on)
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
APPLICATIONS
■ SWITCHMODE POWER SUPPLIES (SMPS)
■ DC-AC CONVERTERS FOR WELDING
EQUIPMENTANDUNINTERRUPTIBLE
POWERSUPPLIESAND MOTOR DRIVE
■ HIGHCURRENT, HIGH SPEED SWITCHING
3
2
1
TO-247
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
DM
P
dv/dt(
T
(•) Pulsewidth limited by safe operating area(1)ISD≤10A, di/dt ≤ 200 A/µs, VDD≤ V
October 1998
Dra in- sour c e Voltage ( VGS= 0)600V
DS
Dra in- gate Vol t age (RGS=20kΩ)600V
DGR
Gat e-source Voltage
GS
I
Dra in Curr ent (c ont inuous) at Tc=25oC10A
D
I
Dra in Curr ent (c ont inuous) at Tc=100oC6.2A
D
30V
±
(•)Dra in Curr ent (p ulsed)40A
Tot al Dissipat ion at Tc=25oC160W
tot
Der ati ng Factor1.28W/
1) P eak Diode Recover y voltage slope4.5V/ns
St orage Tem pe rat ure-65 to 150
stg
T
Max. Oper at ing Junction Tem perature150
j
,Tj≤T
(BR)DSS
JMAX
o
C
o
C
o
C
1/8
Page 2
STW10NB60
THERMAL DATA
R
thj-case
Rthj-amb
R
thc-sink
T
AVALANCHE CHARACTERISTICS
SymbolParameterMax ValueUnit
I
AR
E
Ther mal Res istance J unction- cas eMax
Ther mal Res istance J unction- ambientMax
Ther mal Res istance C ase - sinkTy p
Maximum Lead T emperat ur e For S o lder ing Purpose
l
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
Single Pulse A valanche E ner gy
AS
(starting T
=25oC, ID=IAR,VDD=50V)
j
max,δ <1%)
j
0.78
30
0.1
300
10A
850mJ
o
C/W
oC/W
o
C/W
o
C
ELECTRICAL CHARACTERISTICS
=25oC unless otherwisespecified)
(T
case
OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
(BR)DSS
Drain-source
ID=250µAVGS= 0600V
Break dow n Volt age
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gat e- bod y Leakage
Current (V
DS
=0)
=0)
V
=MaxRating
DS
=MaxRatingTc=100oC
V
DS
V
=± 30 V
GS
1
50
100nA
±
ON(∗)
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage VDS=VGSID= 250 µA345V
Sta t ic Dr ain -s ource O n
VGS=10V ID=4 A0.690.8
Resistance
I
D(on)
On State Drain Current VDS>I
D(on)xRDS(on)max
10A
VGS=10V
DYNAMIC
SymbolParameterTest ConditionsMin.Typ.Max.Unit
g
(∗)Forward
fs
Tr ansc on duc tance
C
C
C
Input C apac i t ance
iss
Out put Capacitance
oss
Reverse T r ansfer
rss
Capacit a nc e
VDS>I
D(on)xRDS(on)maxID
=17A36.5S
VDS=25V f=1MHz VGS= 01480
210
25
1924
273
33
µ
µA
Ω
pF
pF
pF
A
2/8
Page 3
STW10NB60
ELECTRICAL CHARACTERISTICS
(continued)
SWITCHING ON
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
d(on)
t
r
Turn-on Time
Rise T i me
VDD=300V ID= 4.5 A
R
=4.7
G
Ω
VGS=10V
25
11
35
15
(see test circuit, figure 3)
Q
Q
Q
Tot al G at e Char ge
g
Gat e- Source Char g e
gs
Gate-Drain Charge
gd
VDD= 480 V ID=9 A VGS=10V
R
=4.7
G
Ω
VGS=10V
40
10.5
17.5
56nC
SWITCHING OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
r(Voff)
t
t
Off-voltage Rise T im e
Fall T ime
f
Cross-over Time
c
VDD=480V ID=9A
=4.7 Ω VGS=10V
R
G
(see test circuit, figure 5)
12
10
21
17
14
29
SOURCEDRAINDIODE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
(∗) Pulsed: Pulse duration = 300µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Source-drain Current
(•)
Source-drain Current
10
40
(pulsed)
(∗)ForwardOnVoltage ISD=10A VGS=01.6V
Reverse Re covery
rr
Time
Reverse Re covery
rr
ISD=9A di/dt=100A/µs
= 100 VTj=150oC
V
DD
(see test circuit, figure 5)
600
5.4
Charge
Reverse Re covery
18
Current
ns
ns
nC
nC
ns
ns
ns
A
A
ns
µ
A
C
SafeOperating AreaThermalImpedance
3/8
Page 4
STW10NB60
OutputCharacteristics
Transconductance
TransferCharacteristics
Static Drain-sourceOn Resistance
Gate Charge vs Gate-sourceVoltage
4/8
CapacitanceVariations
Page 5
STW10NB60
NormalizedGate ThresholdVoltage vs
Temperature
Source-drainDiode Forward Characteristics
NormalizedOn Resistancevs Temperature
5/8
Page 6
STW10NB60
Fig. 1:
UnclampedInductiveLoad TestCircuit
Fig. 3: Switching Times Test CircuitsFor
ResistiveLoad
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granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in thispublication are
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