Page 1
STV7697A
PLASMA DISPLAY PANEL SCAN DRIVER
FEATURES
■ 64 OUTPUTS PLASMA DISPLAY DRIVER
■ 170V ABSOLUTE MAXIMUM SUPPLY
■ 5V SUPPLY FOR LOGIC
■ 100/400 mA SOURCE / SINK OUTPUT
■ 700 mA SOURCE / SINK OUTPUT DIODE
■ 64-BIT SHIFT REGISTER (20 MHz)
■ BLANK CONTROL
■ COMPLEMENTARY OUTPUT CONTROL
■ BCD TECHNOLOGY
■ 100 PINS PQFP PACKAGE OR DICE.
DESCRIPTION
The STV7697A is a scan driver for Plasma
Display Panel (PDP) implemented in ST’s
proprietary BCD technology. Using a 64-bit
cascadable 20 MHz shift register, it drives 64 high
current & high voltage outputs. By serially
connecting several STV7697A, any vertical pixel
definition can be performed. The STV7697A is
supplied with a separated 160V power output
supply and a 5V logic supply.All command inputs
are CMOS compatible.
The STV769 7A package is a 100 pins PQFP.
.
PQFP100 (14 x 20 x 2.80 mm)
(Full Plastic Quad Flat Pack)
ORDER CODE: STV7697A
ORDER CODE: STV7697A/WAF (1)
(1): Unsawn Tested Wafer
Version 4.2
June 2000 1/15
This ispreliminary information on a new product indevelopment orundergoing evaluation. Details are subject tochange without notice.
1
Page 2
TABLE OF CONTENTS
PIN ASSIGNMENT . ............................................................ 4
BLOCK DIAGRAM . ............................................................ 7
CIRCUIT DESCRIPTION . . . . . . . . . ................................................ 7
Note 1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . ............................... 8
Note 1 THERMAL DATA . . . . . . . . . ................................................ 8
Note 5 ELECTRICAL CHARACTERISTICS .......................................... 9
Note 6 AC TIMINGS REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Note 6 AC TIMINGS CHARACTERISTICS . . . . . . . . . ................................. 10
Figure 2. INPUT/OUTPUT SCHEMATICS . . . . . . . . . . ................................. 13
Figure 6. PACKAGE MECHANICAL DATA . . . . . . . .................................. 14
2/15
2
2
Page 3
PIN CONNECTIONS
(Die pinout)
OUT36
OUT35
OUT38
OUT37
OUT40
OUT39
OUT42
OUT41
OUT43
OUT44
OUT46
OUT45
OUT48
OUT47
OUT50
OUT49
OUT52
OUT51
OUT53
OUT54
OUT56
OUT55
OUT58
OUT57
OUT60
OUT59
OUT62
OUT61
OUT64
OUT63
STV7697A
OUT34
OUT33
V
PP
V
SSP
V
SSP
V
SSP
V
PP
V
SSSUB
V
SSLOG
V
SSLOG
V
CC
V
SSLOG
V
SSSUB
V
PP
V
SSP
V
SSP
V
SSP
V
PP
OUT32
OUT31
PIN CONNECTIONS
(TQFP pinout)
OUT30
OUT29
OUT35
OUT28
OUT37
OUT36
OUT27
OUT26
OUT38
OUT25
OUT40
OUT39
STV7697A
Bare Die
(0,0)
x
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT47
OUT46
OUT45
OUT43
OUT42
OUT41
OUT44
OUT17
OUT16
OUT49
OUT48
OUT15
OUT14
OUT51
OUT50
y
OUT13
OUT12
OUT53
OUT52
OUT11
OUT10
OUT55
OUT54
OUT9
OUT57
OUT56
OUT8
OUT7
OUT59
OUT58
OUT6
OUT5
OUT61
OUT60
OUT4
OUT3
OUT63
OUT62
OUT2
OUT1
V
P
P
V
SSP
V
SSP
V
PP
V
SSLOG
CLK
STB
SOUT(SIN)
V
CC
SIN(SOUT)
F/R
BLK
POL
V
PP
V
SSP
V
SSP
V
PP
OUT34
OUT33
V
V
V
V
SSSUB
V
SSLOG
V
SSLOG
V
SSLOG
V
SSSUB
V
V
V
OUT32
OUT31
302928272625242322212019181716151413121110
31
32
33
V
PP
34
SSP
35
SSP
36
SSP
37
V
PP
38
39
40
V
CC
41
42
43
44
V
PP
45
SSP
46
SSP
47
SSP
V
48
PP
49
STV7697A
PQFP100
50
5152535455565758596061626364656667686970717273747576777879
OUT30
OUT29
OUT28
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
OUT15
OUT14
OUT13
987654321
OUT9
OUT11
OUT10
OUT8
OUT12
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80 OUT64
OUT1
V
PP
V
SSP
V
SSP
V
PP
NC
NC
V
SSLOG
CLK
STB
SOUT(SIN)
V
CC
SIN(SOUT)
NC
F/R
BLK
POL
V
PP
V
SSP
V
SSP
V
PP
3/15
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Page 4
STV7697A
PIN ASSIGNMENT
(TQFP100)
Pin Number Symbol Type Function
33-37-44-48-81-84-97-100 V
41 - 90 V
34-35-36-45-46-47-82-83-98-99 V
38-43 V
39-40-42-94 V
1 to 32, 49 to 80 OUT 64 to OUT 1 Output Power Output
91 SOUT (SIN) Output Shift Register Data Output (forward)
85 POL Input Polarity Selection
86 BLK Input Output Blanking Command
87 F/ Input Selection of shift direction
89 SIN (SOUT) Input Shift Register Data Input (forward)
92 Input Latch of data to outputs
93 CLK Input Clock of data shift register
88-95-96 NC -
PP
CC
SSP
SSSUB
SSLOG
R
STB
Supply High Voltage Supply of power outputs
Supply 5 V Logic Supply
Ground Ground of power outputs
Ground Substrate Ground
Ground Logic Ground
PIN ASSIGNMENT (Power Outputs)
Output N° Pin N°
180 1764 3332 4916
279 1863 3431 5015
378 1962 3530 5114
477 2061 3629 5213
576 2160 3728 5312
675 2259 3827 5411
774 2358 3926 5510
8 73 2457 4025 569
9 72 2556 4124 578
10 71 26 55 42 23 58 7
11 70 27 54 43 22 59 6
12 69 28 53 44 21 60 5
13 68 29 52 45 20 61 4
14 67 30 51 46 19 62 3
15 66 31 50 47 18 63 2
16 65 32 49 48 17 64 1
Output N° Pin N° Output N° Pin N° Output N° Pin N°
4/15
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Page 5
PADSDIMENSIONS (in µm)/ PADS POSITIONS
The reference is the centre of the die (x=0, y=0)
TOP SIDE from left to right
Name Centre:X Centre:Y Size:x SIze: y
V
V
V
V
V
SSLOG
SSP
SSP
-2468.5 4135.0 75.0 90.0
PP
-2313.5 4135.0 75.0 90.0
-2188.5 4135.0 75.0 90.0
-2063.5 4134.5 75.0 90.0
PP
-1620.0 4135.0 75.0 90.0
CLK -1430.0 4135.0 75.0 90.0
STB -781.0 4135.0 75.0 90.0
SOUT -612.5 4135.0 75.0 90.0
V
CC
-335.5 4144.5 75.0 90.0
SIN 379.5 4135.0 75.0 90.0
F/R 548.0 4135.0 75.0 90.0
BLK 1082.0 4135.0 75.0 90.0
POL 1853.0 4135.0 75.0 90.0
2021.5 4140.0 75.0 90.0
2156.5 4140.0 75.0 90.0
2291.5 4140.0 75.0 90.0
2454.5 4129.5 75.0 90.0
V
V
V
V
PP
SSP
SSP
PP
BOTTOM SIDE from left to right
Name Centre:X Centre:Y Size:x SIze: y
OUT34 -2468.0 -4087.5 75.0 90.0
OUT33 -2318.0 -4089.5 75.0 90.0
V
V
V
V
V
V
SSSUB
V
SSLOG
V
SSLOG
V
V
SSLOG
V
SSSUB
SSP
SSP
SSP
CC
-2182.0 -4089.5 75.0 90.0
PP
-2047.0 -4093.0 75.0 90.0
-1912.0 -4093.0 75.0 90.0
-1777.0 -4093.0 75.0 90.0
-1642.0 -4089.5 75.0 90.0
PP
-683.0 -4088.0 75.0 90.0
-382.5 -4088.0 75.0 90.0
419.5 -4087.5 75.0 90.0
618.5 -4087.5 75.0 90.0
951.0 -4087.5 75.0 90.0
1308.0 -4087.5 75.0 90.0
STV7697A
BOTTOM SIDE from left to right (continued)
Name Centre:X Centre:Y Size:x SIze: y
V
PP
V
SSP
V
SSP
V
SSP
V
PP
OUT32 2318.0 -4093.5 75.0 90.0
OUT31 2468.5 -4093.5 75.0 90.0
RIGHT SIDE from top to bottom
Name Centre:X Centre:Y Size:x SIze: y
OUT1 2647.0 3697.0 90.0 75.0
OUT2 2647.0 3484.0 90.0 75.0
OUT3 2647.0 3238.5 90.0 75.0
OUT4 2647.0 2992.5 90.0 75.0
OUT5 2647.0 2743.0 90.0 75.0
OUT6 2647.0 2506.5 90.0 75.0
OUT7 2647.0 2264.0 90.0 75.0
OUT8 2647.0 2018.0 90.0 75.0
OUT9 2647.0 1774.5 90.0 75.0
OUT10 2647.0 1529.0 90.0 75.0
OUT11 2647.0 1285.5 90.0 75.0
OUT12 2647.0 1040.0 90.0 75.0
OUT13 2647.0 796.5 90.0 75.0
OUT14 2647.0 551.0 90.0 75.0
OUT15 2647.0 307.5 90.0 75.0
OUT16 2647.0 62.0 90.0 75.0
OUT17 2647.0 -181.5 90.0 75.0
OUT18 2647.0 -427.0 90.0 75.0
OUT19 2647.0 -670.5 90.0 75.0
OUT20 2647.0 -916.0 90.0 75.0
OUT21 2647.0 -1159.5 90.0 75.0
OUT22 2647.0 -1405.0 90.0 75.0
OUT23 2647.0 -1648.5 90.0 75.0
OUT24 2647.0 -1894.0 90.0 75.0
1438.5 -4087.5 75.0 90.0
1797.5 -4093.5 75.0 90.0
1932.5 -4093.5 75.0 90.0
2067.5 -4093.5 75.0 90.0
2193.0 -4093.5 75.0 90.0
5/15
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Page 6
STV7697A
RIGHT SIDE from top to bottom (continued)
Name Centre:X Centre:Y Size:x SIze: y
OUT25 2647.0 -2137.5 90.0 75.0
OUT26 2647.0 -2383.5 90.0 75.0
OUT27 2647.0 -2627.0 90.0 75.0
OUT28 2647.0 -2872.5 90.0 75.0
OUT29 2647.0 -3116.0 90.0 75.0
OUT30 2647.0 -3363.0 90.0 75.0
LEFT SIDE from bottom to top
Name Centre:X Centre:Y Size:x SIze: y
OUT35 -2646.5 -3363.0 90.0 75.0
OUT36 -2646.5 -3116.0 90.0 75.0
OUT37 -2646.5 -2872.5 90.0 75.0
OUT38 -2646.5 -2627.0 90.0 75.0
OUT39 -2646.5 -2383.5 90.0 75.0
OUT40 -2646.5 -2137.5 90.0 75.0
OUT41 -2646.5 -1894.0 90.0 75.0
OUT42 -2646.5 -1648.5 90.0 75.0
OUT43 -2646.5 -1405.0 90.0 75.0
OUT44 -2646.5 -1159.5 90.0 75.0
OUT45 -2646.5 -916.0 90.0 75.0
OUT46 -2646.5 -670.5 90.0 75.0
OUT47 -2646.5 -427.0 90.0 75.0
OUT48 -2646.5 -181.5 90.0 75.0
OUT49 -2646.5 62.0 90.0 75.0
OUT50 -2646.5 307.5 90.0 75.0
OUT51 -2646.5 551.0 90.0 75.0
OUT52 -2646.5 796.5 90.0 75.0
OUT53 -2646.5 1040.0 90.0 75.0
OUT54 -2646.5 1285.5 90.0 75.0
OUT55 -2646.5 1529.0 90.0 75.0
OUT56 -2646.5 1774.5 90.0 75.0
OUT57 -2646.5 2018.0 90.0 75.0
OUT58 -2646.5 2264.0 90.0 75.0
OUT59 -2646.5 2506.5 90.0 75.0
OUT60 -2646.5 2743.0 90.0 75.0
LEFT SIDE from bottom to top (continued)
Name Centre:X Centre:Y Size:x SIze: y
OUT61 -2646.5 2949.5 90.0 75.0
OUT62 -2646.5 3228.5 90.0 75.0
OUT63 -2646.5 3487.0 90.0 75.0
OUT64 -2646.5 3763.0 90.0 75.0
6/15
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Page 7
BLOCK DIAGRAM
93
CLK
89
92
STB
V
CC
86
BLK
V
CC
85
POL
STV7697A
STV7697A
V
CC
87
64-BITSHIFTREGISTER
P1 P64
Q1 Q64Q2 Q63
---
V
SSP
80 1
OUT1 OUT64
LATCH
V
PP
V
SSP
S64S1
---
V
PP
F/R
91
SOUT(SIN)SIN(SOUT)
V
SSSUB
Pins 38-43
V
SSLOG
Pins 39-40-42-94
V
CC
Pins 41-90
V
SSP
Pins34-35 -36-45-46
47-82-83-98-99
V
PP
Pins 33-37-44-48
81-84-97-100
CIRCUIT DESCRIPTION
The STV7697Acontains all the logic and the power circuits necessary to drive rows of a Plasma
Display Panel (P. D. P.). The state of the displayed
line is loaded into the shift register. Data are shifted at each low to high transition of the (CLK) shift
clock. After 64 shifts the first bit is available at the
serial output. This output can be used to cascade
several drivers to perform any vertical resolution.
The forward / reverse (F/R) input is used to select
the direction of the shift register, data input/output
status is set according to the selected direction.
SIN, CLK, STB inputs
are Smith trigger inputs . If not used on the application, F/R, BLK, POL logical inputs are internaly
pulled to level ”1”. The maximum frequency of the
shift clock is 20 MHz.
All the data are memorized into the latch stage
when the strobe input (STB) is pulled high.
Blanking input (BLK) forces the power outputs to
high level when pulled high with polarity input
(POL) at high level and forced to low level with
POL at low level.
The level of the power output is inverted when the
polarity command (POL) is pulled high.
Sustain currentmust not be sunk in the power outputtoVPPwhen the power supply is applied.
V
SSLOG
and V
SSSUB
must be connected as close
as possible to the logical reference ground of the
application.
Shift Register Truth Table
Input Input/Output
F/R CLK SIN SOUT Output Q
H Rise IN OUT Forward Shift
H H or L IN OUT Steady
L Rise OUT IN Reverse Shift
L H or L OUT IN Steady
Shift Register
Function
7/15
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Page 8
STV7697A
Power Output Truth Table
Qn (1) STB BLK POL Driver Output Comments
X X H H All H Forced to High
X X H L All L Forced to Low
H L L L H Copy Data
L L L L L Copy Data
H L L H L Copy Inverted Data
L L L H H Copy Inverted Data
X H L L Qn Data Latched
X H L H Qn Inverted Data Latched
Note 1 Qn is theparallel output of the shift register (n = 1 to 64). Qn takes the value of serial input (SIN) after ”n” shift
clock periods.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
V
V
POUT
I
POUT
I
DOUT
T
T
T
CC
PP
IN
OUT
jmax
oper
stg
Logic Supply Range -0.3, +7 V
Driver Supply Range -0.3, +170 V
Logic Input Voltage Range
Logic Output Voltage Range
Driver Output Voltage Range
-0.3, V
-0.3, V
CC
CC
-0.3, V
+0.3
+ 0.3
PP
V
V
V
Driver Output Current (3) (5) +100/-400 mA
Diode Output Current (4) (5) ±700 mA
Operating Temperature -20, +85 °C
Junction Temperature (2) +125 °C
Storage Temperature -50,+150 °C
THERMAL DATA
Symbol Parameter Value Unit
R
th(j-a)
P
oper
T
joper
Note 2 For PQFP100 packaging.
Note 3 Through one power output.
Note 4 Through one power output with V
Note 5 These parameters are measured during ST’s internal qualification which includes temperature characterisation
on standard batches and on corners batches of the process. These parameters are not tested on the parts.
8/15
3
Junction-ambient Thermal Resistance (2) Max 50 °C/W
Operating Power Dissipation (T
=25°C) Max 2 W
amb
Operating Junction Temperature (2) Max +125 °C
PP =VSSP
(see test diagram)
.
Page 9
ELECTRICAL CHARACTERISTICS
STV7697A
(VCC=5V,VPP= 160 V, V
SSP
=0V,V
SSLOG
=V
SSSUB
=0V,T
amb
=25°C, f
= 20 MHz, unless
CLK
otherwise specified)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
SUPPLY
V
CC
I
CCH
I
CCL
V
PP
I
PPH
OUTPUT
OUT1-OUT64
V
POUTH
V
POUTL
V
DOUTH
V
DOUTL
SOUT
V
OH
V
OL
INPUT (CLK, F/ , , POL, BLK, SIN, )
V
IH
V
IL
I
IH
I
IL
Logic Supply Voltage 4.5 5 5.5 V
Logic Supply Current (all inputs high) - - 100 µA
f
Logic Supply Current
= 8 MHz, SIN = 1010
CLK
- 5.3 - mA
Power Output Supply Voltage 15 - 160 V
Power Output Supply Current
- - 100 µA
(steady outputs)
Power Output High Level (voltage drop
versus V
PP
)
Power Output Low Level I
Output Diode High Level I
Output Diode Low Level I
= - 10 mA
I
POUTH
= - 40 mA
I
POUTH
= 200 mA - 3.1 10 V
POUTL
= +400 mA (5) - 2.3 10 V
DOUTH
= - 400 mA (5) -10 -2.2 - V
DOUTL
10
-
-
5
-
-
Logic Output High Level IOH=1mA 4 - - V
Logic Output Low Level IOL= -1 mA - - 0.4 V
RSTB
Input High Level
Input Low Level - -
High Level Input Current
Low Level Input Current CLK, SIN, ,
F/ , BLK, POL
STB
R
V
IH=VCC
VIL=0V
0.8 V
--V
CC
0.2V
CC
--10µA
-
-
70
-
10
100
V
V
V
µA
µA
Note 6 Compatible with power dissipation (see test diagram).
9/15
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Page 10
STV7697A
AC TIMINGS REQUIREMENTS
(VCC=4.5 V to 5.5 V,T
Symbol Parameter Min. Typ. Max. Unit
t
CLK
t
WHCLK
t
WHCLK
t
SDAT
t
HDAT
t
SFR
t
DSTB
t
STB
t
BLK
t
POL
Data Clock Period 50 - - ns
Duration of clock (CLK) pulse at high level 15 - - ns
Duration of clock (CLK) pulse at low level 15 - - ns
Set-up Time of data input before clock low to high transition 10 - - ns
Hold Time of data input after clock low to high transition 10 - - ns
Forward/reverse (F/R) Set-upTime before low to high transition 100 - - ns
Minimum Delay to latch STB after clock low to high transition 10 - - ns
Strobe STB Pulse Duration 20 - - ns
Blank (BLK) Pulse Duration 500 - - ns
Polarity (POL) Pulse Duration 500 - - ns
= -20 to +85°C,input signals max leading edge & trailing edge (tR,tF) = 10 ns)
amb
AC TIMINGS CHARACTERISTICS
(VCC=5V,VPP=90V,V
Vcc, V
= 0.8 VCC,VOH= 4.0 V,VOL= 0.4 V,CL= 15pF, unless otherwise specified)
IHMin.
SSP
=0V,V
SSLOG=VSSSUB
=0V,T
amb
=25°C, f
= 20 MHz, V
CLK
ILMax.
= 0.2
Symbol Parameter Min. Typ. Max. Unit
t
CLK
t
RDAT
t
FDAT
t
PHL1
t
PLH1
t
PHL2
t
PLH2
t
PHL3
t
PLH3
t
PHL4
t
PLH4
t
ROUT
t
FOUT
Note 7 One output among 64, loading capacitor C
Data Clock Period 50 - - ns
Logical Data Output Rise Time
Logical Data Output Fall Time
Delay of logic data output after clock (CLK) high to low transition
Delay of logic data output after clock (CLK) low to high transition
Delay of power output change after clock (CLK) high to low transition
Delay of power output change after clock (CLK) low to high transition
Delay of power output change after blanking (BLK) high to low transition
Delay of power output change after blanking (BLK) low to high transition
Delay of power output change after polarity (POL)high to low transition
Delay of power output change after polarity (POL)low to high transition
Power Output Rise Time (7)
Power Output Fall Time (7)
= 100pF, other outputs at low level.
OUT
-
-
-
-
-
-
-
-
-
-
-
-
20
11
45
48
120
120
110
110
-
-
100
60
-
-
80
80
180
180nsns
165
165nsns
160
160nsns
200
200nsns
ns
ns
ns
ns
10/15
3
Page 11
Figure 1. AC Characteristics Waveform
t
WLCLK
CLK
SIN
SOUT
STB
F/R
OUTn
BLK
OUTn
POL
OUTn
50% 50% 50%
t
FDAT
10%
10%
90%
90%
t
RDAT
50% 50%
t
PLH3
10%
50% 50%
t
PHL4
90%
10%
t
ROUT
90%
10%
t
FOUT
t
CLK
t
WHCLK
t
SDAT
50% 50%
t
PLH1
50%
t
STB
t
SFR
50%
t
PHL2
90%
t
PLH2
t
BLK
t
POL
90%
t
t
DSTB
HDAT
t
PHL3
90%
10%
t
PLH4
STV7697A
50%50%
10%
”1”
”0”
”1”
”0”
”1”
”0”
”1”
”0”
”1”
”0”
”1”
”0”
”1”
”0”
”1”
”0”
”1”
”0”
”1”
”0”
11/15
Page 12
STV7697A
Figure 2. Test Configuration
V
PP
V
PP
V
DOUTH
I
DOUTL
OUTI
OUTI
V
DOUTL
V
SSP
V
SSP
Output sinking current as positive value, sourcing current as negative value
I
DOUTL
12/15
Page 13
INPUT/OUTPUT SCHEMATICS
STV7697A
Figure 3. F/R, BLK, POL, HIZ
F/R,BLK, POL
(Pins 87,86, 85)
V
SSSUB
(Pins 38, 43)
Figure 4. CLK, STB
V
CC
(Pins41, 90)
V
SSLOG
(Pins 39, 40,
42, 94)
VCC(Pins41, 90)
Figure 5. SIN, SOUT Input
SIN, SOUT
(Pins 89,91)
V
SSSUB
(Pins38, 43)
V
(Pins39, 40, 42, 94)
SSLOG
Figure 6. Power Output
V
(Pins 33,37, 44, 48, 81,84, 97, 100)
PP
VCC(Pins 41,90)
V
(Pins 39,40, 42, 94)
SSLOG
CLK, STB
(Pins 93, 92)
V
SSSUB
(Pins 38, 43)
V
(Pins 39, 40, 42,94)
SSLOG
OUTi
(Pins1 to 32, 49 to 80)
V
SSP
(Pins34, 35, 36, 45,46, 47, 82, 83, 98, 99)
13/15
Page 14
STV7697A
PACKAGE MECHANICAL DATA
100 PINS - THIN PLASTIC QUAD FLAT PACK (PQFP100)
80 51
81
e
50
E3
SEATING PLANE
E
E1
0,10 mm
.004 inch
A
A2
A1
B
100
130
D3
D1
D
31
L1
L
K
Millimeters Inches
Dimensions
Min. Typ. Max. Min. Typ. Max.
A 3.40 0.134
A1 0.25 0.010
A2 2.55 2.80 3.05 0.100 0.110 0.120
B 0.22 0.38 0.0087 0.015
C 0.13 0.23 0.005 0.009
D 22.95 23.20 23.45 0.903 0.913 0.923
D1 19.90 20.00 20.10 0.783 0.787 0.791
D3 18.85 0.742
e 0.65 0.026
E 16.95 17.20 17.45 0.667 0.677 0.687
E1 13.90 14.00 14.10 0.547 0.551 0.555
E3 12.35 0.486
L 0.65 0.80 0.95 0.026 0.031 0.037
L1 1.60 0.063
K0°(Min.), 7° (Max.)
c
14/15
Page 15
STV7697A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other
rights ofthird parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject tochange
without notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics.
2000 STMicroelectronics - All Rights Reserved
Purchase of I
Rights to use these components in a I
Australia - Brazil - China -Finland - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The
Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
2
C Components ofSTMicroelectronics, conveys a license under the Philips I2C Patent.
Standard Specifications as defined by Philips.
STMicroelectronics GROUP OF COMPANIES
2
C system, is granted provided that the system conforms to the I2C
http://www.st.com
15/15
4
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