Datasheet STGIPS40W60L1 Datasheet (ST)

SLLIMM™ (small low-loss intelligent molded module)

IPM, single phase - 40 A, 600 V ultra fast IGBT

Features

■ IPM 40 A, 600 V single phase IGBT including

control ICs for gate driving and free-wheeling
diodes

■ IGBTs with excellent trade-off between low

conduction losses and fast switching
performance

■ V

■ 3.3 V, 5 V, 15 V CMOS/TTL inputs

comparators with hysteresis and pull down /
pull up resistors

■ Undervoltage lockout

■ Internal bootstrap diode

■ Dead time and interlocking function

■ Smart shutdown function

■ Comparator for fault protection against over

temperature and overcurrent

■ DBC substrate leading to low thermal

resistance

■ Isolation rating of 2500 V

■ 4.7 kΩ NTC UL recognized for temperature

control

■ UL recognition pending (in agreement to

QQQX2.E81734 - Electrically-isolated
semiconductor devices - component)

negative temperature coefficient

CE(sat)

rms

/min

STGIPS40W60L1

Preliminary data

SDIP-22L

Description

This intelligent power module provides a compact,
high performance AC motor drive for a simple and
rugged design. It targets high frequency
converters. It combines ST proprietary control ICs
with the most advanced IGBT and diode
technologies tailored to high switching frequency
operation. SLLIMM™ is a trademark of
STMicroelectronics.

Applications

■ Power factor correction for compressors

Table 1. Device summary

Order code Marking Package Packaging

STGIPS40W60L1 GIPS40W60L1 SDIP-22L Tube

January 2012 Doc ID 018866 Rev 2 1/21

This is preliminar y information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.

www.st.com

21

Contents STGIPS40W60L1

Contents

1 Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . 3

2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1.1 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1.2 Dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/21 Doc ID 018866 Rev 2

STGIPS40W60L1 Internal schematic diagram and pin configuration

1 Internal schematic diagram and pin configuration

Figure 1. Internal schematic diagram

Pin22: P

Pin21: P

Pin19: PHASE

Pin20: PHASE

Pin18 : N

Pin17: N

LVG

CP+

OUT

HVG

Vboot

LIN

SD/OD

VCC

DT

HIN

Pin3: N C

Pin4: T1

Pin2: VBOOT

Pin 1: OUT

Pin5: T2

Pin7: /SD

Pin 6: /LIN

Pin8: H IN

OP+

GND

OPOUT

OP-

Pin10: OP-

Pin9: DT

Pin11: OPOUT

Pin13 : VCC

Pin12: OP+

Pin14: CIN

Pin15: GND

AM09386v2

Pin16: GND

Doc ID 018866 Rev 2 3/21

Internal schematic diagram and pin configuration STGIPS40W60L1

Table 2. Pin description

Pin Symbol Description

1OUT

2V

PHASE

boot

PHASE reference output

Bootstrap voltage

3 NC Not connected

4T

5T

1

2

6LIN

NTC thermistor terminal 1

NTC thermistor terminal 2

Low side logic input

7SD/OD Shutdown logic input (active low) / open drain (comparator output)

8 HIN High side logic input

9 DT Dead time setting

10 OP- Op amp inverting input

11 OP

OUT

Op amp output

12 OP+ Op amp non inverting input

13 V

CC

Low voltage power supply

14 CIN Comparator input

15 GND Ground

16 GND Ground

17 N Negative DC input

18 N Negative DC input

19 PHASE Phase output

20 PHASE Phase output

21 P Positive DC input

22 P Positive DC input

Figure 2. Pin layout (bottom view)

Marking area

4/21 Doc ID 018866 Rev 2

AM06017v1

STGIPS40W60L1 Electrical ratings

2 Electrical ratings

2.1 Absolute maximum ratings

Table 3. Inverter part

Symbol Parameter Value Unit

± I

V

± I

P

CES

CP

TOT

Each IGBT collector emitter voltage (V

Each IGBT continuous collector current

(1)

C

(2)

= 25°C

at T

C

Each IGBT pulsed collector current 80 A

= 0) 600 V

IN

40 A

Each IGBT total dissipation at TC = 25°C 100 W

1. Calculated according to the iterative formula:

ICTC()

------------ ----------------- --------------- ----------------- ----------------- ----------------- --------=

R

thj c–

T

V

CE sat()max()Tjmax()ICTC

–

jmax()TC

(),()×

2. Pulse width limited by max junction temperature

Table 4. Control part

Symbol Parameter Value Unit

V

V

V

V

OUT

CIN

boot

V

Output voltage applied between

- GND

OUT

Low voltage power supply -0.3 to +21 V

CC

V

boot

- 21 to V

boot

Comparator input voltage -0.3 to VCC +0.3 V

Bootstrap voltage applied between

- OUT

V

boot

Logic input voltage applied between HIN, LIN and

IN

GND

-0.3 to 620 V

-0.3 to 15 V

+ 0.3 V

V

dV

SD/OD

OUT

Open-drain voltage -0.3 to 15 V

/dt Allowed output slew rate 50 V/ns

Table 5. Total system

Symbol Parameter Value Unit

V

ISO

(1)

T

J

T

C

1. The maximum junction temperature rating of the power chips integrated within the SDIP module is 150°C
(@T
limited to T

Isolation withstand voltage applied between each
pin and heatsink plate (AC voltage, t = 60 sec.)

2500 V

Operating junction temperature for IGBT and diode -40 to 150 °C

Module case operation temperature -40 to 125 °C

≤ 100°C). To ensure safe operation of the SDIP module, the average junction temperature should be

C

(avg) ≤ 125°C (@TC ≤ 100°C).

j

Doc ID 018866 Rev 2 5/21

Electrical ratings STGIPS40W60L1

2.2 Thermal data

Table 6. Thermal data

Symbol Parameter Value Unit

R

thJC

Figure 3. Transient thermal impedance IGBT/diode - inverter

Thermal resistance junction-case single diode 2.5 °C/W

10

1

[K/W]

Diode

thj-c

Z

IGBT

0.1

0.01

1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02

time [s]

Thermal resistance junction-case single IGBT 1.25 °C/W

AM09385v1

6/21 Doc ID 018866 Rev 2

STGIPS40W60L1 Electrical characteristics

3 Electrical characteristics

TJ = 25 °C unless otherwise specified.

Table 7. Inverter part

Value

Symbol Parameter Test conditions

Min. Typ. Max.

Unit

V

CE(sat)

I

CES

V

Collector-emitter
saturation voltage

Collector-cut off current

= 0 "logic state")

(V

IN

Diode forward voltage VIN = 0 "logic state", IF = 30A - 2.5 V

F

Switching on/off (inductive load)

t

t

c(on)

t

t

c(off)

E

E

di/dt

t

t

c(on)

t

t

c(off)

E

E

di/dt

Tur n - on t i m e

on

Crossover time (on) - 80 -

Turn-off time - 320 -

off

Crossover time (off) - 125 -

t

Reverse recovery time - 115 -

rr

Turn-on switching losses - 585 -

on

Turn-off switching losses - 600 -

off

Rate of rise of on-state

(on)

current

Tur n - on t i m e

on

Crossover time (on) - 110 -

Turn-off time - 420 -

off

Crossover time (off) - 140 -

t

Reverse recovery time - 150 -

rr

Turn-on switching losses - 930 -

on

Turn-off switching losses - 780 -

off

Rate of rise of on-state

(on)

current

VCC = V
state", I

V

CC

state", I

V

CE

(1)

V

DD

V

CC

= V

= 410 V,
= V

= 15 V, VIN = 1 "logic

boot

= 30 A

C

= 15 V, VIN = 1 "logic

boot

= 30 A, TJ = 125 °C

C

= 600 V, V

boot

CC

= 15 V,

= V

VIN = 1 "logic state" (see
IC = 30 A (see

Figure 4

VDD = 410 V, VCC = V
V

= 1 "logic state" (see

IN

IC = 80 A (see

V

= 410 V,

DD

VCC = V
V

= 1 "logic state" (see

IN

boot

Figure 4

= 15 V,

IC = 30 A, TJ = 125 °C
(see

Figure 4

= 410 V,

V

DD

VCC = V

boot

and 5)

= 15 V,
VIN = 1 "logic state" (see
I

= 80 A, TJ = 125 °C

C

(see

Figure 4

and 5)

-2.02.5

-1.7

= 15 V, - 500 µA

Boot

- 410 -

Ta bl e 1 3

)

and 5)

= 15 V,

boot

Ta bl e 1 3

),

- 2500 - A/µs

and 5)

- 550 -

Ta bl e 1 3

Ta bl e 1 3

)

)

- 2100 - A/µs

V

ns

µJ

ns

µJ

1. tON and t
under the internally given gate driving condition. Parameter values take into account a 20 nH stray inductance.

include the propagation delay time of the internal drive. t

OFF

C(ON)

and t

are the switching time of IGBT itself

C(OFF)

Doc ID 018866 Rev 2 7/21

Electrical characteristics STGIPS40W60L1

Figure 4. Switching time test circuit

Figure 5. Switching time definition

100% IC 100% IC

t

rr

VCE

IC IC

VIN

t

ON

t

C(ON)

VIN(ON)

10% IC 90% IC 10% VCE

(1)

VIN

VIN(OFF)

t

OFF

VCE

t

C(OFF)

10% VCE 10% IC

1. “Switching time definition" refers to HIN inputs (active high). For LIN
be inverted for turn-on and turn-off.

8/21 Doc ID 018866 Rev 2

(a) turn-on

(b) turn-off

AM09223V1

inputs (active low), VIN polarity must

STGIPS40W60L1 Electrical characteristics

3.1 Control part

Table 8. Low voltage power supply (VCC = 15 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

CC_hys

V

CC_thONVCC

V

CC_thOFFVCC

I

qccu

I

qcc

VCC UV hysteresis 1.2 1.5 1.8 V

UV turn ON threshold 11.5 12 12.5 V

UV turn OFF threshold 10 10.5 11 V

Undervoltage quiescent
supply current

Quiescent current

VCC = 10 V
SD

/OD = 5 V; LIN = 5 V;

HIN = 0, CIN = 0

= 15 V

V

CC

SD/OD = 5 V; LIN = 5 V

200 µA

1mA

HIN = 0, CIN = 0

V

ref

Internal reference voltage 0.5 0.54 0.58 V

Table 9. Bootstrapped voltage (VCC = 15 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

BS_hys

V

BS_thONVBS

V

BS_thOFFVBS

I

QBSU

I

QBS

V

UV hysteresis 1.2 1.5 1.8 V

BS

UV turn ON threshold 10.6 11.5 12.4 V

UV turn OFF threshold 9.1 10 10.9 V

Undervoltage VBS quiescent
current

VBS quiescent current

VBS = 10 V
SD/OD = 5 V; LIN and

HIN = 5 V; CIN = 0

= 15 V

V

BS

SD

/OD = 5 V; LIN and

70 110 µA

150 210 µA

HIN = 5 V; CIN = 0

R

DS(on)

Bootstrap driver on resistance LVG ON 120 Ω

Table 10. Logic inputs (VCC = 15 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

Low logic level voltage 0.8 V

il

V

I

HINh

I

HINl

I

LINl

I

LINh

I

SDh

I

SDl

High logic level voltage 2.25 V

ih

HIN logic “1” input bias current HIN = 15 V 110 175 260 µA

HIN logic “0” input bias current HIN = 0 V 1 µA

LIN logic “1” input bias current LIN = 0 V 3 6 20 µA

LIN logic “0” input bias current LIN = 15 V 1 µA

SD logic “0” input bias current SD = 15 V 10 40 100 µA

SD logic “1” input bias current SD = 0 V 1 µA

Doc ID 018866 Rev 2 9/21

Electrical characteristics STGIPS40W60L1

Table 11. Op amp characteristics (VCC = 15 V)

Symbol Parameter Test condition Min Typ Max Unit

V

io

I

io

I

ib

V

icm

V

OL

V

OH

I

o

SR Slew rate

GBWP Gain bandwidth product V

A

vd

SVR Supply voltage rejection ratio vs. V

Input offset voltage Vic = 0 V, Vo = 7.5 V 6 mV

Input offset current

V

= 0 V, Vo = 7.5 V

Input bias current

(1)

ic

Input common mode voltage
range

Low level output voltage RL = 10 kΩ to V

0V

CC

440nA

100 200 nA

75 150 mV

High level output voltage RL = 10 kΩ to GND 14 14.7 V

Output short circuit current

Source,
V

= + 1; Vo = 0 V

id

Sink,

= - 1; Vo = V

V

id

= 1 - 4 V; CL = 100 pF;

V

i

CC

unity gain

= 7.5 V 8 12 MHz

o

16 30 mA

50 80 mA

2.5 3.8 V/μs

Large signal voltage gain RL = 2 kΩ 70 85 dB

CC

60 75 dB

CMRR Common mode rejection ratio 55 70 dB

1. The direction of input current is out of the IC.

Table 12. Sense comparator characteristics (VCC = 15 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

ib

V

t

d_comp

Input bias current V

Open-drain low-level output

ol

voltage

Comparator delay

SR Slew rate C

t

sd

Shutdown to high / low side
driver propagation delay

Comparator triggering to high /

t

isd

low side driver turn-off
propagation delay

= 1 V - 1 µA

CP+

= - 3 mA - 0.5 V

I

od

/OD pulled to 5 V through

SD
100 kΩ resistor

= 180 pF; Rpu = 5 kΩ -60 V/µsec

L

V

= 0, V

OUT

V

= 0 to 3.3 V

IN

Measured applying a voltage
step from 0 V to 3.3 V to pin
CINi

boot

= VCC,

- 90 130 ns

50 125 200

ns

50 200 250

10/21 Doc ID 018866 Rev 2

STGIPS40W60L1 Electrical characteristics

Table 13. Truth table

Logic input (VI) Output

Condition

SD

/OD LIN HIN LVG HVG

Shutdown enable
half-bridge tri-state

Interlocking
half-bridge tri-state

0 ‘’logic state”
half-bridge tri-state

1 “logic state”
low side direct driving

1 “logic state”
high side direct driving

Note: X: don’t care

LXXLL

HLHLL

HHL L L

HLLHL

HHHL H

Doc ID 018866 Rev 2 11/21

Electrical characteristics STGIPS40W60L1

3.1.1 NTC thermistor

Table 14. NTC thermistor

Symbol Parameter Test conditions Min. Typ. Max. Unit.

R

25

R

125

B B-constant T

Resistance TC = 25°C 4.7 kΩ

Resistance TC = 125°C 160 Ω

= 25°C 3950 K

C

T Operating temperature -40 150 °C

Equation 1: resistance variation vs. temperature

1

1

⎛⎞

B

---

--------- -–

⎝⎠

T

RT() R

25

e

⋅=

298

Where T are temperatures in Kelvins

Figure 6. NTC resistance vs. temperature

R (kΩ)

R (kΩ)

100

100

AM07843v1

AM07843v1

10

10

1

1

0.1

0.1

0.01

0.01
T (°C)

-50 0 50 100

-50 0 50 100

T (°C)

12/21 Doc ID 018866 Rev 2

STGIPS40W60L1 Electrical characteristics

3.1.2 Dead time

Figure 7. Dead time and interlocking waveforms definitions

LIN

CONTROL SIGNAL EDGES
OVERLAPPED:

INTERLOCKING + DEAD TIME

CONTROL SIGNALS EDGES
SYNCHRONOUS (*):

DEAD TIME

CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:

DEAD TIME

HIN

LVG

HVG

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

LIN

HIN

LVG

HVG

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

LIN

HIN

LVG

HVG

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

INTERLOCKING

DTLH

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

DTLH DTHL

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

LH

DT

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

INTERLOCKING

DTHL

DT

HL

CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:

DIRECT DRIVING

LIN

HIN

LVG

HVG

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

DTLH

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

DTHL

(*) HIN and LIN can be connected together and driven by just one control signal

Figure 8. Typical dead time vs. DT resistor value

3.5

3

2.5

2

DT (µs)

1.5

1

0.5

0

0 50 100 150 200 250 300

Rdt (kOhm)

AM06020v1

Doc ID 018866 Rev 2 13/21

Electrical characteristics STGIPS40W60L1

3.2 Recommendations

● Input signal HIN is active high logic. A 85 kΩ (typ.) pull down resistor is built-in for each

high side input. If an external RC filter is used, for noise immunity, pay attention to the
variation of the input signal level.

● Input signal LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an

internal 5 V regulator through a diode, is built-in for each low side input.

● To prevent the input signals oscillation, the wiring of each input should be as short as

possible.

● By integrating an application specific type HVIC inside the module, direct coupling to

MCU terminals without any opto-coupler is possible.

● Each capacitor should be located as nearby the pins of IPM as possible.

● Low inductance shunt resistors should be used for phase leg current sensing.

● Electrolytic bus capacitors should be mounted as close to the module bus terminals as

possible. Additional high frequency ceramic capacitor mounted close to the module
pins will further improve performance.

● The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see

Section 4: Smart shutdown function

● When setting the maximum voltage to be applied between P-N, the internal stray

inductance and the maximum di/dt should be considered. Due to both internal and
layout stray inductances, the di/dt results in a voltage surges between the DC-link
capacitor and the switches during commutations.

● Suggested control supply voltage (V

● Suggested high side bias voltage (V

for detailed info).

): from 13.5 V to 18 V

CC

between V

BS

BOOT

and PHASE): from 13 V to 18 V

14/21 Doc ID 018866 Rev 2

STGIPS40W60L1 Smart shutdown function

4 Smart shutdown function

The STGIPS40W60L1 integrates a comparator for fault sensing purposes. The comparator
non-inverting input (C
implement a simple overcurrent protection function. When the comparator triggers, the
device is set in shutdown state and both its outputs are set to low-level leading the half­bridge in tri-state. In the common overcurrent protection architectures the comparator output
is usually connected to the shutdown input through a RC network, in order to provide a
mono-stable circuit, which implements a protection time that follows the fault condition.
Our smart shutdown architecture allows to immediately turn-off the output gate driver in
case of overcurrent, the fault signal has a preferential path which directly switches off the
outputs. The time delay between the fault and the outputs turn-off is no more dependent on
the RC values of the external network connected to the shutdown pin. At the same time the
internal logic turns on the open-drain output and holds it on until the shutdown voltage goes
below the logic input lower threshold. Finally the smart shutdown function provides the
possibility to increase the real disable time without increasing the constant time of the
external RC network.

Figure 9. Smart shutdown timing waveforms

) can be connected to an external shunt resistor in order to

IN

comp

Vref

CP+

PROTECTION

HIN/LIN

HVG/LVG

SD/OD

upper

threshold

lower

threshold

1

2

open drain gate

(internal)

Fast shut down:

real disable time

the driver outputs are set in SD state

immediately after the comparator

triggering even if the SD signal

has not yet reach

TIME CONSTANTS

= (R

ON_OD

// RSD)

1

= R

SDCSD

2

C

SD

the lower input threshold

SHUT DOWN CIRCUIT

V

BIAS

R

FROM/TO

CONTROLLER

SD

C

SD/OD

SD

R

ON_OD

SMART

SD

LOGIC

Pls refer to

Table 12

for internal propagation delay time details.

Doc ID 018866 Rev 2 15/21

Package mechanical data STGIPS40W60L1

5 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK
specifications, grade definitions and product status are available at:
ECOPACK

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

www.st.com

.

Please refer to dedicated technical note TN0107 for mounting instructions.

Table 15. SDIP-22L package mechanical data

mm.

Dim.

Min. Typ. Max.

A 43.90 44.40 44.90

A1 1.15 1.35 1.55

A2 1.40 1.60 1.80

A3 38.90 39.40 39.90

B 21.50 22.00 22.50

B1 11.25 11.85 12.45

B2 24.70 25.20 25.70

C 5.00 5.40 6.00

C1 6.50 7.00 7.50

C2 11.20 11.70 12.20

e 2.15 2.35 2.55

e1 3.40 3.60 3.80

e2 4.50 4.70 4.90

e3 15.70 15.90 16.10

e4 6.30 6.50 6.70

e5 9.20 9.40 9.60

D 33.20

D1 5.60

E 10.20

E1 0.40

F 0.85 1.00 1.15

F1 0.35 0.50 0.65

R 1.55 1.75 1.95

T 0.45 0.55 0.65

V0° 6°

16/21 Doc ID 018866 Rev 2

STGIPS40W60L1 Package mechanical data

Figure 10. SDIP-22L package drawing (dimensions are in mm.)

8229874_D

Doc ID 018866 Rev 2 17/21

Package mechanical data STGIPS40W60L1

Figure 11. SDIP-22L shipping tube (dimensions are in mm.)

AM10488v1

8123127_E

Base quantity: 11 pcs

Bulk quantity: 132 pcs

18/21 Doc ID 018866 Rev 2

STGIPS40W60L1 Package mechanical data

Figure 12. SDIP-22L shipping tube type B (dimensions are in mm.)

AM10487v1

ANTIS TAT IC S 03 P VC

8123127_E

Base quantity: 11 pcs

Bulk quantity: 132 pcs

Doc ID 018866 Rev 2 19/21

Revision history STGIPS40W60L1

6 Revision history

Table 16. Document revision history

Date Revision Changes

14-Jun-2011 1 Initial release.

24-Jan-2012 2

Added: feature

UL recognition pending (in agreement to
QQQX2.E81734 - Electrically-isolated semiconductor devices ­component) on page 1

Updated:

Figure 10 on page 17

and

Figure 11 on page 18

.

.

20/21 Doc ID 018866 Rev 2

STGIPS40W60L1

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