STMicroelectronis unique "Single Feature Size™"
strip-based process. The resulting transistor
shows extremely high packing density for low onresistance, rugged avalanche characteristics and
less critical alignment steps therefore a remarkable manufacturing reproducibility.
APPLICATIONS
■ SOLENOID AND RELAY DRIVERS
■ MOTOR CONTROL, AUDIO AMPLIFIERS
■ DC-DC CONVERTERS
■ AUTOMOTIVE ENVIRONMENT
3
1
D2PAK
TO-263
(Suffix “T4”)
TO-220
INTERNAL SCHEMATIC DIAGRAM
3
2
1
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
DS
V
DGR
V
GS
(•)Drain Current (continuous) at T
I
D
I
D
(
I
DM
P
tot
dv/dt
E
AS
T
stg
T
j
(•)Current Limited by Package
(
Pulse wi dth limited by safe operating area
••)
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
55V
55V
Gate- source Voltage± 20V
= 25°C
C
Drain Current (continuous) at TC = 100°C
••)
Drain Current (pulsed)320A
Total Dissipation at TC = 25°C
80A
80A
300W
Derating Factor2.0W/°C
(1)
Peak Diode Recovery voltage slope10V/ns
(2)
Single Pulse Avalanche Energy980mJ
Storage Temperature
Max. Operating Junction Temperature
(1)
ISD ≤80A, di/dt ≤300A/ µ s , VDD ≤ V
(2)
Starting Tj = 25 oC ID = 40A VDD = 25V
-55 to 175°C
(BR)DSS
, Tj ≤ T
JMAX
.
1/10January 2003
Page 2
STB85NF55/STP85NF55
THERMA L D ATA
Rthj-case
Rthj-amb
T
l
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
Max
Max
0.5
62.5
300
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS (T
= 25 °C unless otherwise specified)
case
OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
= 250 µA, VGS = 0
V
(BR)DSS
Drain-source
I
D
55V
Breakdown Voltage
= Max Rating
V
DS
= Max Rating TC = 125°C
V
DS
= ± 20V
V
GS
1
10
±100nA
ON
(*)
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
= V
DS
GS
= 10 VID =40 A
V
GS
ID = 250 µA
234V
0.00620.008
V
Resistance
DYNAMIC
SymbolParameterTest ConditionsMin.Typ.Max.Unit
(*)
g
fs
C
iss
C
oss
C
rss
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
= 15VI
DS
= 25V f = 1 MHz VGS = 0
V
DS
D
= 40 A
120S
3700
900
310
µA
µA
Ω
pF
pF
pF
2/10
Page 3
STB85NF55/STP85NF55
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
SymbolParameterTest ConditionsMin.Typ.Max.Unit
= 30 VID = 40 A
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Delay Time
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
SWITCHING OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
d(off)
t
f
Turn-off Delay Time
Fall Time
SOURCE DRAIN DIODE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
(*)
Pulsed: P ul se duration = 300 µs, duty cycle 1.5 %.
(
•)Pulse width limited by s afe operating area.
Source-drain Current
(•)
Source-drain Current (pulsed)
(*)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
V
DD
= 4.7
R
Ω
G
VGS = 10 V
(Resistive Load, Figure 3)
30V ID=80A VGS=10V
V
DD=
(see test circuit, Figure 4)
= 30 VID = 40 A
V
DD
= 4.7Ω, V
R
G
GS
= 10 V
(Resistive Load, Figure 3)
I
= 80 A VGS = 0
SD
I
= 80 A di/dt = 100A/µs
SD
= 25 VTj = 150°C
V
DD
(see test circuit, Figure 5)
25
100
120
30
45
70
35
75
210
5.5
150nC
80
320
1.5V
ns
ns
nC
nC
ns
ns
A
A
ns
nC
A
Safe Operating Area
Thermal Impedance
3/10
Page 4
STB85NF55/STP85NF55
Output CharacteristicsTransfer Characteristics
TransconductanceStatic Drain-source On Resistance
Gate Charge vs Gate-source VoltageCapacitance Variations
4/10
Page 5
STB85NF55/STP85NF55
Normalized Gate Threshold Voltage vs TemperatureNormalized on Resistance vs Temperature
Source-drain Diode Forward CharacteristicsNormalized Breakdown Voltage vs Temperature.
..
5/10
Page 6
STB85NF55/STP85NF55
Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test CircuitFig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent r i ght s of STMi croelectr oni cs. Spec i fications mentioned i n this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as cri tical comp onents in lif e support devi ces or systems without express written approva l of STMicroe l ectronics.
The ST logo is registered trademark of STMicroelectronics
2002 STMi croelectronics - All Ri ghts Rese rved
All other na m es are the property of their respective owners.
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10/10
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