Datasheet SP5730A, SP5730KG, SP5730MP1S, SP5730MP1T, SP5730QP1S Datasheet (MITEL)

Features

SP5730

1.3GHz Low Phase Noise Frequency Synthesiser

Preliminary Information

DS4877 issue 1.9 July 1999

● Complete 1.3GHz single chip system for

Digital Terrestrial Television applications

● Selectable reference division ratio, compatible

with (DTT) requirements

● Optimised for low phase noise, with

comparison frequencies up to 4MHz

● No RF prescaler

● Selectable reference/comparison frequency

output

● Four selectable I

2

● I

C fast mode compliant and compatible with

2

C bus address

3.3 and 5V logic levels

● Four switching ports

● ESD protection, (Normal ESD Handling

procedures should be observed)

Applications

● Digital Satellite ,Cable and Terrestrial tuning
systems

● Communications systems

Ordering Information

SP5730A/KG/MP1S Sticks
SP5730A/KG/MP1T Tape and Reel

SP5730A/KG/QP1S Sticks

SP5730A/KG/QP1T Tape amd Reel

Description

The SP5730 is a single chip frequency synthesiser
designed for tuning systems up to 1.3GHz and is
optimised for digital terrestrial applications.

The RF preamplifier interfaces direct with the RF
programmable divider, which is of MN+A construction
so giving a step size equal to the loop comparison
frequency and no prescaler phase noise degradation
over the RF operating range.

The comparison frequency is obtained either from an
on-chip crystal controlled oscillator, or from an external
source. The oscillator frequency, Fref, or phase
comparator frequency, Fcomp, can be switched to the
REF/COMP output providing a reference frequency for
a second frequency synthesiser.

The synthesiser is controlled via an I2C bus and is fast
mode compliant. It can be hard wired to respond to one
of four addresses to enable two or more synthesisers to
be used on a common bus.

The device contains four switching ports P0-P3.

SP5730 Preliminary Information

RF/COMP

enable/select

CRYSTAL
CRYSTAL CAP

RF INPUT

8/9

12 BIT

COUNT

REF DIVIDER

Osc

ADDRESS

SDA

SCL

2

I C BUS

TRANSCEIVER

3 BIT

COUNT

15 BIT LATCH

Figure 1 Block diagram

CHARGE PUMP

CRYSTAL CAP

PORT P3/LOGLEV

AGC
IOUT

CRYSTAL

VEEA

SDA

IFINB

SCL

IFIN

IVCCA

PORT P2

QOUT

PORT P1

VEEC

PORT P3

Lock
fpd/2

PUMP

2 BIT

4 BIT LATCH & PORT

INTERFACE

PORT P1

PORT P2

116

SL1711B

c/p
mode

5 BIT 2 BIT 2 BIT

fpd/2 select

PORT P0

DRIVE

VCCB

V

VCODIS

EE

RF INPUT

VCO B

RF INPUT

VCO A

V

CC

VEEB

REF/COMP

PSCAL

ADDRESS

PSCALB

PORT P0

VCCC

CHARGE PUMP

DRIVE

disable

MP16

MP16 & QP16

Figure 2 Pin connections top view

2

Preliminary Information SP5730

Electrical Characteristics

Tamb= -40oC to 85oC, VCC= 4.5 to 5.5V
These characteristics are guaranteed by either production test or design. They apply within the specified

ambient temperature and supply voltage unless otherwise stated.

Characteristic Pin Value Units Conditions

Min Typ Max

Supply current 20 mA
RF input voltage 13,14 12.5 300 mVrms 100 MHz – 1.3GHz, see Figure. 4
RF input voltage 13,14 40 300 mVrms 50MHz - 100MHz, see Figure 4
RF input impedance 13,14 See Figure. 5
SDA, SCL 4, 5
Input high voltage 3 5.5 V 5V I2C logic selected
Input low voltage 0 1.5 V 5V I2C logic selected
Input high voltage 2.3 3.5 V 3V3 I2C logic selected
Input low voltage 0 1 V 3V3 I2C logic selected
Input high current 10 µA Input voltage =Vcc
Input low current 10 µA Input voltage = Vee
Leakage current 10 µA Vee = Vcc
Hysteresis 0.4 V

SDA output voltage 4 0.4 V Isink = 3mA

0.6 V Isink = 6mA
SCL clock rate 5 400 kH
Charge pump output 1 See Table 6 Vpin1 = 2V

current
Charge pump output 1 3 10 nA Vpin1 = 2V, Vcc = 5V, +25°C

leakage
Charge pump drive 16 0.5 mA Vpin16 = 0.7V

output current
Crystal frequency 2,3 2 20 MHz See Figure 3 for application

Recommended crystal 10 200 Ω 4 MHz “parallel resonant”
series resistance crystal.

External reference input 3 2 20 MHz Sinewave coupled through
Frequency 10 nF blocking capacitor

External reference drive 3 0.2 0.5 Vpp Sinewave coupled through
level 10 nF blocking capacitor

3

SP5730 Preliminary Information

Electrical Characteristics (continued)

Tamb= -40oC to 85oC, Vcc= 4.5 to 5.5V

These characteristics are guaranteed by either production test or design. They apply within the specified
ambient temperature and supply voltage unless otherwise stated.

Characteristic Pin Value Units Conditions

Min Typ Max

Buffered REF/COMP output 11 AC coupled 0.5-20MHz

output amplitude 0.35 Vpp Enabled by bit RE= 1
output impedance 250 Ω See note 2

Phase detector Comparison 4 MHz
frequency

Equivalent phase noise at phase dBc/Hz SSB, within loop bandwidth
detector -152 Fcomp = 2MHz

-158 Fcomp = 125kHz

RF division ratio 56 32767

Reference division ratio See Table 1

Output ports P0 - P3 6-9 See Note 1

sink current 2 mA Vport = 0.7
Leakage current 10 µA Vport = Vcc

Address Select 10 See Figure 4 Table 3

Input high current 1 mA Vin = Vcc
Input low current -0.5 mA Vin = Vee

Logic level select 6 See note 3

Input high level 3 Vcc V 5V I2C logic selected, or

open circuit
Input low level 0 1.5 V 3V3 I2C logic selected
Input current -10 10 µA Vin = Vee to Vcc

Notes:

1. Output ports high impedance on power up, with data, clock, and enable at logic ‘0’

2. If the REF/COMP output is not used, the output should be left open circuit or connected to Vcc, and disabled by
setting RE = 0

3. Bi-directional port. When used as an output, the input logic state is ignored. When used as an input the port should
be switched in to high impedance (off) state.

4

Preliminary Information SP5730

Absolute Maximum Ratings

All voltages are referred to Vee at 0V

Characteristic Min Max Units Conditions

Supply voltage, Vcc -0.3 7 V Transient
RF input voltage 2.5 Vpp Differential
All I/O port DC offsets -0.3 Vcc+0.3 V
SDA and SCL DC offset -0.3 6V V
Storage temperature -55 +150
Junction temperature 150
QP16 thermal resistance,
chip to ambient 80 °C/W
chip to case 20 °C/W
Power consumption at 83 mW All ports off
Vcc = 5.5V
ESD protection 2 kV mil std 883 latest revision method 3015

o

C

o

C

class 1

Functional Description

The SP5730 contains all the elements necessary, with
the exception of a frequency reference, loop filter and
external high voltage transistor, to control a varicap
tuned local oscillator, so forming a complete PLL
frequency synthesised source. The device allows for
operation with a high comparison frequency and is
fabricated in high speed logic, which enables the
generation of a loop with good phase noise performance.
It can also be operated with comparison frequencies
appropriate for frequency offsets as required in digital
terrestrial (DTT) receivers The block diagram is shown
in Figure 2.

The RF input signal is fed to an internal preamplifier,
which provides gain and reverse isolation from the
divider signals. The output of the preamplifier interfaces
direct with the 15-bit fully programmable divider, which
is of MN+A architecture, where the dual modulus
prescaler is 8/9, the A counter is 3-bits, and the M
counter is 12 bits.

The output of the programmable divider is fed to the
phase comparator where it is compared in both phase
and frequency domain with the comparison frequency.
This frequency is derived either from the on-board
crystal controlled oscillator or from an external reference
source. In both cases the reference frequency is divided
down to the comparison frequency by the reference
divider which is programmable into 1 of 29 ratios as
detailed in Table 1.

The output of the phase detector feeds a charge pump
and loop amplifier section, which when used with an
external high voltage transistor and loop filter, integrates
the current pulses into the varactor line voltage.

The programmable divider output Fpd divided by two
can be switched to port P0 by programming the device
into test mode. The test modes are described in Table 4.

Programming

The SP5730 is controlled by an I2C data bus and is
compatible with both standard and fast mode formats
and with I2C data generated from nominal 3.3V and 5V
sources. The I2C logic level is selected by the bi-directional
port P3/LOGLEV. 5V logic levels are selected by
connecting P3/LOGLEV to Vcc or leaving open circuit
and 3.3V by connecting to ground. If this port is used as
an input the P3 data should be programmed to high
impedance. If used as an output 5V logic only levels can
be used and in this case the logic state imposed by the
port on the input is ignored.

Data and Clock are fed in on the SDA and SCL lines
respectively as defined by I2C bus format. The synthesiser
can either accept data (write mode), or send data (read
mode). The LSB of the address byte (R/W) sets the
device into write mode if it is low, and read mode if it is
high. Table 2 illustrates the format of the data. The
device can be programmed to respond to several
addresses, which enables the use of more than one
synthesiser in an I2C bus system. Table 3 shows how the
address is selected by applying a voltage to the ‘address’
input.

5

SP5730 Preliminary Information

When the device receives a valid address byte, it pulls
the SDA line low during the acknowledge period, and
during following acknowledge periods after further data
bytes are received. When the device is programmed into
read mode, the controller accepting the data must pull the
SDA line low during all status byte acknowledge periods
to read another status byte. If the controller fails to pull the
SDA line low during this period, the device generates an
internal STOP condition, which inhibits further reading.

Write mode

With reference to Table 2, bytes 2 and 3 contain
frequency information bits 214-20 inclusive. Byte 4 and
byte 5 control the reference divider ratio, see Table 1,
charge pump setting, see Table 6, REF/COMP output,
seeTable 7, output ports and test modes, see Table 4.

After reception and acknowledgement of a correct ad­dress (byte 1), the first bit of the following byte determines
whether the byte is interpreted as a byte 2 or 4, a logic ‘0’
indicating byte 2, and a logic ‘1’ indicating byte 4. Having
interpreted this byte as either byte 2 or 4 the following
data byte will be interpreted as byte 3 or 5 respectively.
Having received two complete data bytes, additional
data bytes can be entered, where byte interpretation
follows the same procedure, without readdressing the
device. This procedure continues until a STOP condition
is received. The STOP condition can be generated after
any data byte, if however it occurs during a byte transmis­sion, the previous byte data is retained. To facilitate
smooth fine tuning, the frequency data bytes are only
accepted by the device after all 15 bits of frequency data
have been received, or after the generation of a STOP
condition.

Read mode

Programmable features

RF programmable
divider

Function as described above

Reference programmable
divider

Function as described above.

Charge pump current

The charge pump current can be pro
grammed by bits C1-C0 within data byte
5, as defined in Table 6.

Test mode

The test modes are invoked by bits REB.
RS, T1 and T0 as described in Table 4.

Reference/Comparison
frequency output

The reference frequency Fref or
comparison frequency Fcomp can be
switched to the REF/COMP output,
function as defined in Table 7.
RE and RS default to logic ‘I’ during
device power up, thus enabling the
comparison frequency Fcomp at the
REF/COMP output.

When the device is in read mode, the status byte read
from the device takes the form shown in Table 2.

Bit 1 (POR) is the power-on reset indicator, and this is set
to a logic ‘1’ if the Vcc supply to the device has dropped
below 3V (at 25°C), e.g. when the device is initially turned
ON. The POR is reset to ‘0’ when the read sequence is
terminated by a STOP command. When POR is set high
this indicates that the programmed information may
have been corrupted and the device reset to power up
condition.

Bit 2 (FL) indicates whether the device is phase locked,
a logic ‘1’ is present if the device is locked, and a logic ‘0’
if the device is unlocked.

6

Preliminary Information SP5730

R4 R3 R2 R1 R0 Ratio

00000 2
00001 4
00010 8
00011 16
00100 32
00101 64
0 0 1 1 0 128
0 0 1 1 1 256
0 1 0 0 0 Illegal state
01001 5
01010 10
01011 20
01100 40
01101 80
0 1 1 1 0 160
0 1 1 1 1 320
1 0 0 0 0 Illegal state
10001 6
10010 12
10011 24
10100 48
10101 96
1 0 1 1 0 192
1 0 1 1 1 384
1 1 0 0 0 Illegal State
11001 7
11010 14
11011 28
11100 56
1 1 1 0 1 112
1 1 1 1 0 224
1 1 1 1 1 448

X = don’t care

Table 1 Reference division ratio

MSB LSB

Address 1 1 0 0 0 MA1 MA0 0 A Byte 1

2

14

6

Programmable divider 0 2
Programmable divider 2
Control Data 1 T1 T0 R4 R3 R2 R1 R0 A Byte 4
Control Data C1 C0 RE RS P3 P2 P1 P0 A Byte 5

7

Table 2 Write data format (MSB is transmitted first)

13

2

5

2

12

2

4

2

11

2

3

2

10

2

2

2

9

2

1

2

8

2
2

0

A Byte 2
A Byte 3

7

SP5730 Preliminary Information

MSB LSB

Address 1 1 0 0 0 MA1 MA0 1 A Byte 1
Status byte POR FL 0 0 0 0 0 0 A Byte 2

Table 2 Read data format (MSB is transmitted first)

A : Acknowledge bit
MA1,MA0 : Variable address bits (see Table 3)

0

214- 2
R4-R0 : Reference division ratio select (see Figure 3)
C1, C0 : Charge pump current select (see Figure 6)
RE : REF/COMP output enable
RS : REF/COMP output select when RE=1 (see Figure 2)
T1-T0 : Test mode control bits
P3-P0 : P3 - P0 port output states
POR : Power on reset indicator
FL : Phase lock flag

: Programmable division ratio control bits

MA1 MA0 Address input voltage level

0 0 0 - 0.1Vcc
0 1 Open circuit
1 0 0.4Vcc - 0.6Vcc #
1 1 0.9Vcc - Vcc

# Programmed by connecting a 30kΩ ± 5% resistor between pin 10 and Vcc

Table 3 Address selection

RE.RS T1 T0 Test mode description

0 0 0 Normal operation

1 0 0 Normal operation Port P0 = Fpd/2
X 0 1 Charge pump sink.* Status byte FL set to logic ‘0’
X 1 0 Charge pump source * Status byte FL set to logic ‘0’
X 1 1 Charge pump disabled * Status byte FL set to logic ‘1’

*clocks need to be present on crystal and RF inputs to enable charge pump test modes and to toggle

Status byte bit FL

X = Dont Care

Table 4 Test modes

8

Preliminary Information SP5730

C1 C0 Current in µA

byte 5, bit 1 byte 5, bit 2

Min Typ Max
0 0 +- 116 +- 155 +- 194
0 1 +- 247 +- 330 +- 412
1 0 +- 517 +- 690 +- 862
1 1 +- 1087 +- 1450 +- 1812

Table 6 Charge pump current

2

68pF

150pF

SP5730

Figure 3 XTAL oscillator application

RE RS REF/COMP OUTPUT

0 0 High impedance
0 1 High impedance Test mode enabled, see Figure 5
1 0 Fref selected
1 1 Fcomp selected

X = don’t care

3

Table 7; REF/COMP output

9

SP5730 Preliminary Information

300

37.5

25

12.5

50 100 500 1000 1300 1500

Frequency (MHz)

Figure 4 Typical RF input sensitivity

+j1

+j0.5

+j0.2

0.50.2 10

–j0.2

–j0.5

2 5

–j1

+j2

+j5

X

–j5

–j2

FREQUENCY

1.8GHz, 2.3GHz

50MHz, 500Mhz, 1GHz 1.3GHz

MARKERS AT 1.3GHz,

, 2..8GHz

10

Figure 5 RF input impedance

Preliminary Information SP5730

C31

15nF

C32

68pF

R7

13K

T1

BCW31

R8

22K

5V Synth

C30

82pF

X1

4MHz

5V

R9

16K

R10

1K

C39

2.2nF

C41

4u7F

C33

100nF

+5V

+30V

C34

100nF

C38

100pF

C37

100pF

Varactor Line

PSOUT

PSOUTB

R16

10K

LOSEL

5V Synth

C52

4u7F

C51

100pF

C50

100nF

0V0V5V Synth

C42

100pF

C43

100nF

C44

100pF

C47

100pF

C49

100nF

C60

150pF

5V Synth

1

2

3

4

5

7

8

9

10

11

12

13

14

15

16

6

RF Input

RF Input

Xtal

Charge Pump

Drive Output

SCL

Address

I2C Bus

Interface

Programmable

Divider

Phase

Comparator

Xtal

Vcc

Ref/Comp

P0P1

P2

P3/LL

SDA

Vee

Osc

Cap

IC2

SP5769

SDA5

3

5V0

4

GND

5

SCL5

6

J3

I2C BUS

12345

J1

5 WAY 0.1" HEADER

R19

1K

Varactor Line 2

5V Synth

R20

0R

Figure 6 evaluation board schematic

11

SP5730 Preliminary Information

Figure 7 Evaluation board (top view)

12

Figure 8 Evaluation board (bottom view)

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