Datasheet SP503CF, SP504MCF Datasheet (Sipex Corporation)

®

SP504

WAN Multi-Mode Serial Transceiver

■ +5V Only

■ Seven (7) Drivers and Seven (7) Receivers

■ Driver and Receiver Tri-State Control

■ Reduced V.35 Termination Network

■ Pin Compatible with the SP503

■ Software Selectable Interface Modes:

-RS-232E (V.28)

-RS-422A (V.11, X.21)

-RS-449 (V.11 & V.10)

-RS-485

-V.35

-EIA-530 (V.11 & V.10)

-EIA-530A (V.11 & V.10)

-V.36

DESCRIPTION...

The SP504 is a single chip device that supports eight (8) physical serial interface standards for Wide Area Network Connectivity. The SP504 is fabricated using a low power BiCMOS process technology, and incorporates a Sipex patented (5,306,954) charge pump allowing +5V only operation. Seven (7) drivers and seven (7) receivers can be configured via software for any of the above interface modes at any time. The SP504 is suited for DTE–DCE applications. The SP504 requires only one external resistor per V.35 driver for compliant V.35 operation.

Vcc

22µF, 16V

SWITCHABLE V.35 TERMINATION RESISTOR NETWORKS

22µF, 16V

RxD

RXC

CTS

DSR

DCD

RI

SCT

C1+ C1-

Programmable Charge Pump

C2+ C2-

RxD

RxC

CTS

DSR

DCD

RI

SCT

SP504

Vdd

Vss

TxD

DTR

RTS

RL

LL

ST

TT

Driver DecodeReceiver Decode

22µF, 16V

TxD

DTR

RTS

RL

LL

ST

TT

1

SPECIFICATIONS

TA = +25°C and VCC = +5.0V unless otherwise noted.

MIN. TYP. MAX. UNITS CONDITIONS

LOGIC INPUTS

V

IL

V

IH

2.0 Volts

LOGIC OUTPUTS

V

OL

V

OH

2.4 Volts I

RS-485 DRIVER

TTL Input Levels

V

IL

V

IH

Outputs

2.0 Volts

HIGH Level Output +6.0 Volts LOW Level Output –0.3 Volts Differential Output ±1.5 ±5.0 Volts RL=54Ω, CL=50pF Balance ±0.2 Volts |VT| - |VT| Offset +2.5 Volts Open Circuit Voltage ±6.0 Volts Output Current 28.0 mA RL=54Ω

Short Circuit Current ±250 mA Terminated in –7V to +10V Transition Time 20 40 ns Rise/fall time, 10%–90% Max. Transmission Rate 10 Mbps RL=54Ω; Figure 3a Propagation Delay TA @ 25°C & VCC = +5V only t

PHL

t

PLH

Differential Driver Skew 20 40 ns | t

50 80 100 ns Figures 3a and 5; RL=54Ω 50 80 100 ns CL=50pF

RS-485 RECEIVER

TTL Output Levels

V

OL

Input

V

OH

2.4 Volts

HIGH Threshold +0.2 +12 Volts (a)-(b)

LOW Threshold –7.0 –0.2 Volts (a)-(b)

Common Mode Range –7.0 +12.0 Volts

HIGH Input Current Refer to Rec. input graph

LOW Input Current Refer to Rec. input graph

Receiver Sensitivity ±0.2 Volts Over –7V to +12V common

Input Impedance 12 kΩ Max. Transmission Rate 10 Mbps Figure 3a Propagation Delay TA = 25°C & VCC = +5V only t

PHL

t

PLH

Differential Receiver Skew 30 ns | t

80 110 180 ns Figures 3a and 7; A is invert80 110 180 ns ing and B is non-inverting.

V.35 DRIVER

TTL Input Levels All outputs measured w/

V

IL

V

IH

2.0 Volts connected to the non-

Outputs in Figure 18.

Differential Output ±0.44 ±0.66 Volts RL=100Ω

Source Impedance 50 100 150 Ω

Short-Circuit Impedance 135 150 165 Ω V

Voltage Output Offset –0.6 +0.6 Transition Time 35 60 ns 48kbps data rate.; TA@ 25°C Max. Transmission Rate 10 Mbps RL=100Ω

0.8 Volts

0.4 Volts I

= +3.2mA

OUT

= –1.0mA

OUT

0.8 Volts

– t

PHL

|; TA @ +25°C

PLH

0.4 Volts

mode range

– t

PHL

|; TA @ +25°C

PLH

0.8 Volts 150Ω termination resistor inverting outputs as shown

= –2V to +2V; A = B

OUT

2

SPECIFICATIONS (Continued)

TA = +25°C and VCC = +5.0V unless otherwise noted.

MIN. TYP. MAX. UNITS CONDITIONS

V.35 DRIVER

Propagation Delay TA @ 25°C & VCC = +5V only t

PHL

t

PLH

Differential Driver Skew 30 40 ns | t

V.35 RECEIVER

TTL Output Levels

V

OL

V

OH

Input

Differential Threshold ±80 mV Input Impedance 90 100 110 Ω

Short-Circuit Impedance 135 150 165 Ω V Max. Transmission Rate 10 Mbps Propagation Delay TA @ 25°C & VCC = +5V only t

PHL

t

PLH

Differential Receiver Skew 30 ns | t

RS-422 DRIVER (V.11)

TTL Input Levels

V

IL

V

IH

Outputs

Open Circuit Voltage,V

Differential Output, V

T

Balance ±0.4 Volts |VT| – |VT|

Offset +3.0 Volts

Short Circuit Current ±150 mA V Power Off Current ±100 µAVcc = 0V, V Transition Time 20 40 ns Rise/fall time, 10%-90% Max. Transmission Rate 10 Mbps RL=100Ω; Figure 3a Propagation Delay TA @ 25°C & VCC = +5V only t

PHL

t

PLH

Differential Driver Skew 20 40 ns | t

RS-422 RECEIVER (V.11)

TTL Output Levels

V

OL

V

OH

Input

HIGH Threshold +0.2 +6.0 Volts (a)-(b)

LOW Threshold –6.0 –0.2 Volts (a)-(b)

Common Mode Range –7.0 +7.0 Volts

HIGH Input Current Refer to Rec. input graph

LOW Input Current Refer to Rec. input graph

Receiver Sensitivity ±0.3 Volts VCM = +7V to –7V

Input Impedance 4 kΩ VIN = +10V to –10V Max. Transmission Rate 10 Mbps Propagation Delay TA @ 25°C & VCC = +5V only t

PHL

t

PLH

Differential Receiver Skew 30 ns | t

RS-232 DRIVER (V.28)

TTL Input Level

V

IL

V

IH

50 80 100 ns Figures 3b and 5 50 80 100 ns

– t

PHL

|; TA @ +25°C

PLH

0.4 Volts

2.4 Volts

= +2V to –2V

IN

100 130 200 ns Figure 3b and 7; A is invert100 130 200 ns ing and B is non-inverting.

– t

PHL

|; TA @ +25°C

PLH

0.8 Volts

2.0 Volts

O

±2.0 ±5.0 Volts RL=100Ω

0.5V

O

±6.0 Volts RL=3.9kΩ

0.67V

O

Volts TA @ +25°C

= 0V

out

50 80 100 ns Figure 3a and 5; 50 80 100 ns R

DIFF

PHL

=100Ω

– t

PLH

|; TA @ +25°C

0.4 Volts

2.4 Volts

80 110 180 ns Figure 3a and 7; A is invert80 110 180 ns ing and B is non-inverting.

– t

PHL

|; TA @ +25°C

PLH

0.8 Volts

2.0 Volts

= ±0.25V

3

SPECIFICATIONS (Continued)

TA = +25°C and VCC = +5.0V unless otherwise noted.

MIN. TYP. MAX. UNITS CONDITIONS

RS-232 DRIVER (V.28)

Outputs

HIGH Level Output +5.0 +15 Volts RL=3kΩ, VIN=0.8V LOW Level Output –15.0 –5.0 Volts RL=3kΩ, VIN=2.0V Open Circuit Voltage –15 +15 Volts Short Circuit Current ±100 mA V Power Off Impedance 300 Ω Vcc = 0V, V

Slew Rate 30 V/µsRL=3kΩ, CL= 50pF Transition Time 1.56 µsRL=3kΩ, CL=2500pF ; Max. Transmission Rate 120 230.4 kbps RL=3kΩ, CL=2500pF

Propagation Delay TA @ 25°C & VCC = +5V only t t

PHL PLH

0.5 1 4 µs Measured from 1.5V of V

0.5 1 4 µs to 50% of V

RS-232 RECEIVER (V.28)

TTL Output Levels

Input

V

OL

V

OH

2.4 Volts

0.4 Volts

HIGH Threshold 1.7 3.0 Volts LOW Threshold 0.8 1.2 Volts Receiver Open Circuit Bias +2.0 Volts

Input Impedance 3 5 7 kΩ VIN = +15V to –15V Max. Transmission Rate 120 230.4 kbps Propagation Delay TA @ 25°C & VCC = +5V only t t

PHL PLH

0.05 0.25 1 µs Measured from 50% of V

0.05 0.25 1 µs to 1.5V of V

RS-423 DRIVER (V.10)

TTL Input Levels

V

V Output

IL IH

2.0 Volts

0.8 Volts

Open Circuit Voltage, VO±4.0 ±6.0 Volts RL=3.9kΩ

HIGH Level Output, V

LOW Level Output, V

Short Circuit Current ±150 mA V

+3.6 +6.0 Volts RL=450Ω; V

T

–6.0 –3.6 Volts RL=450Ω; V

T

0.9V

OC

Volts TA =+25˚C,, VCC = +5.0V

Power Off Current ±100 µAVCC = 0V, V Transition Time 100 ns Rise/fall time, between ±3V Max. Transmission Rate 120 kbps RL=450Ω Propagation Delay TA @ 25°C & VCC = +5V only t t

PHL PLH

0.05 0.5 2 µs Measured from 1.5V of V

0.05 0.5 2 µs to 50% of V

RS-423 RECEIVER (V.10)

TTL Output Levels

Input

V

OL

V

OH

2.4 Volts

0.4 Volts

HIGH Threshold +0.3 +7.0 Volts

LOW Threshold –7.0 –0.3 Volts

HIGH Input Current Refer to Rec. input graph

LOW Input Current Refer to Rec. input graph

Receiver Sensitivity ±0.3 Volts VCM = +7V to –7V

Input Impedance 4 kΩ VIN = +10V to –10V Max. Transmission Rate 120 kbps

= 0V

OUT

= ±2.0V

out

VCC = +5.0V, TA @ +25°C between ±3V, TA @ +25°C

=3kΩ

OUT; RL

.

OUT

≥ 0.9V

OUT

≥ 0.9V

OUT

= 0V, VCC = +5.0V

OUT

= ±0.25V

OUT

; RL=450Ω

OUT

IN

OC OC

IN

4

SPECIFICATIONS (Continued)

TA = +25°C and VCC = +5.0V unless otherwise noted.

MIN. TYP. MAX. UNITS CONDITIONS

RS-423 RECEIVER (V.10)

Propagation Delay TA @ 25°C & VCC = +5V only t t

PHL PLH

0.05 0.2 1 µs Measured from 50% of V

0.05 0.2 1 µs to 1.5V of V

OUT

POWER REQUIREMENTS

V

CC

ICC (no interface selected) 30 mA V (RS-232 Mode) 140 mA fIN = 120kbps. Drivers loaded.

4.75 5.00 5.25 Volts

CC

=5.0V

(RS-422 Mode) 320 mA fIN = 2Mbps. Drivers loaded. (RS-449 Mode) 320 mA fIN = 2Mbps. Drivers loaded. (EIA-530 Mode) 320 mA fIN = 2Mbps. Drivers loaded. (EIA-530A Mode) 320 mA fIN = 2Mbps. Drivers loaded. (RS-485 Mode) 370 mA fIN = 2Mbps. Drivers loaded. (V.35 Mode) 210 mA fIN = 2Mbps. Drivers loaded. (V.36 Mode) 310 mA fIN = 2Mbps. Drivers loaded.

ENVIRONMENTAL AND MECHANICAL

Operating Temperature Range 0 +70 °C Storage Temperature Range –65 +150 °C Package 80–pin QFP

RECEIVER INPUT GRAPHS

IN

–3.25mA

RS-422 RECEIVER

–3V–10V

Maximum Input Current versus Voltage

+3.25mA

+10V+3V

–0.6mA

RS-423 RECEIVER

+3.25mA

–3V–10V

+10V+3V

Maximum Input Current versus Voltage

–3.25mA

RS-485 RECEIVER

+1.0mA

–3V–7V

+12V+6V

1 Unit Load Maximum Input Current versus Voltage

5

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these ratings or any other above those

Package Derating:

øJA....................................................46 °C/W

øJC...................................................16 °C/W

indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

VCC............................................................................+7V

Input Voltages:

Logic...............................-0.3V to (VCC+0.5V)

Drivers............................-0.3V to (VCC+0.5V)

Receivers...........................................±15V

Output Voltages:

Logic................................-0.3V to (VCC+0.5V)

Drivers................................................±14V

Receivers........................-0.3V to (VCC+0.5V)

Storage Temperature..........................-65˚C to +150˚C

Power Dissipation.........................................2000mW

STORAGE CONSIDERATIONS

Due to the relatively large package size of the 80-pin quad flat-pack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40°C and 60%RH. If the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 125°C in order remove moisture prior to soldering. Sipex ships the 80-pin QFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH.

OTHER AC CHARACTERISTICS

TA = +70°C to 0°C and VCC = +4.75V to +5.25V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232 MODE

t

; Tri-state to Output LOW 0.70 5.0 µsCL = 100pF, Fig. 4 ; S

PZL

t

; Tri-state to Output HIGH 0.40 2.0 µsCL = 100pF, Fig. 4 ; S

PZH

t

; Output LOW to Tri-state 0.20 2.0 µsCL = 100pF, Fig. 4 ; S

PLZ

t

; Output HIGH to Tri-state 0.40 2.0 µsCL = 100pF, Fig. 4 ; S

PHZ

RS-423 MODE

t

; Tri-state to Output LOW 0.15 2.0 µsCL = 100pF, Fig. 4 ; S

PZL

t

; Tri-state to Output HIGH 0.20 2.0 µsCL = 100pF, Fig. 4 ; S

PZH

t

; Output LOW to Tri-state 0.20 2.0 µsCL = 100pF, Fig. 4 ; S

PLZ

t

; Output HIGH to Tri-state 0.15 2.0 µsCL = 100pF, Fig. 4 ; S

PHZ

RS-422, RS-485 MODES

t

; Tri-state to Output LOW 2.80 10.0 µsCL = 100pF, Fig. 4 & 6; S

PZL

t

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 4 & 6; S

PZH

t

; Output LOW to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 4 & 6; S

PLZ

t

; Output HIGH to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 4 & 6; S

PHZ

V.35 MODE

t

; Tri-state to Output LOW 2.60 10.0 µsCL = 100pF, Fig. 4 & 6; S

PZL

t

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 4 & 6; S

PZH

closed closed closed closed

closed closed

2

1

2

1

2

1

2

6

OTHER AC CHARACTERISTICS (Continued)

TA = +70°C to 0°C and VCC = +4.75V to +5.25V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS V.35 MODE

t

; Output LOW to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 4 & 6; S

PLZ

t

; Output HIGH to Tri-state 0.15 2.0 µsCL = 15pF, Fig. 4 & 6; S

PHZ

RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232 MODE

t

; Tri-state to Output LOW 0.12 2.0 µsCL = 100pF, Fig. 2 ; S

PZL

t

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 2 ; S

PZH

t

; Output LOW to Tri-state 0.10 2.0 µsCL = 100pF, Fig. 2 ; S

PLZ

t

; Output HIGH to Tri-state 0.10 2.0 µsCL = 100pF, Fig. 2 ; S

PHZ

RS-423 MODE

t

; Tri-state to Output LOW 0.10 2.0 µsCL = 100pF, Fig. 2 ; S

PZL

t

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 2 ; S

PZH

t

; Output LOW to Tri-state 0.10 2.0 µsCL = 100pF, Fig. 2 ; S

PLZ

t

; Output HIGH to Tri-state 0.10 2.0 µsCL = 100pF, Fig. 2 ; S

PHZ

RS-422/RS-485 MODES

t

; Tri-state to Output LOW 0.10 2.0 µsCL = 100pF, Fig. 2 & 8 ; S

PZL

t

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 2 & 8 ; S

PZH

t

; Output LOW to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 2 & 8 ; S

PLZ

t

; Output HIGH to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 2 & 8; S

PHZ

V.35 MODE

t

; Tri-state to Output LOW 0.10 2.0 µsCL = 100pF, Fig. 2 & 8; S

PZL

t

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 2 & 8; S

PZH

t

; Output LOW to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 2 & 8; S

PLZ

t

; Output HIGH to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 2 & 8; S

PHZ

closed closed

closed closed closed closed

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

TRANSCEIVER TO TRANSCEIVER SKEW [ (t

phl

– t

)

– (t

– t

)

plh

Trcvr1

phl

plh

TrcvrX

]

RS-232 Driver 20 50 ns VCC = +5.0V, TA @ +25°C RS-232 Receiver 20 ns RS-422 Driver 20 50 ns VCC = +5.0V, TA @ +25°C RS-422 Receiver 20 ns RS-423 Driver 20 50 ns VCC = +5.0V, TA @ +25°C RS-423 Receiver 20 ns V.35 Driver 20 50 ns VCC = +5.0V, TA @ +25°C V.35 Receiver 20 ns

7

A

R

V

OD

V

OC

R

Receiver

Output

Test Point

RL

1KΩC

1KΩ

V

S

1

S

2

CC

B

Figure 1. Driver DC Test Load Circuit

C

DI

A B

L1

R

L

C

L2

A

B

Figure 3a. Driver/Receiver Timing Test Circuit

Output

Under

Test

RO

C

L

15pF

Figure 2. Receiver Timing Test Load Circuit

A

DI

B

A B

Figure 3b. Timing Test Ckt. (V.35 mode only for SP504)

V

500Ω

S

1

S

2

CC

RO

15pF

Figure 4. Driver Timing Test Load #2 Circuit

Note : Figures 3a and 3b shown above are used for evaluating maximum transmission rate. For 10Mbps transmission rate, an input signal of 5MHz is applied

to the driver input. In order for a valid transmission rate, the driver output must adhere to the output electrical specifications (VOH & VOL) and an acceptable duty cycle for the protocol tested. The receiver outputs are checked for proper TTL/CMOS VOH & VOL levels and an acceptable output duty cycle.

8

+3V

DRIVER INPUT

0V

A

DRIVER

OUTPUT

DIFFERENTIAL

OUTPUT

V

– V

A

Figure 5. Driver Propagation Delays

B

+

V

O

0V

–

V

O

B

f = 1MHz; tR < 10ns; tF < 10ns

1.5V 1.5V t

PLH

1/2V

V

O

t

SKEW

t

F

t

PHL

1/2V

t

SKEW

t

R

O

+3V

TDEC

X

1.5V 1.5V

0V 5V

A, B

V

OL

V

OH

2.3V

0V

Figure 6. Driver Enable and Disable Times

+

V

OD2

A – B

–

V

OD2

V

OH

RECEIVER OUT

V

OL

t

PHL

f = 1MHz; tR < 10ns; tF < 10ns

t

ZL

Output normally LOW

Output normally HIGH

t

ZH

f = 1MHz; tR ≤ 10ns; tF ≤ 10ns

0V 0V

1.5V 1.5V

INPUT

OUTPUT

t

PLH

0.5V

t

LZ

t

HZ

Figure 7. Receiver Propagation Delays

Note : Figures 5 and 7 shown above are corrected from the original SP504 datahseet. Both figures were incorrect on the original datasheet where the

driver output from Figure 5 and the receiver output from Figure 7 are inverted signals.

9

+3V

RDEC

X

0V 5V

RECEIVER OUT

V

IL

V

IH

RECEIVER OUT

0V

Figure 8. Receiver Enable and Disable Times

DRIVER INPUT

1.5V 1.5V

f = 1MHz; tR < 10ns; tF < 10ns

t

ZL

1.5V

Output normally LOW

Output normally HIGH

t

ZH

- 0V

DRIVER INPUT

- 0V

0.5V

t

LZ

t

HZ

- 0V

DRIVER OUTPUT

Figure 9. Typical RS-232 Driver Output Waveform

- 0V

DRIVER INPUT

- 0V

DRIVER OUTPUT

Figure 11. Typical RS-422/485 Driver Output Waveform Figure 12. Typical V.35 Driver Output Waveform

DRIVER OUTPUT

Figure 10. Typical RS-423 Driver Output Waveform

DRIVER INPUT

- 0V

DRIVER OUTPUT

- 0V

10

PINOUT…

RxD 1

RDEC

2

0

RDEC

3

1

4

RDEC

2

RDEC

5

3

TTEN 6

SCTEN 7

N/C 8

9

TDEC

3

TDEC

10

2

TDEC

11

1

12

TDEC

0

DTR 13

TxD 14 TxC 15 RTS 16

RL 17

V35_STAT 18

DCD 19

RxC 20

80 CTS

RI 21

79 SCT

ST 22

78 DSR

77 SCT(b)

LL 24

STEN 23

76 SCT(a)

25

+

CC

V

75 GND

74 VCC73 VCC72 GND

71 RD(b)

70 RD(a)

SP504

30

31

26

28

27

–

+

1

2

1

2

DD

C

V

GND 29

69 DM(b)

68 DM(a)

33

32

SS

CC

V

67 CS(b)

GND 34

66 CS(a)

65 TT(b)

RR(a) 35

RR(b) 36

64 GND

63 TT(a)

RT(a) 37

RT(b) 38

62 VCC61 SD(a)

IC(a) 39

IC(b) 40

60 GND 59 SD(b) 58 TR(a) 57 GND 56 TR(b) 55 V 54 RS(a) 53 GND 52 RS(b) 51 LL(a) 50 GND 49 LL(b) 48 V 47 RL(a) 46 GND 45 RL(b) 44 ST(b) 43 GND 42 ST(a) 41 V

Pin 61 — SD(a) — Analog Out — Send data, inverted; sourced from TxD.

Pin 63 — TT(a) — Analog Out — Terminal Timing, inverted; sourced from TxC

Pin 65 — TT(b) — Analog Out — Terminal Timing, non–inverted; sourced from TxC.

CC

Pin 70 — RD(a) — Receive Data, analog input; inverted; source for RxD.

Pin 71 — RD(b) — Receive Data; analog input;

CC

non-inverted; source for RxD. Pin 76 — SCT(a) — Serial Clock Transmit;

analog input, inverted; source for SCT.

CC

Pin 77 — SCT(b) — Serial Clock Transmit: analog input, non–inverted; source for SCT

Pin 79 — SCT — Serial Clock Transmit; TTL output; sources from SCT(a) and SCT(b) inputs.

PIN ASSIGNMENTS… CLOCK AND DATA GROUP

Pin 1 — RxD — Receive Data; TTL output, sourced from RD(a) and RD(b) inputs.

Pin 14 — TxD — TTL input ; transmit data source for SD(a) and SD(b) outputs.

Pin 15 — TxC — Transmit Clock; TTL input for TT driver outputs.

Pin 20 — RxC — Receive Clock; TTL output sourced from RT(a) and RT(b) inputs.

Pin 22 — ST — Send Timing; TTL input; source for ST(a) and ST(b) outputs.

Pin 37 — RT(a) — Receive Timing; analog input, inverted; source for RxC.

Pin 38 — RT(b) — Receive Timing; analog input, non-inverted; source for RxC.

Pin 42 — ST(a) — Send Timing; analog output, inverted; sourced from ST.

Pin 44 — ST(b) — Send Timing; analog output, non-inverted; sourced from ST.

Pin 59 — SD(b) — Analog Out — Send data, non-inverted; sourced from TxD.

CONTROL LINE GROUP

Pin 13 — DTR — Data Terminal Ready; TTL input; source for TR(a) and TR(b) outputs.

Pin 16 — RTS — Ready To Send; TTL input; source for RS(a) and RS(b) outputs.

Pin 17 — RL — Remote Loopback; TTL input; source for RL(a) and RL(b) outputs.

Pin 18 — V35_STAT — V.35 Status; TTL output; outputs logic high when in V.35 mode.

Pin 19 — DCD— Data Carrier Detect; TTL output; sourced from RR(a) and RR(b) inputs.

Pin 21 — RI — Ring Indicate; TTL output; sourced from IC(a) and IC(b) inputs.

Pin 24 — LL — Local Loopback; TTL input; source for LL(a) and LL(b) outputs.

Pin 35 — RR(a)— Receiver Ready; analog input, inverted; source for DCD.

Pin 36 — RR(b)— Receiver Ready; analog input, non-inverted; source for DCD.

Pin 39 — IC(a)— Incoming Call; analog input, inverted; source for RI.

11

Pin 40 — IC(b)— Incoming Call; analog input,non-inverted; source for RI.

Pin 45 — RL(b) — Remote Loopback; analog output, non-inverted; sourced from RL.

Pin 47 — RL(a) — Remote Loopback; analog output inverted; sourced from RL.

Pins 12–9 — TDEC0 – TDEC3 — Transmitter decode register; configures transmitter modes; TTL inputs.

Pin 23 — STEN — Enables ST driver; active low; TTL input.

Pin 49— LL(b) — Local Loopback; analog output, non-inverted; sourced from LL.

Pin 51 — LL(a) — Local Loopback; analog output, inverted; sourced from LL.

Pin 52 — RS(b) — Ready To Send; analog output, non-inverted; sourced from RTS.

Pin 54 — RS(a) — Ready To Send; analog output, inverted; sourced from RTS.

Pin 56 — TR(b) — Terminal Ready; analog output, non-inverted; sourced from DTR.

Pin 58 — TR(a) — Terminal Ready; analog output, inverted; sourced from DTR.

Pin 66 — CS(a)— Clear To Send; analog input, inverted; source for CTS.

Pin 67 — CS(b)— Clear To Send; analog input, non-inverted; source for CTS.

Pin 68 — DM(a)— Data Mode; analog input, inverted; source for DSR.

Pin 69 — DM(b)— Data Mode; analog input, non-inverted; source for DSR

POWER SUPPLIES

Pins 25, 33, 41, 48, 55, 62, 73, 74 — VCC — +5V input.

Pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75 — GND — Ground.

Pin 27 — VDD +10V Charge Pump Capacitor — Connects from VDD to VCC. Suggested capacitor size is 22µF, 16V.

Pin 32 — VSS –10V Charge Pump Capacitor — Connects from ground to VSS. Suggested capacitor size is 22µF, 16V.

Pins 26 and 30 — C Capacitor — Connects from C

+

1

gested capacitor size is 22µF, 16V. Pins 28 and 31 — C

Capacitor — Connects from C

+

2

gested capacitor size is 22µF, 16V.

and C

–

— Charge Pump

1

+

–

to C

. Sug-

1

–

. Sug-

2

1

–

— Charge Pump

2

+

2

NOTE: NC pins should be left floating; internal signals may be present.

Pin 78 — DSR— Data Set Ready; TTL output; sourced from DM(a), DM(b) inputs.

Pin 80 — CTS— Clear To Send; TTL output; sourced from CS(a) and CS(b) inputs.

CONTROL REGISTERS

Pins 2–5 — RDEC0 – RDEC3 — Receiver decode register; configures receiver modes; TTL inputs.

Pin 6 — TTEN — Enables TT driver, active low; TTL input.

Pin 7 — SCTEN — Enables SCT receiver; active high; TTL input.

12

FEATURES…

The SP504 is a highly integrated serial transceiver that allows software control of its interface modes. Similar to the SP503, the SP504 offers the same hardware interface modes for RS-232 (V.28), RS-422A (V.11), RS-449, RS485, V.35, EIA-530 and includes V.36 and EIA-530A. The interface mode selection is done via an 8–bit switch; four (4) bits control the drivers and four (4) bits control the receivers. The SP504 is fabricated using low power BiCMOS process technology, and incorporates a Sipex patented (5,306,954) charge pump allowing +5V only operation. Each device is packaged in an 80–pin JEDEC Quad FlatPack package.

The SP504 is ideally suited for wide area network connectivity based on the interface modes offered and the driver and receiver configurations. The SP504 has seven (7) independent drivers and seven (7) independent receivers. In V.35 mode, the SP504 includes the necessary components and termination resistors internal within the device for compliant V.35 operation.

THEORY OF OPERATION

The SP504 is made up of five separate circuit blocks — the charge pump, drivers, receivers, decoder and switching array. Each of these circuit blocks is described in more detail below.

Charge–Pump

The SP504's charge pump design is based on the SP503 where Sipex's patented charge pump design (5,306,954) uses a four–phase voltage shifting technique to attain symmetrical ±10V power supplies. In addition, the SP504 charge pump incorporates a "programmable" feature that produces an output of ±10V or ±5V for V and VDD depending on the mode of operation.

SS

The charge pump still requires external capacitors to store the charge. Figure 17a shows the waveform found on the positive side of capacitor C2, and Figure 17b shows the negative side of capcitor C2. There is a free–running oscillator that controls the four phases of the voltage shifting. A description of each phase follows.

The SP504 charge pump is used for RS-232 where the output voltage swing is typically ±10V and also used for RS-423. However, RS-

423 requires the voltage swing on the driver output be between ±4V to ±6V during an open circuit (no load). The charge pump would need to be regulated down from ±10V to ±5V. A typical ±10V charge pump would require exter- nal clamping such as 5V zener diodes on V and VSS to ground. The ±5V output has sym-

DD

metrical levels as in the ±10V output. The ±5V is used in the following modes where RS-423 levels are used: RS-449, EIA-530, EIA-530A and V.36.

Phase 1 (±10V)

— VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to +5V. The C is then switched to ground and the charge on C is transferred to C +5V, the voltage potential across capacitor C2 is

–

. Since C

2

+

is connected to

2

now 10V.

Phase 1 (±5V)

— VSS & VDD charge storage and transfer — With the C1 and C2 capacitors initially charged to +5V, C charge on C capacitor. Simultaneously the C ground and the 5V charge on C to the VDD storage capacitor.

Figure 13a. Charge Pump Phase 1 for ±10V.

Figure 13b. Charge Pump Phase 1 for ±5V.

+

is then switched to ground and the

l

–

is transferred to the VSS storage

1

VCC = +5V

++

C

1

–5V

VCC = +5V

++

C

1

–5V

+5V

C

2

––

–5V

+5V

C

2

––

–

is switched to

2

+

is transferred

2

C

4

+

–

V

Storage Capacitor

DD

+

–

V

Storage Capacitor

SS

C

3

C

4

+

–

Storage Capacitor

V

DD

+

–

V

Storage Capacitor

SS

C

3

+

l

–

1

13

VCC = +5V

++

C

1

C

–10V

2

––

C

4

+

–

V

DD

+

–

V

SS

C

3

Storage Capacitor

VCC = +5V

++

C

1

C

2

––

–5V

C

4

+

–

V

DD

+

–

V

SS

C

3

Storage Capacitor

Figure 14a. Charge Pump Phase 2 for ±10V.

VCC = +5V

++

C

1

–5V

+5V

C

2

––

–5V

C

4

+

–

V

DD

+

–

V

SS

C

3

Storage Capacitor

Figure 15. Charge Pump Phase 3.

Phase 2 (±10V)

— VSS transfer — Phase two of the clock connects the negative terminal of C2 to the V storage capacitor and the positive terminal of C

SS

to ground, and transfers the generated –l0V or the generated –5V to C3. Simultaneously, the positive side of capacitor C 1 is switched to +5V and the negative side is connected to ground.

Phase 2 (±5V)

— VSS & VDD charge storage — C nected to VCC to recharge the C1 capacitor. C is switched to ground and C The 5V charge from Phase 1 is now transferred

–

is connected to C3.

2

+

is recon-

1

Figure 14b. Charge Pump Phase 2 for ±5V.

VCC = +5V

++

C

1

+10V

C

2

––

C

4

+

–

V

DD

+

–

V

SS

C

3

Storage Capacitor

Figure 16. Charge Pump Phase 4.

to the VSS storage capacitor. VSS receives a continuous charge from either C1 or C2. With the C1 capacitor charged to 5V, the cycle begins again.

2

Phase 3

— VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1 produces –5V in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C

+

2

voltage potential across C2 is l0V. For the 5V output, C potential on C2 is only +5V.

+

is connected to ground so that the

2

+

is at +5V, the

2

+10V

C

2

+

(a)

+5V

C

2

GND

C

2

–

(b)

GND

C

2

–5V

–10V

Figure 17. Charge Pump Waveforms

14

+

–

Since both VDD and VSS are separately generated from VCC in a no–load condition, VDD and VSS will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design.

The clock rate for the charge pump typically operates at 15kHz. The external capacitors must be a minimum of 22µF with a 16V breakdown rating.

External Power Supplies

For applications that do not require +5V only, external supplies can be applied at the V+ and V– pins. The value of the external supply voltages must be no greater than ±l0.5V. The tolerance should be ±5% from ±10V. The current drain for the supplies is used for RS-232 and RS-423 drivers. For the RS-232 driver, the current requirement will be 3.5mA per driver. The RS-423 driver worst case current drain will be 11mA per driver. Power sequencing is required for the SP504. The supplies must be sequenced accordingly: +10V, +5V and –10V. An external circuit would be needed for proper power supply sequencing. Consult factory for application circuitry.

Drivers

The SP504 has seven (7) enhanced independent drivers. Control for the mode selection is done via a four–bit control word. The drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accommodate the selected interface mode. As the mode of the drivers is changed, the electrical characteristics will change to support the requirements of clock, data, and control line signal levels. Table 1 shows the mode of each driver in the different interface modes that can be selected.

There are four basic types of driver circuits — RS-232, RS-423, RS-485 and V.35.

The RS-232 drivers output single–ended signals with a minimum of ±5V (with 3kΩ and 2500pF loading), and can operate up to 120kbps.

The RS-232 drivers are used in RS-232 mode for all signals, and also in V.35 mode where they are used as the control line signals such as DTR and RTS.

The RS-423 drivers are also single–ended signals with a minimum voltage output of ±3.6V (with 450Ω loading) and can operate up to 120kbps. Open circuit VOL and VOH measurements are ±4.0V to ±6.0V. The RS-423 drivers are used in RS-449, EIA-530, EIA-530A and V.36 modes as Category II signals from each of their corresponding specifications.

The third type of driver produces a differential signal that can maintain RS-485, ±1.5V differential output levels with a worst case load of 54Ω. The signal levels and drive capability of the RS-485 drivers allow the drivers to also support RS-422 (V.11) requirements of ±2V differential output levels with 100Ω loads. The RS-422 drivers are used in RS-449, EIA-530, EIA-530A and V.36 modes as Category I signals which are used for clock and data.

The fourth type of driver is the V.35 driver. V.35 levels require ±0.55V driver output signals with a load of 100Ω. The SP504 drivers simplify existing V.35 implementations that use external termination schemes. The drivers were specifically designed to comply with the requirements of V.35 as well as the driver output impedance values of V.35. The drivers achieve the 50Ω to 150Ω source impedance. However, an external 150Ω resistor to ground must be connected to the non-inverting outputs; SD(b), ST(b), and TT(b), in order to comply with the 135Ω to 165Ω short-circuit impedance for V.35. The V.35 driver itself is disabled and transparent when the decoder is in all other modes. All of the differential drivers; RS-485, RS-422, and V.35, can operate up to 10Mbps.

The driver inputs are both TTL or CMOS compatible. Since there are no pull-up or pull-down resistors on the driver inputs, they should be tied to a known logic state in order to define the driver output.

15

Receivers

The SP504 has seven (7) independent receivers which can be programmed for the different interface modes. Control for the mode selection is done via a 4–bit control word that is independent from the driver control word. The coding for the drivers and receivers is identical. Therefore, if the modes for the drivers and receivers are supposed to be identical in the application, the control lines can be tied together.

Like the drivers, the receivers are pre-arranged for the specific requirements of the interface. As the operating mode of the receivers is changed, the electrical characteristics will change to support the requirements of clock, data, and control line receivers. Table 2 shows the mode of each receiver in the different interface modes that can be selected.

There are three basic types of receiver circuits — RS-232, RS-423, and RS-485.

The RS-232 receiver is a single–ended input with a threshold of 0.8V to 2.4V. The RS-232 receiver has an operating voltage range of ±15V and can receive signals up to 120kbps. The input sensitivity complies with EIA-RS-232 and V.28 at +3V to -3V. The input impedance is 3kΩ to 7kΩ. RS-232 receivers are used in RS232 mode for all data, clock and control signals. They are also used in V.35 mode for control line signals such as CTS and DSR.

The RS-423 receivers are also single–ended but have an input threshold as low as ±200mV. The input impedance is guaranteed to be greater than 4kΩ, with an operating voltage range of ±7V. The RS-423 receivers can operate up to 120kbps. RS-423 receivers are used in RS-449, EIA-530, EIA-530A and V.36 modes as Category II signals as indicated by their corresponding specifications.

The third type of receiver is a differential which supports RS-485. The RS-485 receiver has an input impedance of 15kΩ and a differential threshold of ±200mV. Since the characteristics of an RS-422 (V.11) receiver are actually subsets of RS-485, the receivers for RS-422 requirements are covered by the RS-485 receivers.

RS-422 receivers are used in RS-449, EIA-530, EIA-530A and V.36 as Category I signals for receiving clock, data, and some control line signals. The differential receivers can receive data up to 10Mbps.

The RS-485 receivers are also used for the V.35 mode. Unlike the older implementations of differential or V.35 receivers, the SP504 contains an internal resistor termination network that ensures a V.35 input impedance of 100Ω (±10Ω) and a short-circuit impedance of 150Ω (±15Ω). The traditional V.35 implementations required external termination resistors to acheive the proper V.35 impedances. The internal network is connected via low on-resistance FET switches when the decoder is changed to V.35 mode. The termination network is transparent when all other modes are selected. The V.35 receivers can operate up to 10Mbps.

All receivers include a fail-safe feature that outputs a logic HIGH when the receiver inputs are open. For single-ended RS-232 receivers, there are internal 5kΩ pull-down resistors on the inputs which produces a logic HIGH ("1") at the receiver outputs. The single-ended RS-423 receivers produce a logic LOW ("0") on the output when the inputs are open. This is due to a pullup device connected to the input. The differential receivers have the same internal pull-up device on the non-inverting input which produces a logic HIGH ("1") at the receiver output. The three differential receivers when configured in V.35 mode (RxD, RxC & SCT) do not have fail-safe because the internal termination resistor network is connected.

Decoder

The SP504 has the ability to change the interface mode of the drivers or receivers via an 8–bit switch. The decoder for the drivers and receivers is not latched; it is merely a combinational logic switch.

The control word can be externally latched either HIGH or LOW to write the appropriate code into the SP504. The codes shown in Tables 1 and 2 are the only specified, valid modes for the SP504. Undefined codes may represent other interface modes not specified (consult the fac-

16

tory for more information). The drivers are controlled with the data bits labeled TDEC3– TDEC0. All of the drivers can be put into tristate mode by writing 0000 to the driver decode switch. The three drivers TxD, ST and TxC, have a 150Ω pull-down resistor to ground connected at the (b) output. This resistor is part of the V.35 driver circuitry and should be connected when in V.35 mode. Tri-state is possible for all drivers in RS-232 mode. The receivers are controlled with data bits RDEC3–RDEC0; the code 0000 written to the receivers will place the outputs into tri-state mode. The 0000 decoder word will override the enable control line for the one receiver (SCT).

Using the V.35_STAT Pin

The SP504 includes a V.35 status pin where the V35_STAT pin (pin 18) is a logic HIGH ("1") when the decoder is set to V.35 mode. The pin is a logic LOW ("0") when in all other modes including tri-state (decoder set at "0000"). Pin 18 allows the user to easily add FET switches or solid state relays to connect the external 150Ω resistor for V.35 operation. V35_STAT can be connected to the gate of the FET switches or the control of the relays so that the 150Ω resistors are connected to the non-inverting output of the three V.35 drivers. The output current of the V35_STAT pin is that of a typical TTL load of –3.2mA. The electrical specifications are similar to the SP504 receiver outputs. This feature would reduce additional logic required by older traditional methods.

NET1/NET2 Testing and Compliancy

Many system designers are required to certify their system for use in the European public network. Electrical testing is performed in adherence to the NET (Norme Européenne de Télécommunication) which specifies the ITU Series V specifications. The SP504 adheres to all the required physical layer testing for NET1 and NET2. Consult factory for details.

17

SP504 Driver Mode Selection

Pin Label Mode: RS232 V.35 RS422 RS485 RS449 EIA530 EIA-530A

TDEC –TDEC

30

SD(a) tri-state SD(b) TR(a) tri-state TR(b) tri-state tri-state tri-state RS(a) tri-state RS(b) tri-state tri-state tri-state RL(a) tri-state RL(b) tri-state LL(a) tri-state LL(b) tri-state ST(a) tri-state ST(b) TT(a) tri-state TT(b)

Table 1. Driver Mode Selection

0000 0010 1110 0100

tri-state

V.28

tri-state

V.28

V.28 V.11–

V.28

tri-state

V.28

tri-state

V.28

tri-state

V.28

tri-state

V.35– V.35+

V.28

tri-state

V.28

tri-state

V.35– V.35+ V.35– V.35+

V.11– V.11+ V.11– V.11+

V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+

0101

RS485– RS485+ RS485– RS485+ RS485– RS485+ RS485– V.10 RS485+ RS485– RS485+ RS485– RS485+ V.11+ RS485– RS485+

1100 1101 1111

V.11– V.11+ V.11– V.11+ tri-state V.11– V.11+

tri-state

V.10

tri-state

V.11–

V.11– V.11+

V.11– V.11+ V.11– V.11+ V.11– V.11+

V.10

tri-state

V.10

tri-state

V.11– V.11+ V.11– V.11+

V.11– V.11+

V.11– V.11+ V.11– V.11+

tri-state

V.11– V.11+ V.11– V.11+

SP504 Receiver Mode Selection

Pin Label RDEC

–RDEC

3

RD(a) RD(b) RT(a) RT(b) CS(a) CS(b) DM(a) DM(b) RR(a) RR(b) IC(a)

IC(b) SCT(a) SCT(b)

Table 2. Receiver Mode Selection

Mode: RS232 V.35 RS422 RS485 RS449 EIA530 EIA-530A

0000 0010 1110 0100 0101 1100 1101 1111

0

>12kΩ to GND >12kΩ to GND >12kΩ to GND >12kΩ to GND

>12kΩ to GND >12kΩ to GND >12kΩ to GND >12kΩ to GND >12kΩ to GND >12kΩ to GND >12kΩ to GND >12kΩ to GND >12kΩ to GND >12kΩ to GND

V.28

>12kΩ to GND

V.28

>12kΩ to GND

V.28 V.11–

>12kΩ to GND

V.28

>12kΩ to GND

V.28

>12kΩ to GND

V.28

>12kΩ to GND

V.28

>12kΩ to GND

V.35–

V.35+ V.35–

V.35+

V.28

>12kΩ to GND

V.28

>12kΩ to GND

V.28

>12kΩ to GND

V.28

>12kΩ to GND

V.35–

V.35+

V.11– V.11+ V.11– V.11+

V.11+ V.11– V.11+ V.11– V.11+

V.11– V.11+

RS485– RS485+ RS485– RS485+ RS485– RS485+ RS485– RS485+ RS485– RS485+ RS485– RS485+ RS485– RS485+

V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+

V.10

>12kΩ to GND >12kΩ to GND

V.11– V.11+

V.11– V.11+ V.11– V.11+ V.11–

V.11+ V.11– V.11+ V.11– V.11+

V.10

V.11–

V.11+

>12kΩ to GND

V.10

V.11– V.11+

V.11– V.11+ V.11– V.11+

V.10

V.11– V.11+

V.10

V.11– V.11+

V.36

0110

V.11– V.11+

V.10

tri-state

V.10

tri-state

V.10

tri-state

V.10

tri-state

V.11–

V.11+ V.11– V.11+

V.36

0110

V.11– V.11+

V.11– V.11+ V.10

>12kΩ to GND

V.10

>12kΩ to GND

V.10

>12kΩ to GND

V.10

>12kΩ to GND

V.11– V.11+

18

+5V

A — Receiver Tri-State circuitry & V.35

termination resistor circuitry for RxD, RxC & SCT.

B — Driver Tri-State circuitry & V.35

termination circuitry for TxD, TxC & ST.

RS-422 Mode Input Word

0 1 0 0 0

External Latch

1 0 0

10µF

RD(a) 70

RxD 1

RD(b) 71 RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78

DM (b) 69

RR(a) 35

DCD 19

RR(b) 36

IC(a) 39

RI 21

IC(b) 40

SCT(a) 76

SCT 79

SCTEN 7 SCT(b) 77

1N5819

25 26

V

CCVDD

5

4

3

RDEC

2

9 10 11

TDEC

12

22µF

27

Charge Pump

A

X

22µF

C1+

C1-

2830

C2+

22µF

31

C2-

V

SS

32

B

14 TxD 61 SD(a) 59 SD(b)

13 DTR 58 TR(a) 56 TR(b)

16 RTS 54 RS(a) 52 RS(b)

17 RL 47 RL(a) 45 RL(b)

24 LL 51 LL(a) 49 LL(b)

22 ST 42 ST(a) 44 ST(b) 23 STEN

15 TxC 63 TT(a) 65 TT(b) 6 TTEN

SP504

(SEE PAGE 12 FOR GROUND PINS)

22µF

150Ω

①

150Ω

①

150Ω

①

☛ For V.35 Termination, needs to be connected

for proper V.35 operation. A low onresistance (≤1Ω) FET or switch can be used to connect and disconnect the resistor from the non-inverting output.

Figure 18. Typical Operation Circuit

19

MODE: RS-232

DRIVER RECEIVER

TDEC

TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC

3

0 0 1 0 0 0 1 0

0

RD(a) 70

RxD 1

RT(a) 37

RxC 20

CS(a) 66

CTS 80

DM(a) 68

DSR 78

RR(a) 35

DCD 19

IC(a) 39

RI 21

SCT(a) 76

SCT 79

SCTEN 7

14 TxD 61 SD(a)

13 DTR 58 TR(a)

16 RTS 54 RS(a)

17 RL 47 RL(a)

24 LL 51 LL(a)

22 ST 42 ST(a) 23 STEN 15 TxC 63 TT(a) 6 TTEN

RECEIVERS DRIVERS

STEN ST TTEN TT SCTEN SCT 1 Disabled 1 Disabled 1 Enabled 0 Enabled 0 Enabled 0 Disabled

Figure 19. Mode Diagram — RS-232

20

MODE: V.35

DRIVER RECEIVER

TDEC

TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC

3

1 1 1 0 1 1 1 0

0

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

DM(a) 68

DSR 78

RR(a) 35

DCD 19

IC(a) 39

RI 21

SCT(a) 76

SCT 79

SCTEN 7 SCT(b) 77

14 TxD 61 SD(a) 59 SD(b)

13 DTR 58 TR(a)

16 RTS 54 RS(a)

17 RL 47 RL(a)

24 LL 51 LL(a) 22 ST

42 ST(a) 44 ST(b) 23 STEN

15 TxC 63 TT(a) 65 TT(b) 6 TTEN

RECEIVERS DRIVERS

STEN ST TTEN TT SCTEN SCT 1 Disabled 1 Disabled 1 Enabled 0 Enabled 0 Enabled 0 Disabled

Figure 20. Mode Diagram — V.35

21

MODE: RS-422

DRIVER RECEIVER

TDEC

TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC

3

0 1 0 0 0 1 0 0

0

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38 CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78

DM (b) 69

RR(a) 35

DCD 19

RR(b) 36

IC(a) 39

RI 21

IC(b) 40

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

14 TxD 61 SD(a) 59 SD(b)

13 DTR 58 TR(a) 56 TR(b)

16 RTS 54 RS(a) 52 RS(b)

17 RL 47 RL(a) 45 RL(b)

24 LL 51 LL(a) 49 LL(b)

22 ST 42 ST(a) 44 ST(b) 23 STEN

15 TxC 63 TT(a) 65 TT(b) 6 TTEN

RECEIVERS DRIVERS

STEN ST TTEN TT SCTEN SCT 1 Disabled 1 Disabled 1 Enabled 0 Enabled 0 Enabled 0 Disabled

Figure 21. Mode Diagram — RS-422

22

MODE: RS-449

DRIVER RECEIVER

TDEC

TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC

3

1 1 0 0 1 1 0 0

0

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78

DM (b) 69

RR(a) 35

DCD 19

RR(b) 36

IC(a) 39

RI 21

14 TxD 61 SD(a) 59 SD(b)

13 DTR 58 TR(a) 56 TR(b)

16 RTS 54 RS(a) 52 RS(b)

17 RL

47 RL(a)

24 LL

51 LL(a)

22 ST 42 ST(a) 44 ST(b) 23 STEN

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

15 TxC 63 TT(a) 65 TT(b) 6 TTEN

RECEIVERS DRIVERS

STEN ST TTEN TT SCTEN SCT 1 Disabled 1 Disabled 1 Enabled 0 Enabled 0 Enabled 0 Disabled

Figure 22. Mode Diagram — RS-449

23

MODE: RS-485

DRIVER RECEIVER

TDEC

TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC

3

0 1 0 1 0 1 0 1

0

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38 CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78

DM (b) 69

RR(a) 35

DCD 19

RR(b) 36

IC(a) 39

RI 21

IC(b) 40

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

14 TxD 61 SD(a) 59 SD(b)

13 DTR 58 TR(a) 56 TR(b)

16 RTS 54 RS(a) 52 RS(b)

17 RL 47 RL(a) 45 RL(b)

24 LL 51 LL(a) 49 LL(b)

22 ST 42 ST(a) 44 ST(b) 23 STEN

15 TxC 63 TT(a) 65 TT(b) 6 TTEN

RECEIVERS DRIVERS

STEN ST TTEN TT SCTEN SCT 1 Disabled 1 Disabled 1 Enabled 0 Enabled 0 Enabled 0 Disabled

Figure 23. Mode Diagram — RS-485

24

MODE: EIA-530

DRIVER RECEIVER

TDEC

TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC

3

1 1 0 1 1 1 0 1

0

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78

DM (b) 69

RR(a) 35

DCD 19

RR(b) 36

IC(a) 39

RI 21

14 TxD 61 SD(a) 59 SD(b)

13 DTR 58 TR(a) 56 TR(b)

16 RTS 54 RS(a) 52 RS(b)

17 RL

47 RL(a)

24 LL

51 LL(a)

22 ST 42 ST(a) 44 ST(b) 23 STEN

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

15 TxC 63 TT(a) 65 TT(b) 6 TTEN

RECEIVERS DRIVERS

STEN ST TTEN TT SCTEN SCT 1 Disabled 1 Disabled 1 Enabled 0 Enabled 0 Enabled 0 Disabled

Figure 24. Mode Diagram — EIA-530

25

MODE: EIA-530A

DRIVER RECEIVER

TDEC

TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC

3

1 1 1 1 1 1 1 1

0

RD(a) 70

RxD 1

RD(b) 71 RT(a) 37

RxC 20

RT(b) 38 CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78

RR(a) 35

DCD 19

RR(b) 36

IC(a) 39

RI 21

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

14 TxD 61 SD(a) 59 SD(b) 13 DTR

58 TR(a)

16 RTS

54 RS(a)

52 RS(b)

17 RL

47 RL(a)

45 RL(b) 24 LL

51 LL(a) 22 ST

42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN

RECEIVERS DRIVERS

STEN ST TTEN TT SCTEN SCT

1 Disabled 1 Disabled 1 •Enabled

1 Disabled 1 Disabled 1 Enabled

0 Enabled 0 Enabled 0 •Disabled

0 Enabled 0 Enabled 0 Disabled

Figure 25. Mode Diagram — EIA-530A

26

MODE: V.36

DRIVER RECEIVER

TDEC

TDEC2 TDEC1 TDEC0 RDEC3 RDEC2 RDEC1 RDEC

3

0 1 1 0 0 1 1 0

0

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

DM(a) 68

DSR 78

RR(a) 35

DCD 19 IC(a) 39

RI 21

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

14 TxD 61 SD(a) 59 SD(b)

13 DTR 58 TR(a)

16 RTS 54 RS(a)

17 RL 47 RL(a)

24 LL 51 LL(a) 22 ST

42 ST(a) 44 ST(b) 23 STEN

15 TxC 63 TT(a) 65 TT(b) 6 TTEN

RECEIVERS DRIVERS

STEN ST TTEN TT SCTEN SCT

STEN ST TTEN TT SCTEN SCT 1 Disabled 1 Disabled 1 •Enabled

1 Disabled 1 Disabled 1 Enabled

0 Enabled 0 Enabled 0 •Disabled

0 Enabled 0 Enabled 0 Disabled

Figure 26. Mode Diagram — V.36

27

ADDITIONAL TRANSCEIVERS WITH THE SP504

Serial ports usually can have two data signals (SD, RD), three clock signals (TT, ST, RT), and

at least eight control signals (CS, RS, etc.). EIARS-449 contains twenty six signal types for a DB-37 connector. A DB-37 serial port design may require thirteen drivers and fourteen receivers1. Although many applications do not use all these signals, some applications may need to support extra functions such as diagnostics. The SP504 supports enough transceivers for the primary channels of data, clock and control signals. Configuring LL, RL and TM would require two additional drivers and one receiver if designing for a DTE (one driver and two receivers for a DCE).

A programmable transceiver such as the SP332 is a convenient solution in a design that requires extra single ended or differential drivers/receivers. As shown in Figure 28, the SP332 can be configured to four different variations.

The SP332 in Figure 29 is configured for two single-ended drivers and one diffferential receiver. For a DTE design, the two drivers are used for LL and RL signals and the receiver is used for the TM signal. This configuration was selected because the two RS-232 drivers can be

used for RS-423 by connecting a zener clamping diode to ground on the two driver outputs. The diodes will limit the voltage swing on the outputs so that the VOC = ±4V to ±6V adheres to the RS-423 specification. The differential receiver can be easily configured to RS-423 by grounding the non-inverting input. The receiver will adhere to the RS-423 specifications.

CIRCUIT CIRCUIT NAME CIRCUIT CIRCUIT

MNEMONIC DIRECTION TYPE

SG SIGNAL GROUND -------------SC SEND COMMON TO DCE

RC RECEIVE COMMON FROM DCE IS TERMINAL IN SERVICE TO DCE IC INCOMING CALL FROM DCE TR TERMINAL READY TO DCE DM DATA MODE FROM DCE SD SEND DATA TO DCE RD RECEIVE DATA FROM DCE TT TERMINAL TIMING TO DCE ST SEND TIMING FROM DCE RT RECEIVE TIMING FROM DCE RS REQUEST TO SEND TO DCE CS CLEAR TO SEND FROM DCE RR RECEIVER READY FROM DCE SQ SIGNAL QUALITY FROM DCE NS NEW SIGNAL TO DCE SF SELECT FREQUENCY TO DCE SR SIGNAL RATE SELECTOR TO DCE SI SIGNAL RATE INDICATOR FROM DCE SSD SECONDARY SEND DATA TO DCE SRD SECONDARY RD FROM DCE SRS SECONDARY RS TO DCE SCS SECONDARY CS FROM DCE SRR SECONDARY RR FROM DCE LL LOCAL LOOPBACK TO DCE RL REMOTE LOOPBACK TO DCE TM TEST MODE FROM DCE SS SELECT STANDBY TO DCE SB STANDBY INDICATOR FROM DCE

1

RS-449 Interchange Circuits Table

COMMON

CONTROL

DATA

TIMING

CONTROL

DATA

CONTROL

CONTROL CONTROL

SECONDARY

PRIMARY CHANNEL

CHANNEL

SEL A 0 0 1 1 SEL B 0 1 0 1 LOOPBACK 1 1 1 1 SHUTDOWN 0 0 0 0

TX1TI1 626

T1

TI2727

RX21620

RX31721

RX41822

TX2

T2

TX3TI3428

T3

TX4TI41

T4

RI1RX1 1519

R1

RI2

R2

RI3

R3

RI4

R4

27

28

3

21 RX3

TI126

TI2 TX2

TI3

RX11519

RX2 RI2 1620

Figure 28. Mode selection for the SP332

TX1 6

T1

T2

T3

R1

R2

R3

RI1

RI4

26

TI1

7

4TX3

3TX4

17RI3 18

T1

TI3428

T3

TI41

T4

RX1

19

R1

RX3

21

R3

RX41822

R4

TX3

TX4

RI3

RI4

6TX1

26

TI1

28

TI3

19

RX1

21 RX3

T1

T3

R1

R3

7TX2

3

15RI1 16RI2

17

6TX1 7TX2

4TX3 3TX4

15RI1 16RI2

17RI3 18RI4

28

"1100" for RS-449 mode

+5V

10µF

Drivers

Receivers

TDEC3—TDEC0 (pins 9-12)

RDEC3—RDEC0 (pins 5-2)

1N5819

22µF

25 27 26 30 28 31

VCCV

TxD

14

DTR

13

RTS

16

TxC

15

ST

22

RL

17 LL

24

RxD

1

RxC

20

CTS

80

DSR

78

DCD

19 RI

21

SCT

79

22µF22µF

DD

C1+ C2+

SP504CF

C1-

32

V

SS

C2-

61 59 58 56 54 52 63 65 42 44 47 45 51 49 70 71

37 38

66 67

68 69

35 36

39 40

76 77

see pinout diagram for various ground pins

22µF

DB-37 Connector

4 22

12 30 7 25 17 35

16

34

6 24 8 26

9 27 11 29

13

31

15

5

23

Note: The SP332 will require clamping diodes on the driver outputs to limit the voltage to ±6V and comply with the RS-423 driver output specification of VOC = ±4V to ±6V and V

≥ ±3.6V with a 450Ω load.

OUT

+5V

9

0.1µF

0 1

C1+

12

C1-

11

C2+

13

C2-

26

27

28

19

20

21

24

SEL A

2

SEL B

SP332

T1 T2 T3

R1 R2

R3

LOOPBACK

5

10

V

+

CC

V

-

0.1µF

14

0.1µF

6

7

3

4

15

16

18

17 23 8

10µF

LL

10

RL

TM

14

18

1

Figure 29. Adding extra differential and single-ended transceivers using the SP332

29

PIN 1

PACKAGE: QUAD FLATPACK

JEDEC "BE-2" OUTLINE

D D1

0.3" RAD. TYP.

0.2" RAD. TYP.

C

L

0.009"/0.015" (0.220/0.380)

C

L

0.02559"/– (0.65/–)

DIMENSIONS in Inches

Minimum/Maximum

(mm)

A

A1

D

D1

E

E1

L

E1

E

AA

Seating

A1

Plane

JEDEC BE-2 Outline

80–PIN

–/0.0925 (–/2.350)

–/0.010

(–/0.250)

0.667/0.687

(16.950/17.450)

0.547/0.555

(13.900/14.100)

0.667/0.687

(16.950/17.450)

0.547/0.555

(13.900/14.100)

0.0255/0.0375 (0.650/0.950)

0°–7°

0.005/0.009" (0.13/0.23)

10°-16°

6°±4°

10°-16°

L

30

TYPICAL PCB LAYOUT FOR THE 80-PIN QFP

0.486"

(12.35mm)

0.094"(2.387mm)

0.650"

(16.51mm)

0.0100" (0.25mm)

0.02559" (0.65mm)

0.01550" (0.40mm)

C

L

C

L

0.0820" (2.08mm)

NOTE: THIS IS A TYPICAL PCB LAYOUT ONLY. PLEASE CHECK YOUR OWN LAYOUT RULES AND

CRITERIA.

31

Model Temperature Range Package Types

ORDERING INFORMATION

SP504MCF........................................................................ 0°C to +70°C ......................................................... 80–pin JEDEC (BE-2 Outline) QFP

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: [email protected]

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

Far East: JAPAN:

Nippon Sipex Corporation Yahagi No. 2 Building 3-5-3 Uchikanda, Chiyoda-ku Tokyo 101, Japan TEL: 011.81.3.3256.0577 FAX: 011.81.3.3256.0621

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