Datasheet SP5669, SP5669KG, SP5669MP1S, SP5669MP1T Datasheet (MITEL)

Ordering Information

SP5669/KG/MP1S (Tubes)
SP5669/KG/MP1T (Tape and reel)

The comparison frequency is obtained either from an
on–chip crystal controlled oscillator, or from an external
source. The oscillator frequency F

ref

or the comparison

frequency F

comp

may be switched to the REF/COMP
output. This feature is ideally suited to providing the
reference frequency for a second synthesiser such as in
a double conversion tuner (see Fig. 8).

The synthesiser is controlled via an I 2 C bus, and
responds to one of four programmable addresses which
are selected by applying a specific voltage to the
‘address’ input. This feature enables two or more
synthesisers to be used in a system.

The device contains four switching ports P0–P3 and a
5–level ADC. The output of the ADC can be read via the
I 2 C
bus.

The device also contains a varactor line disable and
chargepump disable facility.

Features

● Complete 2.7GHz single chip system

● Compatible with UK DTT offset requirements

● Optimised for low phase noise

● Selectable divide by two prescaler

● Selectable reference division ratio

● Selectable reference/comparison frequency output

● Selectable charge pump current

● Four selectable I

2

C bus address

● 5–level ADC

● Pin compatible with the SP5658 3–wire bus

controlled synthesiser and SP5659 I2C bus
synthesiser and SP5659 I2C bus synthesiser
ESD protection; (Normal ESD handling
procedures should be observed)

Applications

● Complete 2.7GHz single chip system

● Optimised for low phase noise

SP5669

2.7GHz I2C Bus Controlled Synthesiser

Preliminary Information

DS4852 - Issue 2.1 May 1999

Description

The SP5669 is a single chip frequency synthesiser
designed for tuning systems up to 2.7GHz and offers
step size compatible with DTT offset requirements.

The RF preamplifier drives a divide by two prescaler
which can be disabled for applications up to 2GHz,
allowing direct interfacing with the programmable
divider so enabling a step size equal to the comparison
frequency. For applications up to 2.7GHz the divide by
two is enabled, giving a step size of twice the
comparison frequency.

2

SP5669

Figure. 1 Pin connections - top view

1161

MP16

CHARGE PUMP

CRYSTAL

REF/COMP

ADDRESS

SDA

SCL
PORT P3
PORT P2

DRIVE
Vee

RF INPUT
RF INPUT
Vcc
ADC
PORT P0
PORT P1

2
3
4
5
6
7
89

10

11

12

13

14

15

RF

1 BIT

17 BIT LA

TCH

4 BIT

LA

TCH

AND

PORT

INTERFACE

I

TRANSCEIVER

CRYSTAL

PUMP

DRIVE

ADDRESS

ADC

SDA
SCL

PORT P3 PORT P2

INPUTS

13

14

4
5
6

11

PROGRAMMABLE

DIVIDER

PUMP

REFERENCE

DIVIDER

PHASE

COMP

2 BIT

OSC 2

1

16

V

EE

15

12

V

CC

987

2/1

13 BIT

COUNT

4 BIT

COUNT

4 BIT

10

PORT P1 PORT P0

16/17

C1, C0

3

REF/COMP

3 BIT

ADC

PE

5 BIT LA

TCH and

MODE CONTROL

LOGIC

(see Fig. 5)

CHARGE

LATCHLATCH

LOCK

DETECT

LATCH

DIVIDE RA

TIO

PRE
AMP

F

L

FPD/2

P0 TEST

CONTROL

POWER ON

DETECT

POR

DISABLE

MODE

CONTROL

C

2

CHARGE

(see Fig. 3)

F

comp

F

ref

F

pd

Figure. 2 Block diagram

3

SP5669

ELECTRICAL CHARACTERISTICS

T amb = –20°C to +80°C, V

CC

= +4.5V to +5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by
either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless
otherwise stated.

Characteristics Pin Value Units Conditions

Min Typ Max

Supply current, I

CC

12 68 85 mA V CC = 5V prescaler enabled, PE = 1
58 73 mAV

CC

= 5V prescaler disabled, PE = 0

RF input voltage 13, 14 40 300 mV rms 300MHz to 2.7GHz Prescaled

enabled, PE = 1, See Fig. 7b.

13, 14100 300 mV rms 80MHz Prescaler enabled,

PE=1, See Fig. 7b.

13,14 50 300 mV rms 80MHz to 2.0GHz Prescaler

disabled, PE = 0, See Fig. 7a.
RF input impedance 13, 14 50 Ω Refer to Fig. 13
RF input capacitance 13, 14 2 pF Refer to Fig. 13
SDA, SCL 5, 6

Input High voltage 3 5.5 V
Input Low voltage 0 1.5 V
Input High current 10 µA Input voltage = V

CC

Input Low Current –10 µA Input voltage = V

EE

LeakageCurrent 10 µAV

CC

= V

EE

Input hysteresis 0.8 V
SDA Output voltage 5 0.4 V I sink = 3mA
Charge pump output 1 See Fig. 6, V pin = 2V
current
Charge pump output 1 ± 3 ± 10 nA V pin1 = 2V
leakage
Charge pump drive
output current 16 1 mAV pin16 = 0.7V
Drive output saturation
voltage when disabled 16 350 mV
External reference
input frequency 2 2 20 MHzAC coupled sinewave
External reference
input ampltude 2 200 500 mV p–pAC coupled sinewave
Crystal frequency 2 4 16 MHz
Crystal oscillator drive 2 35 mV p–p
level
Recommended crystal
series resistance 10 200 Ω Applies to 4MHz crystal only.

‘Parallel resonant’ crystal. Figure
quoted is under all conditions

including start up.
Crystal oscillator
negative resistance 2 400 Ω Includes temperature and

process tolerances.
REF/COMP output 3
Voltage 350 mV p–p AC coupled output. Output

enabled,RE=1. See Note 1.

4

SP5669

Electrical Chacteristics (cont.)

T amb = –20°C to 80 °C, V CC =+ 4.5V to + 5.5V. Reference frequency = 4MHz. These characteristics are guaranteed
by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless
otherwise stated.

Characteristics Pin Value Units Conditions

Min Typ Max

Comparison frequency 2 MHz
Equivalent phase noise at
phase detector –148 dBC/Hz 6kHz loop BW, phase comparator

freq 250kHz. Figure measured @
1kHz offset, SSB (within loop
band width).

RF division ratio 240 131071 Prescaler disabled, PE = 0

480 262142 Prescaler enabled, PE = 1
Reference division ratio See Fig. 3
Output ports P0, P1, P2, P3 7,8,9,

10
Sink current 10 mA V port = 0.7V
Leakage current 10 µA V port = 13.2V

ADC input voltage 11 See Table 4, Fig 4
ADC input current 11 ±10 µAV

CC

≥ V input ≥ V

EE

Address input current High 4 1 mA Input voltage =V

CC

Address input current Low 4 –0.5 mA Input voltage =V

EE

Note 1: If the REF/COMP output is not used, the output should be left open circuit or connected to V CC , and disabled by
setting RE=0.

Absolute Maximum Ratings

All voltages are referred to VEE at 0V.

Characteristics Pin Value Units Conditions

Min Max

Supply Voltage, V

CC

12 0.3 7 V
RF input voltage 13,14 2.5 V p–p AC coupled as per application
RF input DC offset 13,14 –0.3 V CC +0.3 V
Port voltage 7–10 –0.3 14 V Port in off state

7–10 –0.3 6 V Port in on state
Total port current 7–10 50 mA
ADC input DC offset 11 –0.3 V CC +0.3 V
REF/COMP output DC offset 3 –0.3 V

CC

+0.3 V

Charge pump DC offset 1 –0.3 V

CC

+0.3 V

Drive DC offset 16 –0.3 V

CC

+0.3 V

Crystal oscillator DC offset 2 –0.3 V

CC

+0.3 V

Address DC offset 4 –0.3 V

CC

+0.3 V
SDA and SCL DC offset 5, 6 –0.3 6V V
Storage temperature –55 +150 °C
Junction temperature +150 °C
MP16 thermal resistance
chip to ambient 111 °C/W
chip to case 41 °C/W
Power consumption at V CC =5.5V 468 mW All ports off, prescaler enabled
ESD protection All 4 kV Mil Std 883 TM 3015

5

SP5669

Functional Description

The SP5669 contains all the elements necessary, with the
exception of a frequency reference, loop filter and external
high voltage transistor, to control a varicap tuned local
oscillator, so forming a complete PLL frequency
synthesised source. The device allows for operation with
a high comparison frequency and is fabricated in high
speed logic, which enables the generation of a loop with
good phase noise performance. The block diagram is
shown in Fig. 2.

The RF input signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider
signals. The output of the preamplifier interfaces with the
17–bit fully programmable divider via a divide–by–two
prescaler. For applications up to 2GHz RF input, the
prescaler may be disabled so eliminating the degradation
in phase noise due to prescaler action. The divider is of
MN+A architecture, where the dual modulus prescaler is
16/17, the A counter is 4–bits, and the M counter is 13–bits.

The output of the programmable divider is fed to the phase
comparator where it is compared in both phase and
frequency domain with the comparison frequency. This
frequency is derived either from the on–board crystal
controlled oscillator or from an external reference source.
In both cases the reference frequency is divided down to
the comparison frequency by the reference divider which
is programmable into 1 of 15 ratios as detailed in Fig. 3.

The output of the phase detector feeds a charge pump and
loop amplifier section, which when used with an external
voltage transistor and loop filter, integrates the current
pulses into the varactor line voltage. By invoking the
device test modes as described in Fig. 5, the varactor drive
output can be disabled so switching the external transistor
’off’ and allowing an external voltage to be written to the
varactor line for tuner alignment purposes. Similarly, the
charge pump may be also disabled to a high impedance
state.

The programmable divider output Fpd/2 can be switched
to port P0 by programming the device into test mode. The
test modes are described in Fig. 5 high

Programming

The SP5669 is controlled by an I 2 C data bus. Data
and Clock are fed in on the SDA and SCL lines
respectively as defined by I2C bus format. The
synthesiser can either accept data (write mode) or
send data (read mode). The LSB of the address byte
(R/W) sets the device into write mode if it is low, and
read mode if it is high. Tables 1 and 2 in Fig. 4 illustrate
the format of the data. The device can be
programmed to respond to several addresses, which
enables the use of more than one synthesiser in an
I2C bus system. Table 3 in Fig.4 shows how the
address is selected by applying a voltage to the
’address’ input. When the device receives a valid
address byte, it pulls the SDA line low during the
acknowledge period, and during following
acknowledge periods after further data bytes are
received. When the device is programmed into read
mode, the controller accepting the data must pull the
SDA line low during all status byte acknowledge
periods to read another status byte. If the controller
fails to pull the SDA line low during this period, the
device generates an internal STOP condition, which
inhibits further reading.

Write Mode

With reference to Table 1, bytes 2 and 3 contain
frequency information bits 2 14 –2 0 inclusive.
Auxillary frequency bits 2 16 –2 15 are in byte 4. For
most frequencies only bytes 2 and 3 will be required.
The remainder of byte 4 and byte 5 control the
prescaler enable, reference divider ratio (see Fig. 3),
charge pump, REF/COMP output (see Fig. 5), output
ports and test modes (see Fig. 5).

After reception and acknowledgement of a correct
address (byte 1), the first bit of the following byte
determines whether the byte is interpreted as a byte
2 or 4, a logic ’0’ indicating byte 2 and a logic ’1’
indicating byte 4. Having interpreted this byte as
either byte 2 or 4 the following data byte will be
interpreted as byte 3 or 5 respectively. Having
received two complete data bytes, additional data
bytes can be entered, where byte interpretation
follows the same procedure, without readdressing
the device. This procedure continues until a STOP
condition is received. The STOP condition can be
generated after any data byte, if however it occurs
during a byte transmission, the previous data is
retained.

6

SP5669

To facilitate smooth fine tuning, the frequency data bytes
are only accepted by the device after all 17 bits of frequency
data have been received, or after the generation of a STOP
condition. Repeatedly sending bytes 2 and 3 only will not
change the frequency. A frequency change occurs when one
of the following data sequences is sent to an addressed
device;

Additional Programmable Features

Prescaler enable

The divide by two prescaler is enabled by setting bit PE
within byte 4 to a logic ’1’. A logic ’0’ disables the
prescaler, directly passing the RF input frequency to the
17–bit programmable counter. Bit PE is a static select
only.

Charge pump current

The charge pump current can be programmed by bits
C1 and C0 within data byte 5, as defined in Fig. 6.

Test mode

The test modes are invoked by setting bits RE=0 and
RTS=1 within the programming data, and are selected
by bits TS2, TS1 and TS0 as shown in Fig. 5. When TS2,
TS1 and TS0 are received, the device retains previously
received P2, P1 and P0 data.

Reference/Comparison frequency output

The reference frequency F ref can be switched to the
REF/COMP output, pin 3, by setting bit RE=1 and
RTS=0 within byte 5. The comparison frequency F
comp can be switched to the REF/COMP output, pin 3,
by setting bit RE=1 and RTS=1 within byte 5. For RE set
to logic ’0’, the output is disabled and set to a high state.
RE and RTS default to logic ’1’ during device power up,
thus enabling the comparison frequency F comp at the
REF/COMP output.

Bytes 2, 3, 4, 5
Bytes 4, 5, 2, 3

or when a STOP condition follows valid data bytes as
follows;

Bytes 2, 3, 4, STOP
Bytes 4, 5, 2 STOP
Bytes 2, 3, STOP
Bytes 2, STOP
Bytes 4, STOP

It should be noted that the device must be initially
addressed with both frequency AND control byte data,
since the control byte contains reference divider
information which must be provided before a chosen
frequency can be synthesised. This implies that after
initial turn on, bytes 2, 3, 4 must be sent followed by a
STOP condition as a minimum requirement.
Alternatively bytes 2, 3, 4, 5 must be sent if port
information is also required.

Read Mode

When the device is in read mode, the status byte read
fromthe device takes the form shown in Table 2, Fig. 4.

Bit 1 (POR) is the power–on reset indicator, and this is
set to a logic ’1’ if the VCC supply to the device has
dropped below 3V (at 25°C), e.g. when the device is
initially turned ON. The POR is reset to ’0’ when the read
sequence is terminated by a STOP command. When
POR is set high (at low VCC), the programmed
information is lost and the output ports are all set to high
impedance.

Bit 2 (FL) indicates whether the device is phase locked,
a logic ’1’ is present if the device is locked, and a logic
’0’ if the device is unlocked.

Bits 6,7 and 8 (A2, A1, A0) combine to give the output
of the ADC. The ADC can be used to feed AFC
information to the microprocessor via the I 2 C bus.

Comparison

frequency with a

R3 R2 R1 R0 Ratio 4MHz external

reference
0 0 0 0 2 2MHz
0001 4 1MHz
0 0 1 0 8 500kHz
0011 16 250kHz
0100 32 125kHz
0101 64 62.5kHz
0100128 31.25kHz
0111 256 15.625kHz
1 0 0 0 Not -

Allowed
1001 6 666.67kHz
1010 12 333.33kHz
1011 24 166.67kHz
1100 48 83.33kHz
1101 96 41.67kHz
1110192 20.83kHz
1111 384 10.42kHz

Figure. 3 Reference division ratios

7

SP5669

MSB LSB

ADDRESS 1 1 0 0 0 MA1 MA0 1 A Byte 1
STATUS BYTE POR FL X X X A2 A1 A0 A Byte 2

Table 2 Read data format (MSB is transmitted first)

A : Acknowledge bit
MA1, MA0 : Variable address bits (see Table 3)
2 16 –2 0 : Programmable division ratio control bits
PE : Prescaler enable
R3,R2,R1,R0 : Reference division ratio select (see Fig. 3)
C1, C0 : Charge pump current select (see Fig.6)
RE : Reference oscillator output enable
RTS : REF/COMP output select when RE=1 (see Fig.5)
RTS : Test mode enable when RE=0 (see Fig.5)
TS2, TS1, TS0 : Test mode control bits (valid when RE=0, RTS=1, see Fig. 5)
P0 : P0 port output state (always valid except when RE=0, RTS=1)
P3, P2, P1 : P3, P2 and P1 port output states
POR : Power On Reset indicator
FL : Phase Lock Flag
A2, A1, A0 : ADC data (see Table 4)
X : Don’t care

MA1 MA0 Address input voltage level

0 0 0 – 0.1V

CC

0 1 Open circuit
1 0 0.4V CC – 0.6VCC #
1 1 0.9V CC – V

CC

# Programmed by connecting a 15kΩ resistor

between pin 4 and V

CC

Table 3 Address selection

A2 A1 A0 Voltage on ADC input

1 0 0 0.6V

CC

toV

CC

0 1 1 0.45V CC to 0.6V

CC

0 1 0 0.3V CC to 0.45V

CC

0 0 1 0.15V CC to 0.3V

CC

0 0 0 0 to 0.15V

CC

Table 4 ADC levels

MSB LSB

ADDRESS 1 1 0 0 0 MA1 MA0 0 A Byte 1
PROGRAMMABLE

DIVIDER 0 2

14

2

13

2

12

2

11

2

10

2

9

2

8

A Byte 2

PROGRAMMABLE
DIVIDER 2

7

2

6

2

5

2

4

2

3

2

2

2

1

2

0

A Byte 3

CONTROL DATA 1 2

16

2

15

PE R3 R2 R1 R0 A Byte 4

CONTROL DATA C1 C0 RE RTS P3 P2/TS2 P1/TS1 P0/TS0 A Byte 5

Table 1 Write data format (MSB is transmitted first)

Figure. 4 Data formats

8

SP5669

RE RTS TS2 TS1 TS0 REF/COMP OUTPUT Test mode description

MODE

0 0 X X X Disabled to high state Normal operation
0 1 X 0 0 Disabled to high state Charge pump sink.

Status byte FL = logic ‘1’

0 1 X 0 1 Disabled to high state Charge pump source.

Status byte FL = logic ‘0’

0 1 X 1 0 Disabled to high state Charge pump disabled.

Status byte FL=logic ‘0’
0 1 X 1 1 Disabled to high state Port P0 = F pd /2
0 1 1 X X Disabled to high state Varactor Drive Output

disabled

1 0XXX F

ref

switched Normal operation

1 1XXX F

comp

switched Normal operation

X=don’t care

Figure. 5 REF/COMP output mode and Test modes

C1 C0 Current in µA

byte 5, bit 1 byte 5, bit 2

min typ max
0 0±90 ±120 ±150
01 ±195 ±260 ±325
1 0±416 ±555 ±694
11±900 ±1200 ±1500

Figure 6. Charge pump current

300

100

50

10

1000 2000

3000

FREQUENCY

(MHz)

3500

OPERATING

WINDOW

1000 2000

2700

3000

FREQUENCY

(MHz)

3500300

OPERATING

WINDOW

300

100

50

10

VIN

(mV RMS

INT

O 50

)

VIN

(mV RMS

INT

O 50

)

100

8080

Figure. 7a Typical input sensitivity

(prescaler disabled, PE=0)

Figure. 7b Typical input sensitivity

(prescaler enabled, PE=1)

9

SP5669

Double Conversion Tuner Systems

The high 2.7GHz maximum operating frequency and
excellent noise characteristics of the SP5669 enables
the construction of double conversion high IF tuners.

A typical system shown in Fig.8 will use the SP5669 as
the first LO control for full band upconversion to an IF of
greater than 1GHz.

The wide range of reference division ratios allows
the SP5669 to be used both for the up converter LO with
a high phase comparator frequency (hence low phase
noise) and the down converter which utilises the device
in a lower comparison frequency mode (which offers a
fine step size).

50–900MHz

1.6GHz

38.9MHz

1650–2700MHz

SP5659 SP5659

First LO

Second LO

Reference Clock

Figure. 8 Example of double conversion from VHF/UHF frequencies to TV IF

CONTROL

MICRO

15nF

68pF

+30V

+5V

22k

16k 47k

+12V

2n2BCW31

1n
1n

10n

P3

TUNER

OSCILLATOR

OUTPUT

SP5659

13k3

P0

SCL

SDA

ADDRESS

REF

10n

18pF4MHz

Optional application utilising
on–board crystal controlled
oscillator

2
3
4
5
6
7

13
12
11
10

89

116116

14

15

P2 P1

ADC

Figure. 9 Typical appliction

Application Notes

A generic set of application notes AN168 for designing
with synthesisers such as the SP5659 has been written.
This covers aspects such as loop filter design and
decoupling. This application note is also featured in the
Media Data Book, or refer to the Mitel Semicondor
Internet Site http://www.gpsemi.com.

A generic test/demo board has been produced which
can be used for the SP5669. A circuit diagram and list
of components for the board is shown in Figs. 10 and 11.

The board can be used for the following purposes:

(A) Measuring RF sensitivity performance.
(B) Indicating port function.
(C) Synthesising a voltage controlled oscillator.
(D) Testing of external reference

SP5669

SP5669

SP5669

10

SP5669

EXTERNAL

REFERENCE

SKT2

10nF*

*(NOT FITTED)

C6

C2
15nF

R6 13K3

C3

68pF

+5V

P2

+12V

C8

C9
C7/C8/C9 = 100nF

R7
22K

C7

R8

16K

R9

47K

C12
2n2F

VAR
GND

T1

2N3904

13

12

11
10

98

2

3

4

5

6

7

C5
1nF

C4

1nF

SKT1

RF INPUT

C10
1nF

R5 4K7

D5D4D3D2D1

R4 4K7

R3 4K7

R2 4K7

R1 4K7

C11
1nF

C1

18pF

X1 4MHz

P1

C13

100pF

C14
100pF

DISABLE / REF
ENABLE
DATA

/ SDA

CLOCK / SCL

+30V

LOCK

11

14

15

16

NOTE : The circuit diagram shown is designed
for use with a number of synthesisers.
The LED connected to pin 1

1 is redundant when

a SP5659 is used in this board.

Figure. 10 Test board

Figure. 11 Test board (layout)

SP5669

.

11

SP5669

Loop Bandwidth

The majority of applications for which the SP5669 is
intended require a loop filter bandwidth of between
2kHz and10kHz.

Typically the VCO phase noise will be specified at both
1kHz and10kHz offset. It is common practice to arrange
the loop filter bandwidth such that the 1kHz figure lies
within the loop bandwidth. Thus the phase noise de­pends on the synthesiser comparator noise floor, rather
than the VCO.

The 10kHz offset figure should depend on the VCO
providing the loop is designed correctly, and is not
underdamped.

Reference Source

The SP5669 offers optimal LO phase noise perform­ance when operated with a large step size. This is due
to the fact that the LO phase noise within the loop
bandwidth is:

phase comparator LO frequency
noise floor + 20 log

10

phase comparator frequency

Assuming the phase comparator noise floor is flat
irrespective of sampling frequency, this means that the
best performance will be achieved when the overall LO
to phase comparator division ratio is a minimum.

There are two ways of achieving a higher phase compa­rator sampling frequency:–

A) Reduce the division ratio between the reference

source and the phase comparator
B) use a higher reference source frequency.
Approach B) may be preferred for best performance

since it is possible that the noise floor of the reference
oscillator may degrade the phase comparator perform­ance if the reference division ratio is very small.

Driving Two Devicesfrom A Common
Reference

As mentioned earlier in the Datasheet, the SP5669 has
a REF/COMP output which allows two synthesisers to
be driven from a common reference. To do this, the
‘‘Master” should be programmed by setting RE = 1 and
RTS = 0. The driven device should be programmed for
normal operation i.e. RE = 0, and RTS = 0. The two
devices should be connected as shown below.

( )

12

SP5669

4MHz

18pF 1nF

SP5659

2
3
4
5
6
7

13
12
11
10

89

14

15

116116

SP5659

2
3
4
5
6
7

13
12

11

10

89

14

15

116116

Fig. 12 Driving two devices from a common reference

SP5669

SP5669

0.50.2 10

+j0.2

+j0.5

+j1

+j2

+j5

2 5

–j5

–j2

–j1

–j0.5

–j0.2

FREQUENCY

MARKERS AT 100MHz,

S11:Z0 = 50

X

X

X

X

NORMALISED

T

O 50

500MHz, 1GHz

AND 2.7GHz

Figure. 13 typical RF input impedance

13

SP5669

V

REF

500 500

RF INPUTS

V

CC

CHARGE

PUMP

DRIVE

OUTPUT

PORT

CRYSTAL

RF

inputs

Loop amplifier

SDA and SCL and ADC

Reference oscillator

Output Ports

100

OS

(Output disable)

V

CC

200

V

CC

3k

SCL/SDA/ADC

ACK

SDA

ONL

Y

V

CC

30k

3k

10K

ADDRESS

Address input

REF/COMP output

V

CC

REF/COMP

enable/
disable

Figure. 14 Input/Output interface circuits

M Mitel (design) and ST-BUS are registered trademarks of MITEL Corporation
Mitel Semiconductor is an ISO 9001 Registered Company
Copyright 1999 MITEL Corporation
All Rights Reserved
Printed in CANADA

TECHNICAL DOCUMENTATION - NOT FOR RESALE

World Headquarters - Canada

Tel: [phone]

Fax: [phone]

North America Asia/Pacific Europe, Middle East,

Tel: [phone] Tel: [phone] and Africa (EMEA)

Fax: [phone] Fax: [phone] Tel: [phone]

Fax: [phone]

http://www.mitelsemi.com

Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no
liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of
patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or
service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever.
Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or
other intellectual property rights owned by Mitel.

This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or
contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this
publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific
piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or
data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in
any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Mitel’s
conditions of sale which are available on request.