Datasheet SP5668, SP5668KG, SP5668MP1S, SP5668MP1T Datasheet (MITEL)

.

The SP5668 is a single chip frequency synthesiser

designed for tuning systems up to 2.7GHz.

The RF preamplifer contains a divide by two prescaler
which can be disabled for applications up to 2GHz so enabling
a step size equal to the comparison frequency up to 2GHz and
twice the comparison frequency up to 2.7GHz.

Comparison frequencies are obtained either from a crystal
controlled on–chip oscillator or from an external source.

The device contains three switching ports, P0 – P2,
together with an ’in–lock’ flag output. Various test modes
including varactor disable and charge pump disable are also
included.

FEATURES

■ Complete 2.7GHz single chip system

■ Optimised for low phase noise

■ Selectable divide by two prescaler

■ Selectable reference division ratio

■ Charge pump disable

■ Varactor line disable

■ ‘In–lock’ flag

■ Two selectable charge pump currents

■ Three switching ports

■ Reference frequency output

■ ESD protection (Normal ESD handling procedures

should be observed)

MP16

CHARGE PUMP

CAP Q1

CRYSTAL Q2

ENABLE

DATA

CLOCK

PORT P2

PORT P1/OC

DRIVE
V

EE

RF INPUT
RF INPUT

V

CC

LOCK
REF
PORT P0/OC

Fig. 1 Pin connections - top view

APPLICATIONS

■ SAT, TV, VCR and Cable tuning systems

■ Communications systems

ORDERING INFORMATION

SP5668/KG/MP1S (Tubes,)
SP5668/KG/MP1T Tape and Reel)

SP5668

2.7GHz 3-Wire Bus Controlled Synthesiser

Preliminary Information

DS4538 - 1.6 January 1997

2

SP5668

Fig. 2 SP5668 block diagram

ELECTRICAL CHARACTERISTICS

T

AMB

= 120°C to +80°C, V

CC

= +4.5 to +5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by either
production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise
stated.

Characteristic Pin Value Units Conditions

Min Typ Max

Supply current, Icc 12 65 81 mA Vcc = 5V Prescaler enabled, PE = 1

58 72 mA Vcc = 5V Prescaler disabled, PE = 0

RF input voltage 13, 14 100 300 mV

rms

100MHz Prescaler enabled, PE = 1
See Fig. 5b.

13, 14 40 300 mV

rms

300MHz - 2.7GHz Prescaler enabled,
PE = 1, See Fig. 5b.

13,14 40 300 mV

rms

100MHz to 2.0GHz Prescaler

disabled, PE = 0, See Fig. 5a
RF input impedance 13, 14 See Fig. 4.
Data, Clock, Enable 4,5,6

Input high voltage 3 V

CC

V
Input low voltage 0 0.7 V
Input high current 10 µA Input voltage = V

CC

Input low current -10 µA Input voltage = V

EE

Hysteresis 400 mV
Clock Rate 6 500 kHz

REFERENCE

DIVIDER

See Table 1

DE

13

14

INPUTS

RF

PROGRAMMABLE

DIVIDER

÷ 16/17

÷ 2/1

4 BIT

COUNT

13 BIT

COUNT

F

pd

F

comp

PHASE

COMP

CHARGE

PUMP

OSC

F

ref

REF

CRYSTAL

Q1

CRYSTAL

Q2

CHARGE

PUMP

DRIVE

1

16

OS

CO

LOCK

1 BIT

LATCH

3 BIT LATCH

(R0,R1,R2)

1 BIT

LATCH

FLOCK

1 BIT

LATCH

3 BIT

LATCH AND

PORT

INTERFACE

DATA

INTERFACE

DISABLE

18 BIT LATCH

ENABLE

CLOCK

DATA

4
5

6

P2P1P0

3

SP5668

ELECTRICAL CHARACTERISTICS (continued)

T

AMB

= 120°C to +80°C, V

CC

= +4.5 to +5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by either
production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise
stated.

Characteristic Pin Value Units Conditions

Min Typ Max

Bus timing 4, 5, 6

Data set up , t

SU

300 ns See Fig. 3

Data hold, t

HD

600 ns See Fig. 3

Enable set up, t

ES

300 ns See Fig. 3

Enable hold , t

EH

600 ns See Fig. 3

Clock to enable, t

CE

300 ns See Fig. 3

Charge pump output 1 See Table 3, V

pin1

=2V
Current
Charge pump output 1 ±10 nA V

pin1

= 2V
leakage
Drive output current 16 1 mA V

PIN16

= 0.7V
Drive output saturation 16 350 mV OS = 1
Voltage when disabled
External reference input 3 2 20 MHz AC coupled sinewave
frequency
External reference input 3 200 500 mVp-p AC coupled sinewave
amplitude
Crystal frequency 3 4 12 MHz
Recommended crystal 10 200 Ω Applies to 4MHz crystal only.
Series resistance "Parallel resonant" crystal. Figure

quoted is under all conditions

including start up.
Reference oscillator bias 3 200 µA See Fig. 11
current
REF output voltage* 10 350 mVp-p AC coupled, 4MHz reference

frequency, See Fig.
Phase detector comparison 4 MHz
frequency
Equivalent phase noise at dBc/Hz See **Note
phase detector
RF division ratio 240 131071 PE = 0, Prescaler disabled

480 262142 PE = 1, Prescaler enabled
Reference division ratio See Table 1
Output ports P0-P2 7-9

Sink current 10 mA V

PORT

= 0.7V

Leakage current 10 µAV

PORT

= 13.2V

Lock output

Sink current 1 mA V

PIN10

= 0.7V, 'out of lock'

Leakage current 10 µA 'in lock'

* REF output should be connected to V

CC

if unused

** Note: 1. -148dB @ 1KHz offset with 1MHz comparison frequency measured at the phase comparator.

2. When external reference is used, a high signal level is required for low phase noise.

4

SP5668

ABSOLUTE MAXIMUM RATINGS

All voltages are referred to VEE at 0V
Charateristics Pin Min Max Units Conditions
Supply voltage, V

CC

12 -0.3 7 V
RF input voltage 13, 14 2.5 Vp-p
RF input offset 13, 14 -0.3 VCC+0.3 V
Port output voltage 7-9 -0.3 14 V Port in off state

7-9 -0.3 6 V Port in on state
Total port current 7-9 50 mA
REFoutput DC offset 10 -0.3 VCC+0.3 V
Lock output DC offset 11 -0.3 V

CC

+0.3 V
Lock output current 11 10 mA
Charge pump DC offset 1 -0.3 VCC+0.3 V
Drive DC offset 16 -0.3 V

CC

+0.3 V
Crystal oscillator DC offset 2, 3 -0.3 V

CC

+0.3 V
Data, Clock & inputs 4,5,6 -0.3 V

CC

+0.3 V
Storage temperature -55 +150 °C
Junction temperature +150 °C
MP16 Thermal resistance
Chip to ambient 111 °C/W
Chip to case 41 °C/W
Power consumption 407 mV All ports off, prescaler enabled
at V

CC

= 5.5V

ESD protection ALL 2 kV MIL-STD 883 TM3015

FUNCTIONAL DESCRIPTION

The SP5668 contains all the elements necessary, with the
exception of a frequency reference, loop filter and external
high voltage transistor, to control a varicap tuned local oscil­lator, so forming a complete PLL frequency synthesised
source. The device allows for operation with a high compari­son frequency and is fabricated in high speed logic, which
enables the generation of a loop with good phase noise
performance. The RF preamplifier contains a selectable di­vide by two for operation above 2.0GHz. Up to 2GHz the RF
input interfaces directly with the programmable divider, so
eliminating degradation in phase noise due to the prescaler
action. The block diagram is shown in Fig.2.

The SP5668 is controlled by a standard 3–wire bus com­prising data, clock and enable inputs. The programming word
contains 27 bits. P0 - P2 are used for port selection, 217 - 20 set

the programmable divider ratio R2 - R0 select the reference
division ratio (Table1). C0 sets the charge pump current
(Table 3) and the remaining two bits T0, OS access test modes
and disable the varactor drive (Table 2).The programming
format is shown in Fig. 3.

The clock input is disabled by an enable low signal, data is
therefore only clocked into the internal shift registers during an
enable high and is loaded into the controlling buffers by an
enable high to low transition. This load is also synchronised
with the programmable divider so giving smooth fine tuning.

The RF signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider signals.
The output of the preamplifier is fed to the ÷ 2/1 selectable
prescaler and then to the 17 bit fully programmable divider,
which is of MN+A architecture. The M counter is 13 bit and the
A counter 4. If bit PE is set to a 0 the prescaler is disabled;
the control function PE cannot be used dynamically. The
output of the programmable divider is fed to the phase
comparator where it is compared in both phase and frequency
domain with the comparison frequency. This frequency is
derived either from the on board crystal controlled oscillator or
from an external source. In both cases the reference
frequency is divided down to the comparison frequency by the
reference divider which is programmable into 1 of 8 ratios as
described in Table 1.

The output of the phase comparator feeds the charge
pump and loop amplifier section, which when used with an
external high voltage transistor and loop filter integrates the
current pulses into the varactor line voltage. The charge pump
current is selected by bit C0 as described in Table 3.

The phase comparator also drives the lock detect circuit
which generates a lock flag. 'In-lock' is indicated by a high
impedance state on the lock output.

The crystal frequency Fref is available at the REF output.
This may be used as the reference for a second synthesiser
as shown in Fig. 6. The REF output is disabled by connecting
the output, pin 3, to VCC.

5

SP5668

PHASE NOISE

The SP5668 has been designed to offer good phase noise
performance even when operated with a standard low profile
4MHz crystal and a high comparison frequency, e.g. 2MHz.

The typical phase noise performance measured in the
standard application is contained in Table 4. It has been
demonstrated that even higher levels of performance will be
achieved in a tuner application.

TEST MODES

The programmable divider output divided by two Fpd/2 and
the comparison frequency Fcomp, can be switched to ports P0
and P1 respectively.

The charge pump can be forced to either source or sink
current, and may be disabled to high impedance state.

The varactor DRIVE output can be disabled by the OS bit
within the data word, so switching the external transistor 'OFF'
and allowing an external voltage to be written to the varactor
line for tuner alignment purposes.

The test modes are described in Table 2.

Fig. 3 Data format and timing

R2 R1 R0 RATIO Comparison Frequency with a 4MHz

external reference

0002 2MHz
0014 1MHz
0108 500kHz
0 1 1 16 250kHz
1 0 0 32 125kHz
1 0 1 64 62.5kHz
1 1 0 128 31.25kHz
1 1 1 256 15.625kHz

Table 1 Reference division ratio

P1 P0 T0 FUNCTIONAL DESCRIPTION

X X 0 Normal operation
0 0 1 Charge pump sink. LOCK output = Lo Z
0 1 1 Charge pump source. LOCK output = Hi Z
1 0 1 Charge pump disable. LOCK output = Lo Z
1 1 1 Port P1 = Fcomp: Port 0 = Fpd/2

X = Don't care

Table 2 Test modes

CLOCK

ENABLE

DATA

FREQUENCY DATA

2

26225224223222221220219218217216

2

0

P2 P1 P0 TO OS CO R2 R1 R0 PE

LSB

2

16

to

2

0

t : Programmable divider ratio control bits

R2

R1 R0

,,

t : Reference divider ratio control bits (see T

able 1)

P2, P1, P0

t : Port control bits

CO

t : Charge Pump current select (see T

able 3)

OS

t : Drive output disable switch

T0

t : T

est mode enable (see T

able 2)

MSB

PE

:

÷2 Prescaler (Enable = 1, Disable = 0)

6

SP5668

C0 CURRENT IN mA

MIN TYP MAX

0 0.23 0.30 0.37
1 0.68 0.90 1.12

Table 3 Charge pump

F

LO

F

comp

RF Division VCO PHASE EQUIVALENT

(4MHz XTAL) RATIO NOISE @1kHZ PHASE NOISE

OFFSET (dBc/Hz) PHASE

DETECTOR (dBc/Hz)

2GHz 1MHz 2000 -84 -146
2GHz 2MHz 1000 -80 -144

Table 4 Typical phase noise

Fig. 4. Typical input impedance

0.50.2 10

+j0.2

+j0.5

+j1

+j2

+j5

2 5

–j5

–j2

–j1

–j0.5

–j0.2

FREQUENCY

MARKERS AT 100MHz,

S11:Z0 = 50

X

X

X

X

NORMALISED

T

O 50

Ω

500MHz, 1GHz

AND 2.7GHz

7

SP5668

Fig. 5a Typical input sensitivity (Prescaler disabled, PE=0)

Fig. 6. Example of double conversion from VHF/UHF frequencies to TV IF

Fig. 5b Typical input sensitivity (Prescaler enabled, PE=1)

Fig. 7. typical application, SP5668

300

100

40

10

1000 2000

3000

FREQUENCY

(MHz)

3500

OPERATING

WINDOW

1000 2000

2700

3000

FREQUENCY

(MHz)

3500300

OPERATING

WINDOW

300

100

40

10

VIN

(mV RMS

INT

O 50

Ω)

VIN

(mV RMS

INT

O 50

Ω)

100

8080

50

CONTROL

MICRO

15nF

68pF

+30V

+5V

22k

16k 47k

+12V

2n2BCW31

1n
1n

10n

P2

TUNER

OSCILLATOR

OUTPUT

SP5668

13k3

P0

LOCK

CLOCK

DATA

ENABLE

Optional application utilising
on–board crystal controlled
oscillator

1

14

2
3
4
5
6
7

13
12
11
10

89

15

16

P1

4MHz

18pF

2

3

39pF

REFERENCE

VCO

VCO

10nF

50 - 900MHz

38.9MHz

1650-2700MHz

2

3

10

3

SP5668

SP5668

1.6GHZ

8

SP5668

APPLICATION NOTES

A generic set of application notes AN168 for designing with
synthesisers such as the SP5668 has been written. This
covers aspects such as loop filter design and decoupling. This
application note is also featured in the Media IC Handbook.

A generic test/demo board has been produced which can
be used for the SP5668. A circuit diagram is shown in Fig. 8.

The board can be used for the following purposes:
(A) Measuring RF sensitivity performance.
(B) Indicating port function
(C) Synthesising a voltage controlled oscillator
(D) Testing of external reference sources

Fig. 8 Evaluation board

1

14

EXTERNAL

REFERENCE

SKT2

10nF

*(NOT FITTED)

C7

C2
15nF

R6 13K3

C3

68pF

+5V

P2

+12V

C10

C9
100nF

R2
22K

C1

1 100nF

R9

16K

R10

C14
2n2F

VAR
GND

T1

BCW31

13

12

11

10

9

8

2

3

4

5

6

7

C3
1nF

C5

1nF

SKT1

RF INPUT

C4
10nF

R5 4K7

D5D4D2D1

R4 4K7

R7 4K7

R6 4K7

C6 18pF

X1 4MHz

P1

C12
100pF

C13
100pF

ENABLE
DATA

/ SDA

CLOCK / SCL

8

+30V

PIN NO : 7

LOCK

C8

39pF

15

16

REFERENCE
OUTPUT
SKT

SW1

100nF

47µF

47µF

47K

SW2

LOCK

P0
P1

P2

9

SP5668

LOOP BANDWIDTH

The majority of applications for which the SP5668 is
intended require a loop filter bandwidth of between 2kHz and
10kHz.

Typically the VCO phase noise will be specified at both
1kHz and10kHz offset. It is common practice to arrange the
loop filter bandwidth such that the 1kHz figure lies within the
loop bandwidth. Thus the phase noise depends on the
synthesiser comparator noise floor, rather than the VCO.

The 10kHz offset figure should depend on the VCO
providing the loop is designed correctly, and is not
underdamped.

REFERENCE SOURCE

The SP5668 offers optimal LO phase noise performance
when operated with a large step size. This is due to the fact
that the LO phase noise within the loop bandwidth is:

phase comparator
noise floor + 20 log

Assuming the phase comparator noise floor is flat
irrespective of sampling frequency, this means that the best
performance will be achieved when the overall LO to phase
comparator division ratio is a minimum.

There are two ways of achieving a higher phase
comparator sampling frequency:–

A) reduce the division ratio between the reference source
and the phase comparator

B) use a higher reference source frequency.
Approach B) may be preferred for best performance since it is

possible that the noise floor of the reference oscillator may
degrade the phase comparator performance if the reference
division ratio is very small.

LO frequency

phase comparator frequency

()

10

SP5668

V

REF

500 500

RF INPUTS

V

CC

CHARGE

PUMP

DRIVE

OUTPUT

PORT/LOCK

XTAL

RF inputs

Loop amplifier

Disable, Enable, Data and Clock inputs

Reference oscillator

Output Ports and Lock Output

V

CC

BIAS

25K

200

OS

(Output disable)

V

CC

CAP

Reference output

V

CC

1.2mA

REF

Fig.9 Input/Output interface circuits

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Mitel Semiconductor is an ISO 9001 Registered Company
Copyright 1999 MITEL Corporation
All Rights Reserved
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