Datasheet SL25241C, SL2524B, SL2524C, SL2524HP, SL2524LC Datasheet (MITEL)

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1.3GHz Dual Wideband Logarithmic Amplifier
The SL2524 is a pin compatible replacement for the SL2521 and SL2522 series of log amplifiers, and exhibits a superior stability performance. The amplifier is a successive detection type which provides linear gain and accurate loga­rithmic signal compression over a wide bandwidth. The two stages can be operated independently.
When six stages (three SL2524s) are cascaded the strip can be used for IFs between 30-650MHz whilst achieving greater than 65dB dynamic range with a log accuracy of <±1.0dB. The balanced limited output also offers accurate phase information with input amplitude.
1.3GHz Bandwidth (-3dB)
Balanced IF limiting
3ns Rise Times/5ns Fall Times (six stages)
20ns Pulse Handling (six stages)
Temperature Stabilised
Surface Mountable
SL2524
DS4548 - 2.1 July 1995
APPLICATIONS
Ultra Wideband Log Receivers
Channelised Receivers
Monopulse Applications
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC above VEE) +7.0V Storage temperature -65°C to +150°C Operating temperature range SL2524/B/LC -40°C to +85°C SL2524/C/HP -30°C to +85°C Junction temperature - LC20 +175°C
- HP20 +150°C
Applied DC voltage to RF input ±0.4V (between RF I/P Applied RF power to RF input +15dBm
Value of R Thermal resistance:-
resistors NOT less than 180
SET
Die to case -LC 20 28°C/W
- HP20 20°C/W
Die to ambient - LC20 73°C/W
- HP20 82°C/W
ORDERING INFORMATION
SL2524/B/LC (Ceramic leadless chip carrier package) SL2524/C/HP (Plastic J lead chip carrier package) SL2524/NA/1C (DC probe tested bare die) 5962 - 92315 (SMD)
pins)
OPTIONAL PIN
REFERENCE
PIN DESCRIPTION
1 SUB V 2 IF OUTPUT (A)
EE
3 IF OUTPUT (A) 4VEE (A) 5 OUTPUT VC (A) 6 IF INPUT (A) 7 IF INPUT (A) 8VCC (A) 9 DET. OUTPUT (A) 10 R SET (A)
Fig.1 Pin connections top view
PIN DESCRIPTION
11 N/C 12 R SET (B) 13 DET. OUTPUT (B) 14 V 15 IF OUTPUT (B)
(B)
CC
16 IF OUTPUT (B) 17 OUTPUT VCC (B) 18 VEE (B) 19 IF INPUT (B) 20 IF INPUT (B)
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SL2524
Fig.2 Circuit diagram of single stage A - (stage B pin Nos bracketed)
Fig.3 Pad map for SL2524 naked die
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ELECTRICAL CHARACTERISTICS - SL2524B
Guaranteed at the following test conditions unless otherwise stated
Frequency = 200MHz, T
Load impedance = 50, Test Circuit = Fig. 4, R
amb = +25°C, Input power = -30dBm, VCC = 6V ±0.1V, Source Impedance = 50.
= 300. Tested as a dual stage.
SET
SL2524
Characteristic
Supply current Small signal gain (dual stage,
single ended)
Detected output current (max)
Detected output current (no signal)
Min
70
9.6
10.1
9.9
9.5
9.7
9.3
8.2
3.20
3.05
3.15
3.10
2.80
2.90
2.85
0.85
0.80
0.80
Value
Typ
87
11.4
11.6
11.3
11.0
11.2
10.7
9.7
3.45
3.25
3.30
3.30
3.10
3.15
3.10
0.95
0.93
0.90
Max
100
13.0
13.1
12.7
12.5
12.7
12.1
11.2
3.70
3.45
3.45
3.50
3.30
3.45
3.65
1.15
1.10
1.10
Units
mA
dB dB
dB dB
dB dB
dB mA mA mA
mA
mA mA
mA
mA mA mA
Conditions
T
amb = +25°C f = 25MHz See Notes 1, 3
Tamb = -40°C f = 200MHz See Notes 2, 3 T
amb = +25°C f = 200MHz See Note 3
T
amb = +85°C f = 200MHz See Notes 2, 3 amb = -40°C f = 500MHz See Notes 2, 3
T
amb = +25°C f = 500MHz See Note 3
T T
amb = +85°C f = 500MHz See Notes 2, 3 amb = +25°C, V
T See Note 1 T
amb = -40°C, V
See Note 2
= 0dBm, f = 25MHz
IN
= 0dBm, f = 200MHz
IN
Tamb = +25°C, VIN = 0dBm, f = 200MHz T
amb = +85°C, V
See Note 2
= 0dBm, f = 200MHz
IN
Tamb = -40°C, VIN = 0dBm, f = 500MHz See Note 2 Tamb = +25°C, VIN = 0dBm, f = 500MHz T
amb = +85°C, V
See Note 2
= 0dBm, f = 500MHz
IN
Tamb = -40°C, See Note 2 T
amb = +25°C, See Note 2 amb = +85°C, See Note 2
T
Upper cut off frequency (RF)
Lower cut off frequency (RF) Detector cut off frequency Limited IF O/P voltage Phase variation with input level
600 900 600
135
1100 1100
800
0.35 700 155
0±2.0
1
175
0±3.0
MHz MHz MHz
MHz MHz
mV
Degree
(normalised to -30dBm)
-4.0±2.0
Limited O/P var with temp. Noise figure Max I/P before overload Input impedance Output impedance
NOTES
1. Parameter guaranteed but not tested
2. Tested at 25°C only, but guaranteed at temperature
3. Gain will typically increase by 6dB, when RF outputs use 1k loads in place of 50
±12
14 15
1
50
-4.0±3.0
±25
Degree
mV
dB
dBm
k
-3dB w.r.t 200MHz, T
amb = -40°C
See Note 2
-3dB w.r.t 200MHz, T
amb = +25°C
-3dB w.r.t 200MHz, Tamb = +85°C See Note 2
-3dB w.r.t 200MHz, Tamb = +25°C 50% O/P current w.r.t. 200MHz I/P power = 0dBm, T
amb = +25°C
Frequency = 70MHz, -55 to +3dBm See Note 2 Frequency = 200MHz, -55 to +3dBm See Note 2
See Note 1
1kΩ in parallel with 2pF
3
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SL2524
ELECTRICAL CHARACTERISTICS - SL2524C
Guaranteed at the following test conditions unless otherwise stated
Frequency = 200MHz, T Load impedance = 50, Test Circuit = Fig. 4, R
amb = +25°C, Input power = -30dBm, VCC = 6V ±0.1V, Source Impedance = 50.
= 300. Tested as a dual stage.
SET
Characteristic
Supply current Small signal gain (dual stage,
single ended)
Detected output current (max)
Detected output current (no signal)
Min
70
9.6
9.6
9.4
9.0
9.2
8.8
7.7
3.20
2.95
3.05
3.00
2.70
2.80
2.75
0.75
0.70
0.70
Value
Typ
87
11.4
11.6
11.3
11.0
11.2
10.7
9.7
3.45
3.25
3.30
3.30
3.10
3.15
3.10
0.95
0.93
0.90
Max
100
13.0
13.6
13.2
13.0
13.2
12.6
11.7
3.70
3.55
3.55
3.50
3.30
3.55
3.75
1.25
1.20
1.20
Units
mA
dB dB
dB dB
dB dB dB
mA mA
mA mA
mA mA mA
mA mA mA
Conditions
T
amb = +25°C f = 25MHz See Note 3 amb = -30°C f = 200MHz See Notes 2, 3
T
amb = +25°C f = 200MHz See Note 3
T T
amb = +85°C f = 200MHz See Notes 2, 3 amb = -30°C f = 500MHz See Notes 1, 3
T T
amb = +25°C f = 500MHz See Note 1
T
amb = +85°C f = 500MHz See Notes 1, 3
Tamb = +25°C, VIN = 0dBm, f = 25MHz T
amb = -30°C, V
See Note 2 T
amb = +25°C, V
T
amb = +85°C, V
See Note 2
= 0dBm, f = 200MHz
IN
= 0dBm, f = 200MHz
IN
= 0dBm, f = 200MHz
IN
Tamb = -30°C, VIN = 0dBm, f = 500MHz See Note 1 T
amb = +25°C, V
See Note 1 T
amb = +85°C, V
See Note 1
amb = -30°C, See Note 2
T T
amb = +25°C, See Note 2
T
amb = +85°C, See Note 2
= 0dBm, f = 500MHz
IN
= 0dBm, f = 500MHz
IN
Upper cut off frequency (RF)
Lower cut off frequency (RF) Detector cut off frequency Limited IF O/P voltage Phase variation with input level
105
1000
0.35 600 135
0±2.0
2
175
MHz
MHz MHz
mV
Degree
(normalised to -30dBm)
-4.0±2.0
Limited O/P var with temp. Noise figure Max I/P before overload Input impedance Output impedance
NOTES
1. Parameter guaranteed but not tested
2. Tested at 25°C only, but guaranteed at temperature
3. Gain will typically increase by 6dB, when RF outputs use 1k loads in place of 50
±12
14 15
1
50
±25
Degree
mV
dB
dBm
k
-3dB w.r.t 200MHz, T
amb = +25°C
See Note 1
-3dB w.r.t 200MHz, T
amb = +25°C
50% O/P current w.r.t. 200MHz I/P power = 0dBm, T
amb = +25°C
Frequency = 70MHz, -55 to +3dBm See Note 1 Frequency = 200MHz, -55 to +3dBm See Note 1
See Note 1
1kΩ in parallel with 2pF
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GENERAL DESCRIPTION
The SL2524 is primarily intended for use in Radar and EW receivers. Six stages (3 chip carriers) can be cascaded to form a very wideband logarithmic ampifier offering >65dB of input dynamic range, with pulse handling of better than 25ns. (See figs 5 and 6.)
A six stange strip also offers balanced IF limiting, linearity (log accuracy) of < ±1.0dB, temperature stabilisation and programmable detector characteristics.
The detector has an external resistor set (R allows the major characteristics of the detector to be programmed. With six stage strip it is possible to vary the value of R error/linearity.
on each detector and so improve the overall log
SET
) pin which
SET
SL2524
The detector is full wave and good slew rates are achieved with 2ns rise and 5ns fall times (no video filter). The video bandwidth of a six stage strip is typically 600MHz (-3dB).
The amplifier also offers balanced IF limiting, low phase shift versus input amplitude, and at an IF of 120MHz, less than 5° of phase change is achievable over the input level of
-55dBm to +5dBm.
The IF and Video ports can be used simultaneously, so offering phase, frequency and pulse (video) information. A slight loss of dynamic range (2dB) will be observed when the IF ports are used in conjunction with the video.
Fig.4 Test circuit
Fig.5 Schematic diagram showing configuration of SD Log strip
5
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SL2524
Fig.6 Circuit diagram for 6-log strip (results shown in figs. 11 to 24 were achieved with this circuit)
Typical characteristics for a dual - stage amplifier (i.e. One SL2524)
Fig.7 IF Gain vs frequency of 2 amplifiers (One SL2524)
6
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Typical characteristics for a dual - stage amplifier (i.e. One SL2524) cont.
SL2524
Fig.8 Normalised phase vs CW input level at 50, 250 and 450MHz for 50Ω O/P termination (25°C)
Fig.9 Detector current vs R
at 200MHz (25°C)
SET
7
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SL2524
Typical characteristics for a dual - stage amplifier (i.e. One SL2524) cont.
Fig.10 Detector current vs frequency at RSET = 200Ω and 500Ω (25°C)
Typical characteristics for a six stage strip, using detected output (Ref. figs 5 & 6)
Fig.11 Detector bandwidth (25°C)
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Typical characteristics for a six stage strip, using detected output (Ref. figs 5 & 6) cont.
0
SL2524
Fig.12 Detected O/P vs CW input at 60, 125, 450 and 600MHz at 25°C
Fig.13 Detected O/P vs CW input level and temperature at 60 and 125MHz
9
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SL2524
Typical characteristics for a six stage strip, using detected output (Ref. figs 5 & 6) cont.
Fig.14 Detected O/P vs CW input level at 450MHz across temperature
10
Fig.15 Typical log linearity of detected output measured at 450MHz (25°C)
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Typical characteristics for a six stage strip as a low phase shift wideband limiter (Ref. figs 5 & 6)
SL2524
Fig.16 IF limiting characteristics at 60MHz and 500MHz (25°C)
Fig.17 IF limiting characteristic at 60MHz across temperature
11
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SL2524
Typical characteristics for a six stage strip as a low phase shift wideband limiter (Ref. figs 5 & 6)
Fig.18 IF limiting characteristic at 500MHz across temperature
12
Fig.19 Small signal gain vs frequency across temperature
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Typical characteristics for a six stage strip as a low phase shift wideband limiter (Ref. figs 5 & 6)
SL2524
Fig.20 Phase deviation vs CW input level (normalised at -30dBm) at 25°C
across input frequency
Fig.21 Phase deviation vs CW input level (normalised at -30dBm) at 50MHz
across temperature
13
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SL2524
Typical characteristics for a six stage strip as a low phase shift wideband limiter (Ref. figs 5 & 6)
Fig.22 Phase deviation vs CW input level (normalised at -30dBm) at 450MHz
across temperature
14
Fig.23 Peak phase deviation over -65dBm → +10dBm CW input level vs CW input frequency.
Across temperature
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