Datasheet SL4013BD, SL4013BN Datasheet (SLS)

Semiconductor

Dual D Flip-Flop

High-Voltage Silicon-Gate CMOS

The SL4013B consists of two identical, independent data-type flipflops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively.

• Operating Voltage Range: 3.0 to 18 V

• Maximum input current of 1 µA at 18 V over full package-

temperature range; 100 nA at 18 V and 25°C

• Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

SL4013B

ORDERING INFORMATION

SL4013BN Plastic

SL4013BD SOIC

TA = -55° to 125° C for all packages

LOGIC DIAGRAM

PIN ASSIGNMENT

2.5 V min @ 15.0 V supply

FUNCTION TABLE

Inputs Outputs

Clock Data Reset Set Q Q

L L L L H H L L H L X L L Q Q

X X H L L H

SLS

System Logic

PIN 14 =V

PIN 7 = GND

CC

X X L H H L X X H H H H

X = don’t care

SL4013B

Semiconductor

MAXIMUM RATINGS

*

Symbol Parameter Value Unit

V

CC

V

IN

V

OUT

I

IN

P

DC Supply Voltage (Referenced to GND) -0.5 to +20 V DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±10 mA Power Dissipation in Still Air, Plastic DIP+

D

SOIC Package+ Power Dissipation per Output Transistor 100 mW

D

750 500

Tstg Storage Temperature -65 to +150 °C

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

260 °C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

mW

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

CC

VIN, V

OUT

T

A

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and V GND≤(VIN or V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

DC Supply Voltage (Referenced to GND) 3.0 18 V DC Input Voltage, Output Voltage (Referenced to GND) 0 V

CC

Operating Temperature, All Package Types -55 +125 °C

should be constrained to the range

OUT

)≤VCC.

OUT

V

SLS

System Logic

Semiconductor

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

SL4013B

V

CC

Guaranteed Limit

Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125°CUnit

V

OH

V

I

IN

OL

Minimum High-Level

IH

Input Voltage

Maximum Low -Level

IL

Input Voltage

Minimum High-Level Output Voltage

Maximum Low-Level Output Voltage

Maximum Input

V

=0.5 V or V

OUT

V

=1.0 V or V

OUT

V

=1.5 V or V

OUT

V

=0.5 V or V

OUT

V

=1.0 V or V

OUT

V

=1.5 V or V

OUT

VIN=GND or V

VIN= GND or V

CC

CC CC CC

- 0.5 V

- 1.0 V

- 1.5 V

- 0.5 V

- 1.0 V

- 1.5 V

5.0 10 15

3.5 7

11

1.5 3 4

4.95

9.95

14.95

0.05

3.5 7

11

1.5 3 4

4.95

9.95

14.95

0.05

3.5 7

11

1.5 3 4

4.95

9.95

14.95

0.05

18 ±0.1 ±0.1 ±1.0 µA

V

Leakage Current

I

CC

Maximum Quiescent Supply Current (per Package)

VIN= GND or V

CC

5.0 10 15 20

20

1 2 4

20

1 2 4

30 60

120

µA

600

I

OL

I

OH

Minimum Output Low (Sink) Current

Minimum Output High (Source) Current

VIN= GND or V UOL=0.4 V UOL=0.5 V UOL=1.5 V

VIN= GND or V UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V

CC

5.0 10 15

CC

5.0

5.0 10 15

0.64

1.6

4.2

-2.0

-0.64

-1.6

-4.2

0.51

1.3

3.4

-1.6

-0.51

-1.3

-3.4

0.36

0.9

2.4

-1.15

-0.36

-0.9

-2.4

Ma

SLS

System Logic

SL4013B

Semiconductor

AC ELECTRICAL CHARACTERISTICS(C

=50pF, RL=200 kΩ, Input tr=tf=20 ns)

L

V

CC

Guaranteed Limit

Symbol Parameter V ≥-55°C 25°C ≤125°C Unit

t

PLH

TLH

f

t

C

max

, t

PLH

PHL

, t

IN

Maximum Clock Frequency (Figure 1) 5.0

Maximum Propagation Delay, Clock to Q or Q

PHL

(Figure 1)

Maximum Propagation Delay, Set to Q or Reset to Q (Figure 2)

Maximum Output Transition Time, Any Output

THL

(Figure 1)

10 15

5.0 10 15

3.5 8

12

300 130

90

300 130

90

400 170 120

200 100

80

3.5 8

12

300 130

90

300 130

90

400 170 120

200 100

80

Maximum Input Capacitance - 7.5 pF

1.75 4 6

600 260 180

800 340 240

400 200 160

MHz

ns

TIMING REQUIREMENTS(C

=50pF, RL=200 kΩ, Input tr=tf=20 ns)

L

V

CC

Guaranteed Limit

Symbol Parameter V ≥-55°C 25°C ≤125°C Unit

t

tr, t

w

su

Minimum Pulse Width, Clock (Figure 1) 5.0

10 15

Minimum Pulse Width, Set or Reset (Figure 2) 5.0

10 15

Minimum Setup Time, Data to Clock (Figure 3)

5.0 10 15

Minimum Hold Time, Clock to Data

h

(Figure 3)

5.0 10 15

Maximum Input Rise or Fall Time, Clock (Figure

f

1)

5.0 10 15

140

60 40

180

80 50

40 20 15

5 5 5

500

30

6

140

60 40

180

80 50

40 20 15

5 5 5

500

30

6

280 120

80

360 160 100

80 40 30

10 10 10

1000

60 12

ns

µs

SLS

System Logic

SL4013B

Semiconductor

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

Figure 3. Switching Waveforms

EXPANDED LOGIC DIAGRAM

(1/2 of the Device)

SLS

System Logic