Datasheet Si2329DS Datasheet (Vishay) [ru]

P-Channel 8 V (D-S) MOSFET

G

TO-236

(SOT-23)

S

D

Top View

2

3

1

Si2329DS (D9)*

* Marking Code

Ordering Information: Si2329DS-T1-GE3 (Lead (Pb)-free and Halogen-free)

Si2329DS

Vishay Siliconix

MOSFET PRODUCT SUMMARY

VDS (V) R

0.030 at V

0.036 at V

- 8

0.048 at V

0.068 at V

0.120 at V

DS(on)

GS

GS

GS

GS

GS

()

= - 4.5 V

= - 2.5 V

= - 1.8 V

= - 1.5 V

= - 1.2 V

I

D

- 5.9

- 3.7

(A)

- 6

- 6

- 5

e

e

a

Qg (Typ.)

11.8 nC

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• TrenchFET® Power MOSFET

• 100 % R

Tested

g

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

• Load Switch

• Low Voltage Gate Drive

- Low On-Resistance

• Battery Management in Portable Equipment

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

Parameter Symbol Limit Unit

Drain-Source Voltage
Gate-Source Voltage

Continuous Drain Current (T

= 150 °C)

J

Pulsed Drain Current (t = 300 µs)

Continuous Source-Drain Diode Current

Maximum Power Dissipation

Operating Junction and Storage Temperature Range

T

= 25 °C

C

T

= 70 °C

C

T

= 25 °C

A

TA = 70 °C

= 25 °C

T

C

T

= 25 °C

A

T

= 25 °C

C

= 70 °C

T

C

T

= 25 °C

A

TA = 70 °C

V

DS

V

GS

I

D

I

DM

I

S

± 5

- 6

- 5.3

- 4.2

- 20

- 2.1

- 1.0

- 8

- 6

e

b, c

b, c

b, c

V

A

2.5

P

D

T

, T

J

stg

1.6

b, c

1.25

b, c

0.8

- 55 to 150

W

°C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient
Maximum Junction-to-Foot (Drain)

Notes:
a. Based on T
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. Maximum under steady state conditions is 166 °C/W.
e. Package limited.

Document Number: 67690
S11-0865-Rev. A, 02-May-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

= 25 °C.

C

b, d

5 s

Steady State

R

thJA

R

thJF

This document is subject to change without notice.

75 100

40 50

°C/W

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Si2329DS

Vishay Siliconix

MOSFET SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

V

Drain-Source Breakdown Voltage

V

Temperature Coefficient VDS/T

DS

Temperature Coefficient

V

GS(th)

Gate-Source Threshold Voltage

Gate-Source Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

Drain-Source On-State Resistance

Forward Transconductance

Dynamic

b

a

a

a

Input Capacitance

Reverse Transfer Capacitance

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

Gate Resistance

Tur n -O n De l a y T i m e

Rise Time

Turn-Off Delay Time

Fall Time

V

DS

J



V

GS(th)/TJ

V

GS(th)

I

GSS

I

DSS

I

V

D(on)

R

DS(on)

g

fs

C

iss

C

oss

C

rss

Q

g

Q

gs

Q

gd

R

g

t

d(on)

t

r

t

d(off)

t

f

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current

Pulse Diode Forward Current

a

Body Diode Voltage

Body Diode Reverse Recovery Time

Body Diode Reverse Recovery Charge

Reverse Recovery Fall Time

Reverse Recovery Rise Time

I

S

I

SM

V

SD

t

rr

Q

rr

t

a

t

b

Notes:
a. Pulse test; pulse width  300 µs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.

V

V

V

DS

V

DS

= - 4.2 A, V

I

D

IF = - 4.2 A, dI/dt = 100 A/µs, TJ = 25 °C

= 0 V, ID = - 250 µA

GS

ID = - 250 µA

V

= VGS, ID = - 250 µA

DS

VDS = 0 V, VGS = ± 5 V

V

= - 8 V, V

DS

= - 8 V, V

DS

DS

V

V

V

V

V

GS

GS

GS

GS

GS

= 0 V, TJ = 55 °C

GS

- 5 V, V

GS

= - 4.5 V, ID = - 5.3 A

= - 2.5 V, ID = - 4.8 A

= - 1.8 V, ID = - 4.2 A

= - 1.5 V, ID = - 3.5 A

= - 1.2 V, ID = - 0.8 A

VDS = - 4 V, ID = - 5.3 A

= - 4 V, V

DS

= - 4 V, V

= - 4 V, V

= 0 V, f = 1 MHz

GS

= - 4.5 V, ID = - 5.3 A

GS

= - 2.5 V, ID = - 5.3 A

GS

f = 1 MHz 0.8 4.2 8.4 

V

= - 4 V, RL = 0.9 

DD

= - 4.5 V, Rg = 1 

GEN

TC = 25 °C

IS = - 4.2 A

= 0 V

GS

= - 5.3 V

- 8 V

- 6

2.3

mV/°C

- 0.35 - 0.8 V

± 100 nA

- 1

- 10

- 20 A

0.025 0.030

0.030 0.036

0.037 0.048

0.045 0.068

0.060 0.120

2.0 S

1485

480

435

19.3 29

11.8 18

1.7

6.2

20 30

22 33

46 69

20 30

- 2.1

- 20

- 0.8 - 1.2 V

40 60 ns

26 39 nC

17

23

µA



pFOutput Capacitance

nC

ns

A

ns

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

This document is subject to change without notice.

Document Number: 67690

S11-0865-Rev. A, 02-May-11

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

V

0.015

0.030

0.045

0.060

0.075

0.090

0 5 10 15 20

R

DS(on)

- On-Resistance (Ω)

ID- Drain Current (A)

VGS= 1.2 V

VGS= 1.5 V

VGS= 2.5 V

VGS= 1.8 V

VGS= 4.5 V

0

1

2

3

4

5

0 5 10 15 20

V

GS

- Gate-to-Source Voltage (V)

Qg- Total Gate Charge (nC)

ID= 5.3 A

VDS= 2 V

VDS= 4 V

VDS= 6.4 V

0

1

2

3

4

5

0 0.3 0.6 0.9 1.2 1.5

I

D

- Drain Current (A)

VGS- Gate-to-Source Voltage (V)

TC= 125 °C

TC= 25 °C

TC= - 55 °C

20

VGS= 5 V thru 2 V

Si2329DS

Vishay Siliconix

15

10

- Drain Current (A)

D

I

5

0

00.511.52

VDS- Drain-to-Source Voltage (V)

= 1.5 V

GS

VGS= 1 V

Output Characteristics

C - Capacitance (pF)

2800

2100

1400

700

Transfer Characteristics

C

iss

C

C

rss

oss

On-Resistance vs. Drain Current and Gate Voltage

Document Number: 67690
S11-0865-Rev. A, 02-May-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Gate Charge

0

02468

1.45

1.25

1.05

-On-Resistance
(Normalized)

DS(on)

R

0.85

0.65

-50 -25 0 25 50 75 100 125 150

This document is subject to change without notice.

VDS- Drain-to-Source Voltage (V)

Capacitance

ID= 5.3 A

VGS= 4.5 V

VGS= 2.5 V

TJ- Junction Temperature (°C)

On-Resistance vs. Junction Temperature

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Si2329DS

0.1

1

10

0.0 0.2 0.4 0.6 0.8 1.0

I

S

- Source Current (A)

VSD- Source-to-Drain Voltage (V)

TJ= 25 °C

TJ= 150 °C

Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

0.06

ID= 5.3 A

0.05

0.04

Source-Drain Diode Forward Voltage

0.6

0.5

0.4

(V)

GS(th)

V

0.3

0.2

0.1

- 50 - 25 0 25 50 75 100 125 150

TJ-Temperature (°C)

ID= 250 μA

Threshold Voltage

- On-Resistance (Ω)

DS(on)

0.03

R

0.02
12345

VGS- Gate-to-Source Voltage (V)

TJ= 125 °C

TJ= 25 °C

On-Resistance vs. Gate-to-Source Voltage

10

8

6

Power (W)

4

2

0

0.01 0.1 1 10 100 1000

TA= 25 °C

Time (s)

Single Pulse Power

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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

100

Limited by R

10

1

- Drain Current (A)

D

I

0.1

TC= 25 °C
Single Pulse

0.01

0.1 1 10

* V

> minimum VGSat which R

GS

*

DS(on)

BVDSS Limited

VDS- Drain-to-Source Voltage (V)

DS(on)

Safe Operating Area

This document is subject to change without notice.

1 ms

10 ms

100 ms

1 s, 10 s

DC

is specied

Document Number: 67690

S11-0865-Rev. A, 02-May-11

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

0

0.6

1.2

1.8

2.4

3

0255075100125150

Power (W)

TC- Case Temperature (°C)

0.0

0.2

0.4

0.6

0.8

1.0

0 255075100125150

Power (W)

TA- Ambient Temperature (°C)

9.0

7.5

Package Limited

6.0

4.5

- Drain Current (A)

3.0

D

I

1.5

0.0
0 25 50 75 100 125 150

TC- Case Temperature (°C)

Current Derating*

Si2329DS

Vishay Siliconix

Power, Junction-to-Foot

* The power dissipation PD is based on T
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.

Document Number: 67690
S11-0865-Rev. A, 02-May-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Power, Junction-to-Ambient

= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper

J(max)

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This document is subject to change without notice.

5

Si2329DS

10

-3

10

-2

1

10

100010

-1

10

-4

100

0.2

0.1

Square WavePulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1

0.1

0.01

t

1

t

2

Notes:

P

DM

1. Duty Cycle, D =

2. Per Unit Base = R

thJA

=166 °C/W

3. T

JM

-T

A=PDMZthJA

(t)

t

1

t

2

4. Surface Mounted

Duty Cycle = 0.5

Single Pulse

0.02

0.05

10

-3

10

-2

10110

-1

10

-4

0.2

0.1

Duty Cycle = 0.5

Square WavePulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1

0.1

0.01

0.05

Single Pulse

0.02

Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Normalized Thermal Transient Impedance, Junction-to-Ambient

Normalized Thermal Transient Impedance, Junction-to-Foot

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?67690

.

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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

This document is subject to change without notice.

Document Number: 67690

S11-0865-Rev. A, 02-May-11

SOT-23 (TO-236): 3-LEAD

b

3

1

Package Information

Vishay Siliconix

E

E

1

2

S

A

A

2

A

1

Dim

A 0.89 1.12 0.035 0.044

A

1

A

2

b 0.35 0.50 0.014 0.020

c 0.085 0.18 0.003 0.007

D 2.80 3.04 0.110 0.120

E 2.10 2.64 0.083 0.104

E

1

e 0.95 BSC 0.0374 Ref

e

1

L 0.40 0.60 0.016 0.024

L

1

S 0.50 Ref 0.020 Ref

q 3°8°3°8°

ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479

e

e

1

D

0.10 mm

Seating Plane

C

0.004"

C

C

q

L

L

1

MILLIMETERS INCHES

Min Max Min Max

0.01 0.10 0.0004 0.004

0.88 1.02 0.0346 0.040

1.20 1.40 0.047 0.055

1.90 BSC 0.0748 Ref

0.64 Ref 0.025 Ref

0.25 mm

Gauge Plane

Seating Plane

Document Number: 71196
09-Jul-01

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Mounting LITTLE FOOTR SOT-23 Power MOSFETs

Wharton McDaniel

AN807

Vishay Siliconix

Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis

of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.

The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.

ambient air. This pattern uses all the available area underneath the
body for this purpose.

0.114

2.9

0.081

2.05

0.150

3.8

0.059

1.5

0.0394

FIGURE 1. Footprint With Copper Spreading

1.0

0.037

0.95

Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.

Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the

Document Number: 70739
26-Nov-03

A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.

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RECOMMENDED MINIMUM PADS FOR SOT-23

Application Note 826

Vishay Siliconix

0.106
(2.692)

0.037

(0.950)

0.053

(1.341)

0.097

(2.459)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.022

(0.559)

0.049

0.029

(1.245)

(0.724)

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Document Number: 72609 www.vishay.com
Revision: 21-Jan-08 25

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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12

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Document Number: 91000