Datasheet SAA4997H Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA4997H

VErtical Reconstruction IC (VERIC)
for PALplus

Preliminary specification
File under Integrated Circuits, IC02

1996 Oct 24

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for

SAA4997H

PALplus

FEATURES

• PALplus decoding

• Vertical reconstruction

• Quadrature mirror filter

• Luminance and chrominance processing

• Controlling.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

T

amb

ORDERING INFORMATION

TYPE

NUMBER

SAA4997H QFP64

supply voltage − 5.25 V
operating ambient temperature 0 70 °C

NAME DESCRIPTION VERSION

plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm SOT319-2

GENERAL DESCRIPTION

The VErtical Reconstruction IC (VERIC) for PALplus
(VERIC) is especially designed for use in conjunction with
the Motion Adaptive Colour Plus And Control IC
(MACPACIC) to decode the transmitted PALplus video
signal in PALplus colour TV receivers. It provides the full
vertical resolution of a PALplus picture from the letter box
part and the decoded helper information.

PACKAGE

1996 Oct 24 2

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

BLOCK DIAGRAMS

Y_VE_0 to 7

8

36

CLK_32B3

23

CLK_16B2

SAA4997H

UV

F/C

U/V_VE_0/1

4

FORMATTER

bypass

OE_FM2

RSTR_FM23

39

56

54

multi-PIP

OE_FM3

RE_FM2

40

55

TRSTN

TDO_VE

RE_FM3

30

29

BOUNDARY SCAN TEST

28 26 27

SAA4997H



MGE443

handbook, full pagewidth

mode select

F/C

LUMINANCE

(QM-FILTER)

PROCESSING

PIXEL

SELECT

8

multi-PIP

bypass

DELAY

COMPENSATOR

8

8

(LP-FILTER)

PROCESSING

CHROMINANCE

8

8

UV

REFORMATTER

PIXEL

SELECT

4

4

19

5

FM-control

UV-control

Y - UV - FM

Y-control

LINE COUNTER



CONTROL LOGIC

DECODER

PIXEL COUNTER

17

Fig.1 Block diagram.

EVEN_FIELD TDI TCK TMS

INTPOL

21 20 22

FILM

DECODER

Y_FM23_0 to 7

U/V_FM23_0/1

1996 Oct 24 3

VA_AI

HREF_MA

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

Vertical

VERIC

Reconstruction IC

CLK_32B1

U_FM23_0,1

V_FM23_0,1

Y_FM23_0 to 7

4

8

8

4

FM2

TMS4C2970

V_VE_[0,1]

U_VE_[0,1]

8

4

V_VE_0,1

U_VE_0,1

Y_VE_0 to 7 Y_VE_[0 to 7]

8

4

FM3

TMS4C2970

TDO_VE

4

4

DD1-4

V

V

CLK_32B3

OE_FM3

OE_FM2

- Inverse QMF

reconstruction

SS1-4

CLK_16B2

CLK_32B3

RE_FM2

RE_FM3

RSTR_FM23

filter- Vertical

chrominance

FILM

VA_AI

HREF_MA

SRC- FM2/FM3

read control

TDI

TRSTN

INTPOL

EVEN_FIELD

TMS

3

TCK

SAA4997H

MGE444

11

NC

TEST1-3

ok, full pagewidth

CLK_16B1, 2, 3

3

3

MACPACIC

and Control IC

Motion Adaptive Colour Plus

Y_ADC_0 to 7

8

4

8

CLK_32B1, 2, 3

8

Y_FM1_0 to 7

8

TMS4C2970

8

4

U_MA_0,1

Y_MA_0 to 7

U_FM1_0,1

V_FM1_0,1

4

SRCK

FM1

SWCK

4

8

V_MA_0,1

U_ADC_0,1

4

CLK_16 CLK_16B1

(1)

(1)

Y_TO_FM1_0 to 7

U_TO_FM1_0

WE_FM2

U_TO_FM1_1

RSTW_FM23

- BB-decompanding

- Motion adaptive

V_ADC_0,1

5

5

SS1-5

DD1-5

V

V

CLK_16

CLK_32

(1)

WE_FM3

V_TO_FM1_1

V_TO_FM1_0

WE_FM1, RE_FM1

2

luminance/chrominance

separation

- Memory control

CLAMP

VA_FRONT

WE_FRONT

VA_AI

WE_FM4, RE_FM4

RST_FM14

2

- PALplus control

- Clock generation

SNERT_CL

SNERT_DA

SNERT_RST

HREF_MA

WE_MA

FILM

EVEN_FIELD

INTPOL

- Sync generation

- SNERT interface

3

TDI

TCK

TMS

TRSTN

TEST1-3

TDO_MA

4

V_FM4_0,1

U_FM4_0,1

4

V_TO_FM4_0,1

U_TO_FM4_0,1

(2)

VERIC_AV_N

CLK_16B1

FM4

TMS4C2970

Fig.2 Block diagram of the PALplus decoder module.

.

SS

Y_FRONT[0 to 7]

V_FRONT[0,1]

U_FRONT[0,1]

1996 Oct 24 4

(1) In case of stand alone MACPACIC the output signals are U_TO_FM1_1, V_TO_FM1_0 or V_TO_FM1_1; otherwise the output signals are WE_FM2, RSTW_FM23 or WE_FM3.

(2) VERIC available: VERIC_AV_N is connected to V

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for

SAA4997H

PALplus

PINNING

SYMBOL PIN TYPE DESCRIPTION

Y_VE_1 1 output luminance output data bit 1
Y_VE_0 2 output luminance output data bit 0
U_VE_1 3 output chrominance output data bit 1 U-component
U_VE_0 4 output chrominance output data bit 0 U-component
V_VE_1 5 output chrominance output data bit 1 V-component
V_VE_0 6 output chrominance output data bit 0 V-component
V

SS1

V

DD1

n.c. 9 − not connected
n.c. 10 − not connected
n.c. 11 − not connected
n.c. 12 − not connected
n.c. 13 − not connected
n.c. 14 − not connected
n.c. 15 − not connected
n.c. 16 − not connected
HREF_MA 17 input horizontal reference
n.c. 18 − not connected
VA_AI 19 input vertical reference pulse related to output data
INTPOL 20 input INTPOL = 1: PALplus interpolation active

FILM 21 input FILM = 0: CAMERA mode

EVEN_FIELD 22 input EVEN_FIELD = 0: odd field related to MACPACIC input data

CLK_16B2 23 input buffered clock input (16 MHz)
V

SS2

V

DD2

TCK 26 input boundary scan test clock input
TMS 27 input boundary scan test mode select input
TDI 28 input boundary scan test data input
TDO_VE 29 output boundary scan test data output
TRSTN 30 input boundary scan test reset input
n.c. 31 − not connected
n.c. 32 − not connected
TEST1 33 tbf test pins
TEST2 34 tbf
TEST3 35 tbf
CLK_32B3 36 input buffered clock input (32 MHz)
V

SS3

7 input ground 1
8 input positive supply voltage 1 (+5 V)

INTPOL = 0: VERIC switched to bypass mode (standard signal)

FILM = 1: FILM mode

EVEN_FIELD = 1: even field related to MACPACIC input data

24 input ground 2
25 input positive supply voltage 2 (+5 V)

37 input ground 3

1996 Oct 24 5

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

SYMBOL PIN TYPE DESCRIPTION

V

DD3

OE_FM3 39 output output enable field memory 3
RE_FM3 40 output read enable field memory 3
V_FM23_1 41 input chrominance input data bit 1 V-component
V_FM23_0 42 input chrominance input data bit 0 V-component
U_FM23_1 43 input chrominance input data bit 1 U-component
U_FM23_0 44 input chrominance input data bit 0 U-component
Y_FM23_7 45 input Y input data bit 7
Y_FM23_6 46 input Y input data bit 6
Y_FM23_5 47 input Y input data bit 5
Y_FM23_4 48 input Y input data bit 4
Y_FM23_3 49 input Y input data bit 3
n.c. 50 − not connected
Y_FM23_2 51 input Y input data bit 2
Y_FM23_1 52 input Y input data bit 1
Y_FM23_0 53 input Y input data bit 0
RSTR_FM23 54 output reset read field memory 2 and 3
RE_FM2 55 output read enable field memory 2
OE_FM2 56 output output enable field memory 2
V

DD4

V

SS4

Y_VE_7 59 output luminance output data bit 7
Y_VE_6 60 output luminance output data bit 6
Y_VE_5 61 output luminance output data bit 5
Y_VE_4 62 output luminance output data bit 4
Y_VE_3 63 output luminance output data bit 3
Y_VE_2 64 output luminance output data bit 2

38 input positive supply voltage 3 (+5 V)

57 input positive supply voltage 4 (+5 V)
58 input ground 4

SAA4997H

1996 Oct 24 6

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

handbook, full pagewidth

Y_VE_3

Y_VE_4
62

Y_VE_5

Y_VE_6

61

60

SAA4997H

Y_VE_1
Y_VE_0
U_VE_1
U_VE_0
V_VE_1
V_VE_0

V

SS1

V

DD1

n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.

n.c

HREF_MA

n.c.

VA_AI

Y_VE_2
64

63
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19

V

Y_VE_7
59

58

SS4

DD4

V

57

OE_FM2

RE_FM2

56

55

RSTR_FM23

Y_FM23_0

54

53

Y_FM23_1
52

51

50
49
48
47
46
45
44
43
42

41
40
39
38
37
36
35
34
33

Y_FM23_2
n.c.
Y_FM23_3
Y_FM23_4
Y_FM23_5
Y_FM23_6
Y_FM23_7
U_FM23_0
U_FM23_1
V_FM23_0
V_FM23_1
RE_FM3
OE_FM3
V

DD3

V

SS3

CLK_32B3
TEST3
TEST2
TEST1

SAA4997H

20

21

22

23

24

25

SS2

FILM

INTPOL

CLK_16B2

EVEN_FIELD

DD2

V

V

Fig.3 Pin configuration.

1996 Oct 24 7

26

TCK

27

TMS

28

TDI

29

30

TRSTN

TDO_VE

31

n.c.

32

n.c.

MGE442

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

FUNCTIONAL DESCRIPTION
Introduction

As shown in Fig.2 the PALplus module consists of two
special integrated circuits:

• Motion Adaptive Colour Plus And Control IC
(MACPACIC)

• VErtical Reconstruction IC (VERIC)

and four field memories TMS4C2970.
The MACPACIC and the VERIC are intended to generate

digitally decoded 50 Hz YUV signals. The MACPACIC
performs the decompanding function for the helper lines
and the motion adaptive luminance/chrominance
separation. Furthermore, PALplus system controlling,
memory controlling and clock generation are carried out in
this circuit.

The function of the VERIC is to reconstruct the separated
2 × 72 helper lines and the 430 main lines into a standard
576 lines frame according the PALplus system description

“REV 2.0”

576 lines using a vertical sample rate converter.
The data of the VERIC are clocked out with 16 MHz.

The Y :U:V bandwidth ratio is 4:1:1.
The functional block diagram of the VERIC is shown in

Fig.1. The device consists of 3 main parts:

• Luminance processing

• Chrominance processing

• Controlling.

. Chrominance is converted from 430 lines to

SAA4997H

The luminance vertical conversion process in the decoder
is complementary to that of the encoder.

In the decoder the inverse QMF function is implemented to
recombine the two separated sub-bands and to generate
the original video signal with 576 active lines per frame.

Each output line is calculated from up to seven input lines
stored in line memories containing main or helper
information. The various lines are multiplied by switched
coefficients, changing every line within a sequence of four
lines, depending on the specific mode (CAMERA or FILM).

In case of standard PAL reception, the VERIC is switched
to bypass mode controlled by the signal INTPOL.

For multi-PIP processing the VERIC is also switched to
bypass mode, but controlling of FM2/3 is different (see
Fig.6). The total signal delay between the MACPACIC
input and the VERIC output is one line for this mode.
FM2/3 are driven with 32 MHz clock frequency.
The non-multiplexed input data are clocked out with
16 MHz.

Chrominance processing

The chrominance processing is carried out by the vertical
interpolation filter (poly phase filter).

In CAMERA and FILM mode, intra-field vertical sample
rate conversion is carried out.

One output line is calculated out of three or four lines in
CAMERA or FILM mode using different coefficients or
passed through in bypass mode.

The input data are delivered by the field memories FM2
and FM3, which include multiplexed first and second field
data processed by the MACPACIC. The luminance and
chrominance input data of the VERIC are clocked with
32 MHz (CLK_32B3). Internally the device operates at
32 or 16 MHz clock frequency.

Luminance processing

In the PALplus encoder the luminance signal is separated
vertically into two sub-bands by a special Quadrature
Mirror Filter (QMF).

A vertical low-pass sub-band consists of the 430 main
letter box lines per frame, and a vertical high-pass
sub-band includes the 144 helper lines per frame.

The used QMF technique has two advantages:

• Essentially loss-free data processing

• Cancellation of alias components in the main and helper

signal in the decoder.

1996 Oct 24 8

Control functions

The VERIC controller generates the necessary internal
control signals for the line memories, formatters,
reformatters, the selector signals for the multiplexers and
the read signals for the field memories FM2/3.

The system control input signals EVEN_FIELD, INTPOL
and FILM are derived from the control part of the
MACPACIC. The field selection information EVEN_FIELD
is related to the input data of the MACPACIC and is
adapted in the VERIC to its input data.

The control functions are described in Tables 1 and 2.

Table 1 EVEN_FIELD

VALUE STATUS

EVEN_FIELD = 1 even field selected
EVEN_FIELD = 0 odd field selected

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

Table 2 INTPOL and FILM

VALUE STATUS

INTPOL = 0 FILM = 0 bypass mode;

standard signals

INTPOL = 1 FILM = 0 interpolation active;

PALplus CAMERA mode
INTPOL = 0 FILM = 1 bypass mode; multi-PIP
INTPOL = 1 FILM = 1 interpolation active;

PALplus FILM mode

Modes and delays

The PALplus module can operate in two different
hardware configurations:

• Full PALplus configuration (MACPACIC and VERIC)

• Stand alone MACPACIC.

The vertical interpolation of the VERIC can be activated by
the signal INTPOL depending on the PALplus signalling
bits, transmitted in line 23 indicating the type of signal
being received.

However, the delay between input data of the MACPACIC
and output data of the VERIC always has to be 1.5 fields.
This is achieved with a suitable read timing of the field
memories FM2 and FM3 controlled by VA_AI which is
derived from the field length measurement in the
MACPACIC.

In case of INTPOL = LOW and additionally FILM = HIGH
(FILM mode), the VERIC is switched to multi-PIP mode.
In case the delay between input of the MACPACIC and
output of the VERIC is one line (1024 CLK_16 periods).

SAA4997H

Table 3 Delays

MODE FIELD VERIC I/O DELAY

FILM mode first 2 lines

second 3 lines

CAMERA mode first 3 lines

second 4 lines

Input/Output formats

NPUT FORMATS

I
The luminance input range of the main and helper signal

has the following values:

Main signal: black = 16, white = 191 (straight binary)
Helper signal: ±70, mid = 128 (straight binary)
Chrominance format: ±90, mid = 0 (two’s complement).

UTPUT FORMATS

O

Luminance format: black = 16, white = 191 (straight
binary)

Blanking: code 16
Chrominance format: ±90, mid = 0 (two’s complement)
Blanking: code 0.

Test activities

The pins TEST1, TEST2 and TEST3 are provided to
perform the IC test activities, such as scan test.

The pins TRSTN, TDI, TMS, TCK and TDO_VE are
intended for a boundary scan test.

The line and pixel timings of the VERIC are shown in
Figures 5 to 14.

1996 Oct 24 9

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for

SAA4997H

PALplus

DC CHARACTERISTICS

Tj= 0 to 125 °C

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DD

I

DD

I

DD(q)

Inputs

V

IL

V

IH

I

LI

Outputs

V

OL

V

OH

I

OL

I

OH

supply voltage 4.75 5.0 5.25 V
supply current VDD=5V −− 80 mA
quiescent supply current all inputs to VDD or VSS−− 100 µA

LOW level input voltage −0.5 − +0.8 V
HIGH level input voltage 2.0 − V

DD

V

input leakage current −− 1.0 µA

LOW level output voltage IO=20µA −− 0.1 V
HIGH level output voltage IO=20µAV

− 0.1 −−V

DD

LOW level output current VO= 0.5 V 4.0 −−mA
HIGH level output current VO=VDD− 0.5 V 4.0 −−mA

AC CHARACTERISTICS

Tj= 0 to 125 °C

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Clock timing CLK_32B3 (see Fig.4)

T

CY(32)

t

H

t

L

t

r

t

f

∆f

clk

cycle time 28.1 31.25 − ns
HIGH time 9.2 −−ns
LOW time 9.2 −−ns
rise time 2.0 − 4.0 ns
fall time 2.0 − 4.0 ns

deviation of clock frequency −10 − +10 %
Clock timing CLK_16B2 (see Fig.4)
T

CY(16)

t

H

t

L

t

r

t

f

δ duty cycle 40 − 50 %

cycle time 56.2 −−ns

HIGH time 20.5 −−ns

LOW time 20.5 −−ns

rise time 2.0 − 4.0 ns

fall time 4.0 − 4.0 ns

t

H

δ

=

---- ­t

L

1996 Oct 24 10

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for

SAA4997H

PALplus

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Input data timing (CLK_32)

t

su

t

h(i)

Input control timing (CLK_16B2)

HREF_MA, VA_AI, FILM, EVEN_FIELD
t

su

t

h(i)

Output data timing (CLK_16B2)

AND UV_FM23

Y
t

h(o)

t

d(o)

Output control timing (CLK_32B3)

input data set-up time

CLK_16B2 −4.7 −−ns
Y and UV_FM23 −0.8 −−ns

input data hold time

CLK_16B2 5.1 −−ns
Y and UV_FM23 5.2 −−ns

AND INTPOL

input data set-up time 4.5 −−ns

input data hold time 0.1 −−ns

output data hold time CL=15pF 8 −−ns

output data delay time CL=15pF −− 27 ns

OE_FM2, OE_FM3, RE_FM2, RE_FM3
t

h(o)

t

d(o)

output data hold time CL=15pF 5 −−ns

output data delay time CL=15pF −− 20 ns

Delays

t

w(HREF)

t

d(RE)

HREF_MA pulse width − 60 × T

delay

RE_FM2/3 to HREF_MA
t

w(RE)

t

d(VE)(MA)

t

d(VE)

t

d(VE)

t

d(RSTR)

t

d(FM2)

RE_FM2/3 pulse width − 1680 × T

delay HREF_MA to YUV_VE − 80 × T

delay data input to output − 16 × T

delay data input to output multi-PIP − 2 × T

delay RSTR multi-PIP − 2016 × T

delay FM2 input to output multi-PIP − 2040 × T

AND RSTR_FM23

− 127 × T

CY(16)

CY(16)

CY(32)

CY(32)
CY(16)
CY(16)

CY(32)

CY(32)

− ns

− ns

− ns

− ns

− ns

− ns

− ns

− ns

1996 Oct 24 11

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

TIMING

90%
50%
10%

Dn

t

r

t

h(o)

handbook, full pagewidth

CLK

DATA/CONTROL

SAA4997H

t

f

t

H

XX

t

d(o)

t

L

D(n+1)

t

h(i)

t

su

MGE445

Data input: CLK =CLK_32B3
Data output: CLK =CLK_16B2
Control input: CLK =CLK_16B2
Control output: CLK =CLK_32B3

Fig.4 Data/control input/output set-up and hold timing.

1996 Oct 24 12

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

SAA4997H

MGE446

handbook, full pagewidth

w(HREF)

t

w(RE)

t

d(RE)

t

CY(32)

1 × T

d(VE)

t

d(VE)(MA)

t

Fig.5 Pixel timing (except multi-PIP mode).

CLK_32B3

CLK_16B2

HREF_MA

1996 Oct 24 13

RE_FM2/3

Y(U/V)_FM23

Y(U/V)_VE

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

3
3

1122

SAA4997H

MGE447

23

1

d(VE)

t

handbook, full pagewidth

d(RSTW)

t

d(RSTR)

t

d(FM2)

t

33

22

3

2

1

d(MA)

t

11

1024 pixels

Fig.6 Pixel timing multi-PIP mode (MACPACIC input to VERIC output).

VA_AI

CLK_16B2

CLK_32B3

RSTW_FM2

RSTR_FM2

1996 Oct 24 14

YUV_ADC

YUV_MA

YUV_FM2

YUV_VE

WE_FM2 and RE_FM2 are constant HIGH; YUV_MA =MACPACIC input.

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

B

Y839

U1

836B

U0

836B

V1

836B

V0

SAA4997H

MGE448

836B

handbook, full pagewidth

Y0A Y0B Y1A Y1B Y2A Y2B Y3A Y3B Y4A Y4B Y5A Y5B Y6A Y6B Y7A Y7B Y8A Y8B

U70A U50A U30A U10A U70B U50B U30B U10B U74A U54A U34A U14A U74B U54B U34B U14B U78A U58A

U60A U40A U20A U00A U60B U40B U20B U00B U64A U44A U24A U04A U64B U44B U24B U04B U68A U48A

V70A V50A V30A V10A V70B V50B V30B V10B V74A V54A V34A V14A V74B V54B V34B V14B V78A V58A

V60A V40A V20A V00A V60B V40B V20B V00B V64A V44A V24A V04A V64B V44B V24B V04B V68A V48A

field

V 6 0 A

input signal

Fig.7 Input data timing (except multi-PIP mode).

word

bit

CLK_32B3

RE_FM2/3

Y_FM23(0-7)

1996 Oct 24 15

U_FM23_1

U_FM23_0

V_FM23_1

V_FM23_0

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

16

Y

839

0

U1

836

SAA4997H

MGE449

0

U0

836

0

V1

836

0

V0

836

handbook, full pagewidth

Fig.8 Output data timing.

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

16

U70 U50 U30 U10 U74 U54 U34 U14 U78

0

U60 U40 U20 U00 U64 U44 U24 U04 U68

0

V70 V50 V30 V10 V74 V54 V34 V14 V78

0

V60 V40 V20 V00 V64 V44 V24 V04 V68

0

word

V 6 0

input signal

bit

CLK_16B2

Y_VE(0-7)

U_VE_1

1996 Oct 24 16

U_VE_0

V_VE_1

V_VE_0

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

311/623

145 lines

SAA4997H

MGE450

handbook, full pagewidth

20 lines

166/478 167/479

146 lines

multiplexed active lines from FM23

21/333

166 167 311

24232221 25 26 27

Fig.9 Line read timing FM2/3 bypass mode standard signal, first field.

VA_AI

YUV_FM23(0-7)

OE_FM2

1996 Oct 24 17

RE_FM2

OE_FM3

RE_FM3

Y/UV_VE

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

311/623

145 lines

SAA4997H

MGE451

handbook, full pagewidth

19 lines field B

166/478 167/479

146 lines

multiplexed active lines from FM23

21/333

478 479 623

336335334333 337 338 339

Fig.10 Line read timing FM2/3 bypass mode standard signal, second field.

VA_AI

YUV_FM23(0-7)

OE_FM2

1996 Oct 24 18

RE_FM2

OE_FM3

RE_FM3

Y/UV_VE

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

SAA4997H

MGE452

ll pagewidth

21 22 23 24 25 26 27 161 162 163 164 165 166 167 302 303 304 305 306 307 308 309 310

VERIC

line counter

M11,10

(1)

H3,4

M3,2 M5,4H1,2 M7,6 M9,8

Y_FM23

UV11,10

UV3,2 UV5,4 UV7,6 UV9,8

U/V_FM23

OE_FM3

RE_FM3

OE_FM2

RE_FM2

161 162 163 164 165 166 167 302 303 304 305 306 307 308 309 310

Fig.11 Line read timing FM2/3 CAMERA mode, first field.

2423 25 26 27

Y/UV_VE

1996 Oct 24 19

(1) M = main line and H = helper line.

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

SAA4997H

MGE453

handbook, full pagewidth

20 21 22 23 24 25 26 160 161 162 163 164 165 166 301 302 303 304 305 306 307 308 309 310

VERIC

line counter

H3,4

M11,10

M3,2 M5,4 H1,2 M7,6 M9,8

(1)

Y_FM23(0-7)

3,2 5,4 7,6 9,8 11,12

OE_FM3

U/V_FM23(0-1)

RE_FM3

OE_FM2

RE_FM2

476 477 478 479 480 481 482 614 615 616 617 618 619 620 621 622 623

Fig.12 Line read timing FM2/3 CAMERA mode, second field.

336 337 338 339

Y/UV_VE

1996 Oct 24 20

(1) M = main line and H = helper line.

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

SAA4997H

MGE454

handbook, full pagewidth

M11,10

(1)

H3,4

M5,4

H1,2 M7,6 M9,8

M3,2

Y_FM23

UV11,10

UV3,2 UV5,4 UV7,6 UV9,8

U/V_FM23

OE_FM3

RE_FM3

OE_FM2

RE_FM2

162 163 164 165 166 167 168 303 304 305 306 307 308 309 310

Fig.13 Line read timing FM2/3 FILM mode, first field.

252423 26 27 28

Y/UV_VE

1996 Oct 24 21

(1) M = main line and H = helper line.

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

SAA4997H

MGE455

handbook, full pagewidth

M11,10

H3,4

M7,6 M9,8

H1,2

M3,2 M5,4

(1)

Y_FM23(0-7)

OE_FM3

RE_FM3

OE_FM2

RE_FM2

474 475 476 477 478 479 480 615 616 617 618 619 620 621 622 623

Fig.14 Line read timing FM2/3 FILM mode, second field.

336 337 338 339 340

Y/UV_VE

1996 Oct 24 22

(1) M = main line and H = helper line.

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

PACKAGE OUTLINE

QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

c

y

X

51 33

52

32

Z

A

E

SAA4997H

SOT319-2

pin 1 index

64

1

w M

b

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

3.20

0.25

0.05

2.90

2.65

0.25

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

p

D

H

D

cE

0.25

0.14

D

20.1

19.9

p

0.50

0.35

0 5 10 mm

(1)

(1) (1)(1)

14.1

13.9

19

Z

D

scale

eH

H

24.2

1

23.6

20

D

B

e

H

E

w M

b

p

v M

A

v M

B

LLpQZywv θ

E

18.2

17.6

1.0

0.6

A

2

A

E

1.4

1.2

A

1

detail X

0.2 0.10.21.95

Q

(A )

3

θ

L

p

L

Z

E

D

1.2

0.8

o

7

o

0

1.2

0.8

OUTLINE
VERSION

SOT319-2

IEC JEDEC EIAJ

REFERENCES

1996 Oct 24 23

EUROPEAN

PROJECTION

ISSUE DATE

92-11-17
95-02-04

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

(order code 9398 652 90011).

“Quality

(order code 9398 510 63011).

SAA4997H

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

1996 Oct 24 24

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for

SAA4997H

PALplus

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1996 Oct 24 25

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

NOTES

SAA4997H

1996 Oct 24 26

Philips Semiconductors Preliminary specification

VErtical Reconstruction IC (VERIC) for
PALplus

NOTES

SAA4997H

1996 Oct 24 27

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax.[phone]
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Tel. [phone], Fax.[phone]
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220050 MINSK, Tel.[phone],Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 JamesBourchier Blvd., 1407SOFIA,
Tel. [phone], Fax.[phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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Denmark: Prags Boulevard80, PB 1919, DK-2300COPENHAGEN S,

Tel. [phone], Fax.[phone]
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Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400018, Tel. [phone], Fax.[phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax.[phone]
Israel: RAPAC Electronics, 7Kehilat SalonikiSt, TEL AVIV61180,

Tel. [phone], Fax.[phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IVNovembre 3,

20124 MILANO, Tel.[phone],Fax. [phone]
Japan: Philips Bldg13-37, Kohnan 2-chome, Minato-ku, TOKYO108,

Tel. [phone], Fax.[phone]
Korea: Philips House, 260-199Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax.[phone]
Malaysia: No. 76Jalan Universiti, 46200PETALING JAYA, SELANGOR,

Tel. [phone],Fax. [phone]
Mexico: 5900 GatewayEast, Suite 200, ELPASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600PB EINDHOVEN, Bldg.VB,

Tel. [phone], Fax.[phone]
New Zealand: 2 WagenerPlace, C.P.O. Box1041, AUCKLAND,

Tel. [phone], Fax.[phone]
Norway: Box 1, Manglerud0612, OSLO,

Tel. [phone], Fax.[phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 ValeroSt. SalcedoVillage, P.O. Box2108 MCC,MAKATI,
Metro MANILA, Tel.[phone],Fax. [phone]

Poland: Ul. Lukiska10, PL 04-123WARSZAWA,
Tel. [phone], Fax.[phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva35A, 119048 MOSCOW,

Tel. [phone], Fax.[phone]
Singapore: Lorong 1, ToaPayoh, SINGAPORE 1231,

Tel. [phone],Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 MainRoad Martindale,

2092 JOHANNESBURG, P.O.Box 7430 Johannesburg2000,
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South America: Rua doRocio 220, 5thfloor, Suite 51,
04552-903 SãoPaulo, SÃO PAULO- SP, Brazil,
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Spain: Balmes 22, 08007BARCELONA,
Tel. [phone], Fax.[phone]

Sweden: Kottbygatan 7, Akalla, S-16485STOCKHOLM,
Tel. [phone], Fax.[phone]

Switzerland: Allmendstrasse 140, CH-8027ZÜRICH,
Tel. [phone], Fax.[phone]

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung HsiaoWest Road,Sec. 1, P.O.Box 22978,
TAIPEI 100,Tel. [phone], Fax.[phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-BangnaRoad Prakanong, BANGKOK10260,
Tel. [phone], Fax.[phone]

Turkey: Talatpasa Cad. No. 5, 80640GÜLTEPE/ISTANBUL,
Tel. [phone], Fax.[phone]

Ukraine: PHILIPS UKRAINE, 4 PatriceLumumba str., Building B, Floor7,
252042 KIEV, Tel.[phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 BathRoad, Hayes,
MIDDLESEX UB35BX, Tel. [phone], Fax.[phone]

United States: 811 EastArques Avenue, SUNNYVALE, CA94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing &Sales Communications,
Building BE-p, P.O.Box 218, 5600MD EINDHOVEN, TheNetherlands, Fax.[phone]

© Philips Electronics N.V. 1996 SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 537021/1200/01/pp28 Date of release: 1996 Oct 24 Document order number: 9397 750 01423