Datasheet SAA4995WP-V1 Datasheet (Philips)

DATA SH EET

Preliminary specification
File under Integrated Circuits, IC02

1997 Jun 10

INTEGRATED CIRCUITS

SAA4995WP

PANorama-IC (PAN-IC)

1997 Jun 10 2

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

FEATURES

• Horizontal sample rate conversion in both zoom and
compress direction, with a sample rate conversion factor
between 0.5 and 2 (in 384 steps)

• Dynamic sample rate conversion for panorama mode
display e.g. 4 : 3 material on a 16 : 9 display

• Dynamic sample rate conversion for amaronap mode
display of e.g. 16 : 9 material on a 4 : 3 display

• Operates with 1fh and 2f

h

• Programmable via microcontroller SNERT
(Synchronous No parity Eight bit Receive Transmit) bus.

GENERAL DESCRIPTION

The PAN-IC is an add-on IC to be used, for example,
between analog-to-digital conversion and a serial (field)
memory. The device performs the following tasks:

• Linear horizontal sample rate conversion in both zoom
and compress direction, with a sample rate conversion
factor between 0.5 and 2

• Dynamic sample rate conversion for panorama mode
display of e.g. 4 : 3 material on a 16 : 9 display

• Dynamic sample rate conversion for amaronap mode
display of e.g. 16 : 9 material on a 4 : 3 display.

The PAN-IC has the ability to increase the data rate from
the ADC to a maximum of twice the data rate at the output.
To achieve this a clock rate at twice the normal output
clock rate is needed to write data to the memory.
All actions to generate a lower data rate, produces disable
cycles in Write Enable (WE).

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DD

supply voltage 4.5 5 5.5 V

I

DD

supply current − 110 − mA

f

CLK

operating clock frequency −−33 MHz

T

amb

operating ambient temperature 0 − 70 °C

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

SAA4995WP PLCC44 plastic leaded chip carrier; 44 leads SOT187-2

1997 Jun 10 3

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGK176

37 to 44

Y

I7

to

Y

I0

WE

I

WE

O

WE

od

5 31

SECAM
NOTCH

CL16

7

SNDA

34

SNCL

35

VRST

36

LINE CONTROL

SNERT BUS INTERFACE

X0rX0IX1rX1IX2rX

2I

SPL

init

notch

out-phase

in-phase

29 to 22

21 to 18

1 to 4

UI1/U

I0

and

VI1/V

I0

Y

O7
to

Y

O0

VO0/V

O1

and

UO0/U

O1

CL16

CLK

∆Y∆UV

CL16

CLK

8 9

TEST

SCANIN

10 12

V

DD1

GND1

15 16

V

DD2

GND2

33 30

V

DD3

GND3

6 32

V

DD4

GND4

CL16 CLK

CLK

MUX

notch

SAA4995WP

VPD

FRONT-END

VPD

BACK-END

VPD

FRONT-END

VPD

BACK-END

17

14

T1
T0

13
11

INTEGRATOR

DTO

INTEGRATORMUX

C

2

C

0

'0'

C

1

C1

C0

C2

+

1997 Jun 10 4

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

PINNING

SYMBOL PIN DESCRIPTION

U

I1

1 U input bit 1

U

I0

2 U input bit 0

V

I1

3 V input bit 1

V

I0

4 V input bit 0
CL16 5 half system clock
V

DD4

6 supply voltage 4
WE

I

7 write enable input
TEST 8 test mode switch
SCANIN 9 input for scan chain
V

DD1

10 supply voltage 1
T0 11 test mode switch 0
GND1 12 ground 1
T1 13 test mode switch 1
WE

od

14 write enable odd samples
V

DD2

15 supply voltage 2
GND2 16 ground 2
WE

O

17 write enable output
V

O0

18 V output bit 0
V

O1

19 V output bit 1
U

O0

20 U output bit 0
U

O1

21 U output bit 1
Y

O0

22 luminance output bit 0
Y

O1

23 luminance output bit 1

Y

O2

24 luminance output bit 2

Y

O3

25 luminance output bit 3

Y

O4

26 luminance output bit 4

Y

O5

27 luminance output bit 5

Y

O6

28 luminance output bit 6

Y

O7

29 luminance output bit 7
GND3 30 ground 3
CLK 31 system clock
GND4 32 ground 4
V

DD3

33 supply voltage 3
SNDA 34 data input from interface

SNERT bus

SNCL 35 clock input from interface

SNERT bus

VRST 36 reset input in the vertical

blanking interval

Y

I7

37 luminance input bit 7
Y

I6

38 luminance input bit 6
Y

I5

39 luminance input bit 5
Y

I4

40 luminance input bit 4
Y

I3

41 luminance input bit 3
Y

I2

42 luminance input bit 2
Y

I1

43 luminance input bit 1
Y

I0

44 luminance input bit 0

SYMBOL PIN DESCRIPTION

1997 Jun 10 5

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

Fig.2 Pin configuration.

handbook, full pagewidth

12
13
14
15
16
17

7
8

9
10
11

39
38
37
36
35
34
33
32
31
30
29

18

19

20

21

22

23

24

25

26

27

28

6

5

4

3

2

1

44

43

42

41

40

SAA4995WP

MGK175

Y

I5

Y

I6

Y

I7

VRST

SDNA
V

DD3

GND4
CLK
GND3
Y

O7

WE

I

TEST

SCANIN

V

DD1

T0

GND1

WE

od

V

DD2

WE

O

SNCL

CL16

VI0VI1UI0UI1Y

I0

YI2YI3Y

I4

V

DD4

Y

I1

V

O1UO0UO1YO0YO1YO2

YO4YO5Y

O6

V

O0

Y

O3

T1

GND2

FUNCTIONAL DESCRIPTION

The PAN-IC is an add-on IC to be used, for example,
between analog-to-digital conversion and a serial (field)
memory. The device performs the following tasks:

• Linear horizontal sample rate conversion in both zoom
and compress direction, with a sample rate conversion
factor between 0.5 and 2

• Dynamic sample rate conversion for panorama mode
display of e.g. 4 : 3 material on a 16 : 9 display

• Dynamic sample rate conversion for amaronap mode
display of e.g. 16 : 9 material on a 4 : 3 display.

The PAN-IC has the ability to increase the data rate from
the ADC (maximum 16 MHz in a 16/32 MHz concept) to a
maximum of twice the data rate. For this, a 32 MHz clock
rate is needed to write to the memory. All actions to
generate a lower data rate produces disable cycles in write
enable.

In panorama and amaronap modes, the sample rate
conversion factor is modulated along the video line.

In the centre of the line a high quality compression (e.g.
with a factor

4

⁄3) has to be made. Towards the sides of the

line, more and more expansion and compression
respectively is made. The sample rate conversion factor
over a line will have a bathtub shape, with parameters
illustrated in Fig.3:

• X0l and X0r, where in-between a constant data rate is
maintained (area I) and starting points from where a
curve can be programmed for its 2nd derivative (in
areas II and V)

• X1l and X1r, points from where a new curve can be
programmed for its 2nd derivative (for areas III and IV)

• X2l corresponds to the first sample in the output data
stream, defined by start of WE

I

• X2r corresponds to the last sample in the output data
stream, defined by the programmed number of samples

• C1, which controls the second derivatives of the data
rate in areas II and V

• C2, which controls the second derivatives of the data
rate in areas III and IV.

1997 Jun 10 6

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

Interpolation function

The interpolation for phase positions between the original
samples, is achieved with a variable phase delay filter with
10 taps for luminance signals and 4 taps for chrominance
signals. For luminance the PAN-IC supplies samples up to
32 MHz. For chrominance the PAN-IC supplies each
U and V samples with a data rate of 8 MHz (max).

Processing control in the PAN-IC

The compress factor (see Fig.4) at any position in the lines
is a function of the dynamically changing DTO-increment.
When DTO

incr

= 255, the sample rate is divided by 2; when

DTO

incr

= 0, the sample rate in the PAN-IC remains

unchanged; when DTO

incr

= −128, the sample rate is

doubled.

Control of number of samples per line

Three possibilities exist for the relationship between the
end of WE

I

and the required number of samples per line for

storage in the field memory:

• WEI negative edge coincides with the required last
sample in the line; standard operation.

• WEI negative edge is reached before the present last
sample in the line was required; extra dummy WE cycles
will be generated at the maximum rate (zoom factor 2)
to arrive at the required number of samples per line.

• The required number of samples per line is reached
before WEI negative edge; the DTO calculations will
continue until the required number of samples is
reached, but without generation of WE cycles.

The programmed number of samples per line is thus
always realized, independent of all other controls (unless
the line period becomes insufficient to store up to the last
sample in a line). When using odd/even sample
distribution, the programmed number of samples refers to
the number of samples in each data stream.
Consequently, the total number of samples is twice as
many.

There is an offset in the programmed number of samples
compared to the effective number of samples per line.

• Effective number of Y samples = 4 × (programmed
number of samples + 1)

• Effective number of UV samples = 1 × (programmed
number of samples + 1)

SECAM Y notch

A notch filter at the Y input of the PAN-IC can be switched
on. The purpose of this filter is to prevent artefacts from
scan velocity modulation with SECAM inputs. The notch
filter is an FIR filter with coefficients (−103030−1).
When fs= 16 MHz, the notch frequency is 4 MHz; the
maximum gain of the filter is +3 dB at 2 and 6 MHz.

Timing

The inputs are related to CL16 (half system clock). This
clock is used for reference in the PAN-IC from the CL16
pin. The system clock must have a fixed phase relationship
to the CL16 enable signal (one clock system).

Relationship of WE to video data

WE inputs and outputs may be used with either coincident
or advanced WE to video timing (see Fig.5). The advanced
WE to video timing is applicable to field memories, such as
the SAA4955TJ. The input and output WEs of the PAN-IC
can be programmed separately to either timing by the
in-phase and out-phase bits.

Odd/even sample distribution

The PAN-IC usually delivers a complete YUV data stream
to one receiving device, e.g. a field memory. Optionally, a
data stream can be split into odd and even samples, to be
received by two receiving devices.

The relationship between Y and UV samples is then
non-trivial (see Tables 1 to 4).

1997 Jun 10 7

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

NO SPLITTING INTO ODD AND EVEN SAMPLE STREAM
Table 1 Normal output YUV data stream

S

PLITTING INTO ODD AND EVEN SAMPLE STREAM

Keeps corresponding parts of the UV samples in one stream (UV0, UV8, etc. in even stream and UV4, UV12, etc. in odd
stream): The odd data stream misses two samples at the start of a line and has two dummy samples at the end of the
line, to keep the UV format correct and maintain the same line length as for the even stream (In the odd stream, the last
two Y samples and the last U and V samples of a line are not valid).

Table 2 Even YUV data stream

Table 3 Odd YUV data stream

The even and odd data streams given in Tables 2 and 3 can be distributed to two receiving devices with input enable
facilities. A separate input signal for each of the receiving devices must then be applied while the even YUV data stream
and odd YUV data stream are again combined.

C

OMBINED ODD/EVEN OUTPUT YUV DATA STREAM

Table 4 Distribution with odd/even input enable signals

EOEOEOEOEOEOE

Y

0

Y

1

Y

2

Y

3

Y

4

Y

5

Y

6

Y

7

Y

8

Y

9

Y10Y

11

Y

12

UV

76

0

UV

54

0

UV

32

0

UV

10

0

UV

76

4

UV

54

4

UV

32

4

UV

10

4

UV

76

8

UV

54

8

UV

32

8

UV

10

8

UV

76

12

E − E − E − E − E − E − E

Y

0

− Y

2

− Y

4

− Y

6

− Y

8

− Y

10

− Y

12

UV

76

0

− UV

54

0

− UV

32

0

− UV

10

0

− UV

76

8

− UV

54

8

− UV

32

12

−−−−−O−O−O−O−

−−−−−Y

5

−Y

7

−Y

9

−Y11−

−−−−−UV

76

4

− UV

54

4

− UV

32

4

− UV

10

4

−

E − E − E − EOEOEOE

Y

0

−Y

2

−Y

4

Y

5

Y

6

Y

7

Y

8

Y

9

Y10Y

11

Y

12

UV

76

0

− UV

54

0

− UV

32

0

UV

76

4

UV

10

0

UV

54

4

UV

75

8

UV

32

4

UV

54

8

UV

10

4

UV

32

8

1997 Jun 10 8

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

Fig.3 Panorama mode.

handbook, full pagewidth

MGK177

IV

X

2I

C

2

area:

active period

sample

rate

V

X

1I

C

1

I

X

0I

C

0

II

X

0r

C

1

III

X

1r

C

2

X

2r

positions:

Fig.4 Compress factor.

handbook, full pagewidth

MGK178

0.5

1

compress

factor

−256 −128 0
DTO

incr

256

2

1997 Jun 10 9

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. Human body model: C = 100 pF, R = 1.5 kΩ, V = 2 kV.

2. Machine model: C = 200 pF, R = 0 Ω, V = 300 V.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

supply voltage −0.5 +6.5 V

V

i

, V

o

input and output voltages −0.5 VDD+ 0.5 V

I

o/out

output current per output pin − 20 mA
P/out power dissipation per output pin − 100 mW
T

stg

storage temperature −55 +140 °C
T

amb

operating ambient temperature −40 +85 °C
V

ESD

electrostatic handling for all pins note 1 −±2000 V

note 2 −±300 V

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 50 K/W

Fig.5 WE timing.

handbook, full pagewidth

MGK179

CL16

WE

I

WE

I

YUV

I

with in-phase = 0

with in-phase = 1

CLK

WEO/WE

od

WEO/WE

od

YUV

O

with out-phase = 0

with out-phase = 1

1997 Jun 10 10

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

CHARACTERISTICS

V

DD

= 5.0 V; T

amb

=25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

supply voltage 4.5 5 5.5 V

I

DD

supply current − 110 − mA

f

CLK

operating frequency (CLK) −−33 MHz

f

CL16

operating frequency (CL16) −

1

⁄2f

CLK

− MHz

V

IL

LOW level input voltage −−0.8 V

V

IH

HIGH level input voltage 2.0 − V

DD

V

C

i

input capacitance − 10 15 pF

V

OL

LOW level output voltage Io=4mA −−0.4 V

V

OH

HIGH level output voltage Io= −4 mA 2.6 3.4 − V

t

su(i)(D)

input set-up time with respect to CL16
rising edge

except pins SNDA, SNCL,
VRST and CLK; see Fig.6

8 −−ns

t

h(i)(CL16)

input hold time with respect to CL16
rising edge

except pins SNDA, SNCL,
VRST and CLK; see Fig.6

0 −−ns

t

su(i)(CL16)

input set-up time with respect to CLK
rising edge

see Fig.6 7 −−ns

t

h(i)(CL16)

input hold time with respect to CLK
rising edge

see Fig.6 3 −−ns

t

h(o)

output hold time with respect to CLK CL= 7 pF 5 −−ns

t

d

output delay time with respect to CLK CL=15pF −−19 ns

T

amb

operating ambient temperature 0 − 70 °C

T

j

junction temperature −−125 °C

Fig.6 Clock timing.

handbook, full pagewidth

MGK180

CL16

CLK

data
input

data
output

data validdata valid

t

su(i)(D)

t

d

t

h(o)

t

h(i)(D)

t

h(i)(CL16)

t

su(i)(CL16)

t

su(i)(CL16)

t

h(i)(CL16)

1997 Jun 10 11

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

MICROCONTROLLER BUS TIMING (SNERT BUS)

MICROCONTROLLER BUS CONTROL (SNERT BUS)

The following control table applies (Table 5), for control via the microcontroller bus (SNERT bus, consisting of SNCL,
SNDA and VRST signals). Data communication is by writing to the PAN-IC (address 40H to 48H) and reading from it
(address 49H)

Table 5 SNERT-bus control

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

T

cy(SNCL)

SNCL cycle time see Fig.7 1 −µs

t

su(i)

input data set-up time see Fig.7 90 − ns

t

h(i)

input data hold time see Fig.7 50 − ns

t

h(o)(D)

output data hold time see Fig.7 0 − ns

t

d

output data delay time see Fig.7 − 700 ns

ADDRESS

(HEX)

FUNCTION # OF BITS

BIT

POSITION

REMARKS

40 X

1l

8 7 : 0 definition of X1l with a resolution of 4 samples; see Fig.3 and

note 1

41 X

0l

8 7 : 0 definition of X0l with a resolution of 4 samples; see Fig.3 and

note 1

42 X

0r

8 7 : 0 definition of X0r with a resolution of 4 samples; see Fig.3 and

note 1

43 X

1r

8 7 : 0 definition of X1r with a resolution of 4 samples; see Fig.3 and

note 1

44 output samples

per line

8 7 : 0 resolution of 4 luminance samples; actual #

samples = (programmed # samples + 1) × 4; note 2

Fig.7 SNERT bus interface timing.

handbook, full pagewidth

MGK181

SNCL

LSB

SNDA
(receiver
mode)

SNDA
(transmitter
mode)

data
valid

data
valid

data
valid

data
valid

data
valid

t

su(i)

t

h(i)

t

h(o)(D)

t

d

T

cy(SNCL)

1997 Jun 10 12

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

Notes

1. For a symmetrical bathtub curve Xnl+Xnr= output samples per line + 1.

2. WEI falling edge delay to the WEO latest sample should not be equal to the pipeline delay. This can be controlled
with the WEI length via the microcontroller.

TEST

The test mode can be chosen via pins TEST, T0 and T1.

Table 6 Test modes

Note

1. X = don’t care.

45 C

0

8 7 : 0 constant DTO

incr

value for area I, MSB extended by zoom bit

at address 48 (twos complement value); see Figs 3 and 4

46 C

1

6 5 : 0 2nd derivatives for DTO

incr

for areas II and V

(twos complement value); see Figs 3 and 4

distribution 1 6 enables odd/even sample distribution; see Tables 1 to 4

47 C

2

6 5 : 0 2nd derivatives for DTO

incr

for areas III and IV

(twos complement value)
test 1 1 6 test bit, must be logic 0 in normal operation
notch 1 7 SECAM Y notch on/off (logic 1 = on, logic 0 = off)

48 zoom bit 1 0 logic 1 = zoom, logic 0 = compress in area I

in-phase 1 1 logic 1 = shifted relation WE_IN to input data; see Fig.5

out-phase 1 2 logic 1 = shifted relation WE

O

/WEod to output data; see Fig.5

init 1 3 circuitry is initialized at VRST pulse

vrst_xfer 1 4 new settings are activated at VRST pulse

keep 1 5 compression curve is kept from last active line in field
test 2 1 6 test bit, must be logic 0 in normal operation
adapt 1 7 adapt bit, must be logic 0 in normal operation

49 identify read 8 read bits 7 : 0 PAN-IC identifies by pulling all bits LOW (hardware cluck)

MODE

PIN NAME

TEST T1 T0

Functional test 0 X

(1)

X

(1)

Test mode on 1 X

(1)

X

(1)

ADDRESS

(HEX)

FUNCTION # OF BITS

BIT

POSITION

REMARKS

1997 Jun 10 13

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

PACKAGE OUTLINE

UNIT A

A

min. max. max. max. max.

1

A

4

b

p

E

(1)

(1) (1)

eH

E

Z

ywv β

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

4.57

4.19

0.51

3.05

0.53

0.33

0.021

0.013

16.66

16.51

1.27

17.65

17.40

0.51

2.16
45

o

0.18 0.100.18

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

Note

1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.

SOT187-2

D

(1)

16.66

16.51

H

D

17.65

17.40

E

Z

2.16

D

b

1

0.81

0.66

k

1.22

1.07

k

1

0.180

0.165

0.020

0.12

A

3

0.25

0.01

0.656

0.650

0.05

0.695

0.685

0.020

0.085

0.007 0.0040.007

L

p

1.44

1.02

0.057

0.040

0.656

0.650

0.695

0.685

e

E

e

D

16.00

14.99

0.630

0.590

16.00

14.99

0.630

0.590

0.085

0.032

0.026

0.048

0.042

2939

44

1

6

717

28

18

40

detail X

(A )

3

b

p

w M

A

1

A

A

4

L

p

b

1

β

k

1

k

X

y

e

E

B

D

H

E

e

E

H

v M

B

D

Z

D

A

Z

E

e

v M

A

pin 1 index

112E10 MO-047AC

0 5 10 mm

scale

92-11-17
95-02-25

inches

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

D

e

1997 Jun 10 14

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all PLCC
packages.

The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

“Quality

Reference Handbook”

(order code 9398 510 63011).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1997 Jun 10 15

Philips Semiconductors Preliminary specification

PANorama-IC (PAN-IC) SAA4995WP

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of this specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1997 SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Netherlands: Postbus 90050, 5600PB EINDHOVEN, Bldg. VB,
Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,
Tel. [phone], Fax. [phone]

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Rua do Rocio 220, 5th floor, Suite 51,
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Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: seeAustria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]
Middle East: see Italy

Printed in The Netherlands 547047/20/01/pp16 Date of release: 1997 Jun 10 Document order number: 9397 750 01609