Datasheet SA8026DH Datasheet (Philips)

INTEGRATED CIRCUITS

SA8026

2.5GHz low voltage fractional-N
dual frequency synthesizer

Product specification
Supersedes data of 1999 Apr 16

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1999 Nov 04

Philips Semiconductors Product specification

TYPE NUMBER

2.5GHz low voltage fractional-N dual frequency
synthesizer

GENERAL DESCRIPTION

The SA8026 BICMOS device integrates programmable dividers,
charge pumps and a phase comparator to implement a
phase-locked loop. The device is designed to operate from 3 NiCd
cells, in pocket phones, with low current and nominal 3 V supplies.

The synthesizer operates at VCO input frequencies up to 2.5 GHz.
The synthesizer has fully programmable main, auxiliary and
reference dividers. All divider ratios are supplied via a 3-wire serial
programming bus.

Separate power and ground pins are provided to the analog and
digital circuits. The ground leads should be externally short-circuited
to prevent large currents flowing across the die and thus causing
damage. V

The charge pump current (gain) is set by an external resistance at
R

pin. Passive loop filters could be used; the charge pump

SET

operates within a wide voltage compliance range to provide a wider
tuning range.

FEA TURES

•Low phase noise

•Low power

•Fully programmable main and auxiliary dividers

•Normal & Integral charge pumps outputs

•Fast Locking Adaptive mode design

•Internal fractional spurious compensation

•Hardware and software power down

•Split supply for V

must be greater than or equal to V

DDCP

and V

DD

DDCP

DD

.

APPLICATIONS

•350 to 2500 MHz wireless equipment

•Cellular phones (all standards)

•WLAN

•Portable battery-powered radio equipment.

LOCK
TEST

RFin+
RFin–

GND

GND

V

GND

PHP

PHI

1
2
3

DD

4
5
6
7

CP

8
9

10

CP

20
19
18
17
16
15
14
13
12
11

PON
STROBE
DATA
CLOCK

REFin+
REFin–
R
V
AUXin

PHA

Figure 1. Pin Configuration

SA8026

SET

DDCP

SR01649

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

V

DDCP

I

DDCP+IDD

I

DDCP+IDD

f

VCO

f

AUX

f

REF

f

PC

T

amb

Supply voltage 2.7 – 5.5 V
Analog supply voltage V

DDCP

w

V

DD

2.7 – 5.5 V
Total supply current Main and Aux. on – 10 12 mA
Total supply current in power-down mode – 1 – µA
Input frequency 350 – 2500 MHz
Input frequency 20 – 550 MHz
Crystal reference input frequency 5 – 40 MHz
Maximum phase comparator frequency – 4 MHz
Operating ambient temperature –40 – +85 °C

PACKAGE
NAME DESCRIPTION VERSION

SA8026DH TSSOP20 Plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360–1

1999 Nov 04 853–2141 22633

2

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N dual frequency
synthesizer

CLOCK

DATA

STROBE

RFin+
RFin–

REFin+
REFin–

17
18

19

5
6

AMP

16

15

2–BIT SHIFT

REGISTER

ADDRESS DECODER

LOAD SIGNALS

LATCH

REFERENCE

DIVIDER

22–BIT SHIFT

REGISTER

LATCH

MAIN DIVIDER

CONTROL

LATCH

SM

2222

SA

V

DD

3

PUMP

CURRENT

SETTING

PUMP

BIAS

COMP

PHASE

DETECTOR

V

DDCP

13

SA8026

14

R

SET

8

PHP

9

PHI

1

LOCK

TEST

12

AMP

2

AUX DIVIDER

AUXin

PINNING

SYMBOL PIN DESCRIPTION

LOCK 1 Lock detect output
TEST 2 Test (should be either grounded or

V

DD

GND 4 Digital ground
RFin+ 5 RF input to main divider
RFin– 6 RF input to main divider
GND

CP

PHP 8 Main normal charge pump
PHI 9 Main integral charge pump
GND

CP

connected to VDD)

3 Digital supply

7 Charge pump ground

10 Charge pump ground

LATCH

4

GND

Figure 2. Block Diagram

SYMBOL PIN DESCRIPTION

PHA 11 Auxiliary charge pump output
AUXin 12 Input to auxiliary divider
V

DDCP

R

SET

REFin– 15 Reference input
REFin+ 16 Reference input
CLOCK 17 Programming bus clock input
DATA 18 Programming bus data input
STROBE 19 Programming bus enable input
PON 20 Power down control

PHASE

DETECTOR

7, 10
GND

CP

11

20

PHA

PON

SR01496

13 Charge pump supply voltage
14 External resistor from this pin to ground

sets the charge pump current

1999 Nov 04

3

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N dual frequency

SA8026

synthesizer

Limiting values

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

V

DDCP

∆V

DDCP–VDD

V

n

V

n

∆V

GND

T

stg

T

amb

T

j

Handling

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal
precautions appropriate to handling MOS devices.

Digital supply voltage –0.3 +5.5 V
Analog supply voltage –0.3 +5.5 V
Difference in voltage between V
Voltage at pins 1, 2, 5, 6, 12, 15 to 20 –0.3 V
Voltage at pin 8, 9, 11 –0.3 V
Difference in voltage between GNDCP and GND (these pins should be

connected together)
Storage temperature –55 +125
Operating ambient temperature –40 +85
Maximum junction temperature 150

DDCP and

VDD (V

≥ VDD) –0.3 +2.8 V

DDCP

+ 0.3 V

DD
DDCP

–0.3 +0.3 V

+ 0.3 V

_C
_C
_C

Thermal characteristics

SYMBOL PARAMETER VALUE UNIT

R

th j–a

Thermal resistance from junction to ambient in free air 135 K/W

1999 Nov 04

4

Philips Semiconductors Product specification

S

V

AC-coupled input signal level

in

()

S

2.5GHz low voltage fractional-N dual frequency
synthesizer

CHARACTERISTICS

V

DDCP

SYMBOL

= V

= +3.0V, T

DD

PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply; pins 3, 13

V

DD

V

DDCP

I

DDTotal

I

Standby

Digital supply voltage 2.7 – 5.5 V
Analog supply voltage V
Synthesizer operational total supply current V

Total supply current in power-down mode logic levels 0 or VDD – 1 – µΑ

RFin main divider input; pins 5, 6

f

VCO

V

RFin(rms)

Z

IRFin

C

IRFin

N

main

f

PCmax

VCO input frequency 350 – 2500 MHz
AC-coupled input signal level Rin (external) = Rs = 50Ω;

Input impedance (real part) f
Typical pin input capacitance f
Main divider ratio 512 – 65535
Maximum loop comparison frequency indicative, not tested – – 4 MHz

AUX reference divider input; pin 12

f

AUXin

AUXin

Z

AUXin

C

AUXin

N

AUX

Input frequency range 20 – 550 MHz

Input impedance (real part) f
Typical pin input capacitance f
Auxiliary division ratio 128 – 16383

Reference divider input; pins 15, 16

f

REFin

V

RFin

Z

REFin

C

REFin

R

REF

Input frequency range from TCXO 5 – 40 MHz
AC-coupled input signal level single-ended drive;

Input impedance (real part) f
Typical pin input capacitance f
Reference division ratio SA = SM = ”000” 4 – 1023

Charge pump current setting resistor input; pin 14

R

SET

V

SET

External resistor from pin to ground 6 7.5 15 kΩ
Regulated voltage at pin R

Charge pump outputs (including fractional compensation pump); pins 8, 9, 11; R

I

CP

I

MATCH

I

ZOUT

I

LPH

V

PH

Charge pump current ratio to I
Sink-to-source current matching VPH = 1/2 V
Output current variation versus V
Charge pump off leakage current VPH = 1/2 V
Charge pump voltage compliance 0.7 – V

= +25°C; unless otherwise specified.

amb

p

p

1

SET

PH

V

w

DDCP
DD

(with main and aux on)

DD

= +3.0V

single-ended drive;
max. limit is indicative
@ 500 to 2500 MHz

= 2.4 GHz – 300 – Ω

VCO

= 2.4 GHz – 1 – pF

VCO

Rin (external) = R
max. limit is indicative

= 500 MHz – 3.9 – kΩ

VCO

= 500 MHz – 0.5 – pF

VCO

max. limit is indicative

= 20 MHz – 10 – kΩ

REF

= 20 MHz – 1 – pF

REF

= 7.5 kΩ – 1.25 – V

SET

Current gain = IPH/I

DDCP

2

V

in compliance range –10 +10 %

PH

DDCP

= 50Ω;

= 7.5 kΩ, FC = 80

SET

SET

SA8026

2.7 – 5.5 V
– 10 12 mA

–18 – 0 dBm

–18 – 0 dBm

80 – 632 mV

360 – 1300 mV

–15 +15 %
–10 +10 %

–10 +10 nA

–0.8 V

DDCP

PP

PP

1999 Nov 04

5

Philips Semiconductors Product specification

f

REF

13MHz, TCXO

L

f

REF

44MHz, TCXO

2.5GHz low voltage fractional-N dual frequency

SA8026

synthesizer

CHARACTERISTICS (continued)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Phase noise (condition R

Synthesizer’s contribution to close-in phase noise
of 900 MHz RF signal at 1 kHz offset.

Synthesizer’s contribution to close-in phase noise
of 1800 MHz RF signal at 1 kHz offset.

(f)

Synthesizer’s contribution to close-in phase noise
of 800 MHz RF signal at 1 kHz offset.

Synthesizer’s contribution to close-in phase noise
of 2100 MHz RF signal at 1 kHz offset.

Interface logic input signal levels; pins 2, 17, 18, 19, 20

V

IH

V

IL

I

LEAK

HIGH level input voltage 0.7*V
LOW level input voltage –0.3 – 0.3*V
Input leakage current logic 1 or logic 0 –0.5 – +0.5 µA

Lock detect output signal (in push/pull mode); pin 1

V

OL

V

OH

LOW level output voltage I
HIGH level output voltage I

NOTES:

V

SET

1. I

SET =

bias current for charge pumps.

R

SET

2. The relative output current variation is defined as:

= 7.5 kΩ, CP = 00)

SET

– –90 – dBc/Hz

– –83 – dBc/Hz

f

COMP

=

=

= 1MHz

GSM

,

indicative, not tested

– –85 – dBc/Hz

– –77 – dBc/Hz

f

COMP

=

= 19.

= 240kHz

TDMA

,

indicative, not tested

DD

= 2mA – – 0.4 V

sink

= –2mA VDD–0.4 – – V

source

– VDD+0.3 V

DD

V

DI

OUT

I

OUT

+ 2

.

I(I

(I2–I1)

) I1)I

2

I

ZOUT

; with V1+ 0.7V, V2+ V

CURRENT

I

2

I

1

I

2

I

1

–0.8V (See Figure 3.)

DDCP

V

1

V

V

2

PH

SR00602

Figure 3. Relative Output Current Variation

1999 Nov 04

6

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N dual frequency
synthesizer

FUNCTIONAL DESCRIPTION

Main Fractional-N divider

The RFin inputs drive a pre-amplifier to provide the clock to the first
divider stage. For single ended operation, the signal should be fed to
one of the inputs while the other one is AC grounded. The
pre-amplifier has a high input impedance, dominated by pin and pad
capacitance. The circuit operates with signal levels from –18 dBm to
0 dBm, and at frequencies as high as 2.5 GHz. The divider consists
of a fully programmable bipolar prescaler followed by a CMOS
counter. Total divide ratios range from 512 to 65536.

At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator. Also,
the fractional accumulator is incremented by the value of NF. The
accumulator works with modulo Q set by FMOD. When the
accumulator overflows, the overall division ratio N will be increased
by 1 to N + 1, the average division ratio over Q main divider cycles
(either 5 or 8) will be

Nfrac + N )

The output of the main divider will be modulated with a fractional
phase ripple. The phase ripple is proportional to the contents of the
fractional accumulator and is nulled by the fractional compensation
charge pump.

The reloading of a new main divider ratio is synchronized to the
state of the main divider to avoid introducing a phase disturbance.

NF

Q

Auxiliary divider

The AUXin input drives a pre-amplifier to provide the clock to the
first divider stage. The pre-amplifier has a high input impedance,
dominated by pin and pad capacitance. The circuit operates with
signal levels from –18dBm to 0 dBm (80 to 636 mVpp), and at
frequencies as high as 550 MHz. The divider consists of a fully
programmable bipolar prescaler followed by a CMOS counter. Total
divide ratios ranges from 128 to 16383.

Reference divider

The reference divider consists of a divider with programmable
values between 4 and 1023 followed by a three bit binary counter.
The 3 bit SM (SA) register (see figure 4) determines which of the 5
output pulses are selected as the main (auxiliary) phase detector
input.

Phase detector (see Figure 5)

The reference and main (aux) divider outputs are connected to a
phase/frequency detector that controls the charge pump. The pump
current is set by an external resistor in conjunction with control bits
CP0 and CP1 in the C-word (see Charge Pump table). The dead
zone (caused by finite time taken to switch the current sources on or
off) is cancelled by forcing the pumps ON for a minimum time at
every cycle (backlash time) providing improved linearity.

SA8026

REFERENCE
INPUT

DIVIDE BY R /2 /2 /2 /2

Figure 4. Reference Divider

SM=”000”
SM=”001”

SM=”010”
SM=”011”

SM=”100”

SA=”100”

SA=”011”

SA=”010”
SA=”001”

SA=”000”

TO

MAIN

PHASE

DETECTOR

TO

AUXILIARY

PHASE

DETECTOR

SR01415

1999 Nov 04

7

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N dual frequency
synthesizer

f

REF

REF DIVIDER

AUX/MAIN

DIVIDER

“1”

“1”

X

D

R

Q

CLK

R

τ

R

D

CLK

Q

SA8026

V

CC

P

N

GND

P–TYPE

CHARGE PUMP

I

PH

N–TYPE

CHARGE PUMP

f

REF

R

N

I

PH

X

τ

P

τ

SR01451

Figure 5. Phase Detector Structure with Timing

1999 Nov 04

8

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N dual frequency
synthesizer

Main Output Charge Pumps and Fractional
Compensation Currents (see Figure 6)

The main charge pumps on pins PHP and PHI are driven by the
main phase detector and the charge pump current values are
determined by the current at pin R

in conjunction with bits CP0,

SET

CP1 in the C-word (see table of charge pump ratios). The fractional
compensation is derived from the current at R

, the contents of

SET

the fractional accumulator FRD and by the program value of the
FDAC. The timing for the fractional compensation is derived from
the main divider. The main charge pumps will enter speed up mode
after the A-word is set and strobe goes High. When strobe goes
Low, charge pump will exit speed up mode.

Principle of Fractional Compensation

The fractional compensation is designed into the circuit as a means
of reducing or eliminating fractional spurs that are caused by the
fractional phase ripple of the main divider. If I
compensation current and I

is the pump current, then for each

PUMP

charge pump:

I

PUMP_TOTAL

= I

PUMP

+ I

COMP

COMP

is the

.

The compensation is done by sourcing a small current, I
Figure 7, that is proportional to the fractional error phase. For proper
fractional compensation, the area of the fractional compensation
current pulse must be equal to the area of the fractional charge
pump ripple. The width of the fractional compensation pulse is fixed
to 128 VCO cycles, the amplitude is proportional to the fractional
accumulator value and is adjusted by FDAC values (bits FC7–0 in
the B-word). The fractional compensation current is derived from the
main charge pump in that it follows all the current scaling through
external resistor setting, R
For a given charge pump,

FRD is the fractional accumulator value.
The target values for FDAC are: 128 for FMOD = 1 (modulo 5) and

80 for FMOD = 0 (modulo 8).

I

COMP

SA8026

, programming or speed-up operation.

SET

= ( I

/ 128 ) * ( FDAC / 5*128) * FRD

PUMP

COMP

, see

REFERENCE R

MAIN M
DIVIDE RATIO

DETECTOR
OUTPUT

ACCUMULATOR

FRACTIONAL
COMPENSATION
CURRENT

OUTPUT ON
PUMP

NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output.

N N N+1 N N+1

241

PULSE
WIDTH
MODULATION

PULSE LEVEL
MODULATION

Figure 6. Waveforms for NF = 2 Modulo 5 → fraction = 2/

f

RF

MAIN DIVIDER

FRACTIONAL

ACCUMULATOR

3

5

0

mA

µA

SR01416

1999 Nov 04

I

COMP

I

f

REF

PUMP

Σ

Figure 7. Current Injection Concept

9

LOOP FILTER

& VCO

SR01800

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N dual frequency

SA8026

synthesizer

Auxiliary Output Charge Pumps

The auxiliary charge pump on pin PHA are driven by the auxiliary phase detector and PHP, PHI are driven by the main phase detector. The
current value is determined by the external resistor attached to pin R

Main and auxiliary charge pump currents

CP1

0 0 1.5xl
0 1 0.5xl
1 0 1.5xl
1 1 0.5xl

CP0 I

PHA

SET

SET

SET

SET

NOTES

= V

1. I

SET

2. CP1 is used to disable the PHI pump, I

SET/RSET

: bias current for charge pumps.

is the total current at pin PHP during speed up condition.

PHP–SU

Lock Detect

The output LOCK maintains a logic ‘1’ when the auxiliary phase
detector ANDed with the main phase detector indicates a lock
condition. The lock condition for the main and auxiliary synthesizers
is defined as a phase difference of less than "1 period of the
frequency at the input REF
condition when the other counter is powered down. Out of lock (logic
’0’) is indicated when both counters are powered down.

. One counter can fulfill the lock

in+, –

.

SET

3xI
1xl
3xl
1xl

I

PHP

SET

SET

SET

SET

I

PHP–SU

15xl

SET

5xl

SET

15xl

SET

5xl

SET

36xl
12xl

Power-down mode

The power-down signal can be either hardware (PON) or software
(PD). The PON signal is exclusively ORed with the PD bits in
B-word. If PON = 0, then the part is powered up when PD = 1. PON
can be used to invert the polarity of the software bit PD. When the
synthesizer is reactivated after power-down, the main and reference
dividers are synchronized to avoid possibility of random phase
errors on power-up.

I

PHI

SET

SET

0
0

1999 Nov 04

10

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N dual frequency
synthesizer

Serial programming bus

The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 or 3 address bits. Figure 8
shows the timing diagram of the serial input. When the STROBE
goes active HIGH, the clock is disabled and the data in the shift
register remains unchanged. Depending on the address bits, the

Serial bus timing characteristics. See Figure 8.

V

= V

DD

Serial programming clock; CLK

t

r

t

f

T

cy

Enable programming; STROBE

t

START

t

W

t

SU;E

Register serial input data; DATA

t

SU;DAT

t

HD;DAT

DDCP

SYMBOL

=+3.0V; T

= +25°C unless otherwise specified.

amb

PARAMETER MIN. TYP . MAX. UNIT

Input rise time – 10 40 ns
Input fall time – 10 40 ns
Clock period 100 – – ns

Delay to rising clock edge 40 – – ns
Minimum inactive pulse width 1/f
Enable set-up time to next clock edge 20 – – ns

Input data to clock set-up time 20 – – ns
Input data to clock hold time 20 – – ns

data is latched into different working registers or temporary
registers. In order to fully program the synthesizer, 3 words must be
sent: C, B, and A. Table 1 shows the format and the contents of
each word. The D word is normally used for testing purposes. When
sending the B-word, data bits FC7–0 for the fractional compensation
DAC are not loaded immediately. Instead they are stored in
temporary registers. Only when the A-word is loaded, these
temporary registers are loaded together with the main divider ratio.

COMP

SA8026

– – ns

Application information

CLK

DATA

STROBE

t

SU;DAT

ADDRESS LSB

t

START

T

cy

MSB

t

HD;DAT

t

r

Figure 8. Serial Bus Timing Diagram

t

f

t

SU;E

t

w

SR01417

1999 Nov 04

11

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N dual frequency

SA8026

synthesizer

Data format
Table 1. Format of programmed data

Last In MSB Serial Programming Format First In LSB

p23 p22 p21 p20 ../.. ../.. p1 p0

Table 2. A word, length 24 bits

Last In MSB LSB First In

Address fmod Fractional-N Main Divider ratio Spare

0 0 FM NF2 NF1 NF0 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 SK1 SK2

Default
A word select Fixed to 00.
Fractional Modulus select FM 0 = modulo 8, 1 = modulo 5.
Fractional-N Increment NF2..0 Fractional N Increment values 000 to 111.
N-Divider N0..N15, Main divider values 512 to 65535 allowed for divider ratio.

Table 3. B word, length 24 bits

Address Reference Divider Lock PD Fractional Compensation DAC

0 1 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L1 L0 Main Aux FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0

Default
B word select Fixed to 01
R-Divider R0..R9, Reference divider values 4 to 1023 allowed for divider ration.
Lock detect output L1 L0

Power down Main = 1: power to N-divider, reference divider, main charge pumps, Main = 0 to power down.

Fractional Compensation FC7..0 Fractional Compensation charge pump current DAC, values 0 to 255.

0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0

0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 0 0 0

0 0 Combined main, aux. lock detect signal present at the LOCK pin (push/pull).
0 1 Combined main, aux, lock detect signal present at the LOCK pin (open drain).
1 0 Main lock detect signal present at the LOCK pin (push/pull).
1 1 Auxiliary loop lock detect signal present at the LOCK pin (push/pull).
When auxiliary loop and main loop are in power down mode, the lock indicator is low.

Aux = 1: power to Aux divider, reference divider, aux charge pump, Aux = 0 to power down.

Table 4. C word, length 24 bits

Address Auxiliary Divider CP SM SA

1 0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CP1 CP0 SM2 SM1 SM0 SA2 SA1 SA0

Default
C word select Fixed to 10
A-Divider A0..A13, Auxiliary divider values 128 to 16383 allowed for divider ratio.
Charge pump current Ratio CP1, CP0: Charge pump current ratio, see table of charge pump currents.
Main comparison select SM comparison divider select for main phase detector.
Aux comparison select SA Comparison divider select for auxiliary phase detector.

0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 0

Table 5. D word, length 24 bits

Address Synthesizer Test Bits Synthesizer Test Bits

1 1 0 – – – – – Tspu – – – – – – – – – – – – – – –

Default

Tspu: Speed up = 1 Forces the main charge pumps in speed-up mode all the time.

1999 Nov 04

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NOTE: All test bits must be set to 0 for normal operation.

12

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N dual frequency
synthesizer

TYPICAL PERFORMANCE CHARACTERISTICS

3000

2000

1000

0

I

= 51.67 mA

ICP (uA)

–1000

–2000

–3000

SET

I

= 103.33 mA

SET

I

= 165.33 mA

SET

I

= 206.67 mA

SET

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3

COMPLIANCE VOLTAGE (V)

Figure 9. PHI Charge Pump vs. I

(CP = 01; Temp = 25_C)

SET

I

SET

I

SET

I

SET

I

SET

= 206.67 mA

= 165.33 mA
= 103.33 mA

= 51.67 mA

SR01855

SA8026

2500
2000
1500
1000

500

0

Icp (uA)

–500
–1000
–1500
–2000
–2500

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

COMPLIANCE VOLTAGE (V)

Figure 10. PHI Charge Pump Output vs. Temperature

(CP = 01; V

= 3.0 V; I

DD

= 165.33 mA)

SET

+85_C
+25_C
–40_C

SR01856

Icp (uA)

–2000
–4000
–6000
–8000

8000
6000
4000
2000

0

I

= 51.67 mA

SET

I

= 103.33 mA

SET

I

= 165.33 mA

SET

I

= 206.67 mA

SET

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3

COMPLIANCE VOLTAGE (V)

I

SET

I

SET

I

SET

I

SET

Figure 11. PHI Charge Pump vs. I

(CP = 00; TEMP = 25_C)

800
600
400
200

0

Icp (uA)

–200

I

= 51.67 mA

SET

I

–400
–600
–800

= 103.33 mA

SET

I

= 165.33 mA

SET

I

= 206.67 mA

SET

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3

COMPLIANCE VOLTAGE (V)

I

I
I

I

Figure 13. PHP Charge Pump Output vs. I

(CP = 10; Temp = 25_C)

= 206.67 mA

= 165.33 mA
= 103.33 mA
= 51.67 mA

= 206.67 mA

SET

= 165.33 mA

SET

= 103.33 mA

SET

= 51.67 mA

SET

SET

SR01859

SR01857

SET

8000
6000

Icp (uA)

–2000
–4000
–6000
–8000

4000
2000

0

0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

0

COMPLIANCE VOLTAGE (V)

+85_C
+25_C
–40_C

SR01858

Figure 12. PHI Charge Pump Output vs. Temperature

(CP = 00; V

600

400

200

0

Icp (uA)

–200

–400

–600

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

= 3.0 V; I

DD

COMPLIANCE VOLTAGE (V)

= 165.33 mA)

SET

+85_C
+25_C
–40_C

SR01860

Figure 14. PHP Charge Pump Output vs. Temperature

(CP = 10; V

= 3.0 V; I

DD

= 165.33 mA)

SET

1999 Nov 04

13

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N dual frequency
synthesizer

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

250
200
150
100

50

0

Icp (uA)

–50

I

= 51.67 mA

SET

–100

I

= 103.33 mA

SET

–150

I

= 165.33 mA

SET

–200

I

= 206.67 mA

SET

–250

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3

COMPLIANCE VOLTAGE (V)

Figure 15. PHP Charge Pump Output vs. I

(CP = 11; Temp = 25_C)

I

= 206.67 mA

SET

I

= 165.33 mA

SET

I

= 103.33 mA

SET

I

= 51.67 mA

SET

SR01861

SET

SA8026

200
150
100

50

0

Icp (uA)

–50
–100
–150
–200

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

COMPLIANCE VOLTAGE (V)

Figure 16. PHP Charge Pump Output vs. Temperature

(CP = 11; V

= 3.0 V; I

DD

= 165.33 mA)

SET

+85_C
+25_C
–40_C

SR01862

1500

1000

500

0

I

= 51.67 mA

Icp (uA)

–1000

–1500

SET

I

= 103.33 mA

SET

–500

I

= 165.33 mA

SET

I

= 206.67 mA

SET

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2 2.25 2.5 2.75 3

COMPLIANCE VOLTAGE (V)

Figure 17. PHP–SU Charge Pump Output vs. I

(CP = 01; Temp = 25_C)

3500

2500

1500

500

0

–500

Icp (uA)

–1500

–2500

–3500

0 0.25 0.5 0.75 1.251 1.5 1.75 2 2.25 2.5 2.75 3

I

= 51.67 mA

SET

I

= 103.33 mA

SET

I

= 165.33 mA

SET

I

= 206.67 mA

SET

COMPLIANCE VOLTAGE (V)

I

SET

I

SET

I

SET

I

SET

Figure 19. PHP–SU Charge Pump Output vs. I

(CP = 00; Temp = 25_C)

I

= 206.67 mA

SET

I

= 165.33 mA

SET

I

= 103.33 mA

SET

I

= 51.67 mA

SET

= 206.67 mA
= 165.33 mA

= 103.33 mA
= 51.67 mA

SR01863

SET

SR01870

SET

1000

800
600
400
200

0

Icp (uA)

–200
–400
–600
–800

–1000

0 0.25 0.5 0.75 1 1.25

1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

COMPLIANCE VOLTAGE (V)

+85_C
+25_C
–40_C

SR01864

Figure 18. PHP–SU Charge Pump Output vs. Temperature

(CP = 01; V

3000

2000

1000

0

Icp (uA)

–1000

–2000

–3000

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

= 3.0 V; I

DD

COMPLIANCE VOLTAGE (V)

= 165.33 mA)

SET

+85_C
+25_C
–40_C

SR01865

Figure 20. PHP–SU Charge Pump Output vs. Temperature

(CP = 00; V

= 3.0 V; I

DD

= 165.33 mA)

SET

1999 Nov 04

14

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N dual frequency
synthesizer

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

150

I

= 206.67 mA

100

50

0

I

Icp (uA)

–50

–100

–150

= 51.67 mA

SET

I

= 103.33 mA

SET

I

= 165.33 mA

SET

I

= 206.67 mA

SET

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3

COMPLIANCE VOLTAGE (V)

Figure 21. PHA Charge Pump Output vs. I

(CP = 11; Temp = 25_C)

SET

I

= 165.33 mA

SET

I

= 103.33 mA

SET

I

= 51.67 mA

SET

SR01866

SET

SA8026

100

80
60
40
20

0

Icp (uA)

–20
–40
–60
–80

–100

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

COMPLIANCE VOLTAGE (V)

Figure 22. PHA Charge Pump Output vs. Temperature

(CP = 11; V

= 3.0 V; I

DD

= 165.33 mA)

SET

+85_C
+25_C
–40_C

SR01867

400
300
200
100

0

Icp (uA)

–100

I

= 51.67 mA

–200
–300
–400

SET

I

= 103.33 mA

SET

I

= 165.33 mA

SET

I

= 206.67 mA

SET

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3

COMPLIANCE VOLTAGE (V)

I

= 206.67 mA

SET

I

= 165.33 mA

SET

I

= 103.33 mA

SET

I

= 51.67 mA

SET

Figure 23. PHA Charge Pump Output vs. I

(CP = 10; Temp = 25_C)

10.00

5.00

0.00

–5.00
–10.00
–15.00
–20.00
–25.00
–30.00
–35.00

MINIMUM SIGNAL INPUT LEVEL (dBm)

–40.00
–45.00

1300 1500 1700 1900 2100 2300 2500 2700 2900 3100 3300

VDD = 5.00 V
VDD = 3.75 V
VDD = 3.00 V
VDD = 2.70 V

FREQUENCY (MHz)

Figure 25. Main Divider Input Sensitivity vs.

Frequency and Supply Voltage

(Temp = 25_C)

SR01869

SET

SR01878

300

200

100

0

Icp (uA)

–100

–200

–300

0 0.25 0.5 0.75 1.251 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

COMPLIANCE VOLTAGE (V)

Figure 24. PHA Charge Pump Output vs. Temperature

(CP = 10; V

0.00

–5.00
–10.00
–15.00
–20.00
–25.00
–30.00
–35.00
–40.00

MINIMUM SIGNAL INPUT LEVEL (dBm)

–45.00

1300 1500 1700 1900 2100 2300 2500 2700 2900 3100

= 3.0 V; I

DD

FREQUENCY (MHz)

= 165.33 mA)

SET

Figure 26. Main Divider Input Sensitivity vs.

Frequency and Temperature

= 3.00 V)

(V

DD

+85_C
+25_C
–40_C

SR01868

+85_C
–40_C
+25_C

SR01879

1999 Nov 04

15

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N dual frequency
synthesizer

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

0.00

–5.00
–10.00
–15.00
–20.00
–25.00
–30.00
–35.00
–40.00

MINIMUM SIGNAL POWER LEVEL (dBm)

–45.00

0 40 80 120 160 200 240 280 320 360 400 440 480 520 560

Figure 27. Auxiliary Divider Input Sensitivity vs.

Frequency and Supply Voltage

VDD = 5.00 V
VDD = 3.75 V
VDD = 3.00 V
VDD = 2.70 V

FREQUENCY (MHz)

(Temp = 25_C)

SR01880

0.00

–5.00
–10.00
–15.00
–20.00
–25.00
–30.00
–35.00
–40.00

MINIMUM SIGNAL POWER LEVEL (dBm)

–45.00

0 40 80 120 160 200 240 280 320 360 400 440 480 520 560 600 640

FREQUENCY (MHz)

Figure 28. Auxiliary Divider Input Sensitivity vs.

Frequency and Temperature

(Supply = 3.00 V)

SA8026

+85_C
–40_C

+25_C

SR01881

0.00

MINIMUM SIGNAL POWER LEVEL (dBm)

–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55

0

5 10152025303540455055606570

FREQUENCY (MHz)

VDD = 5.00 V
VDD = 3.75 V
VDD = 3.00 V
VDD = 2.70 V

Figure 29. Reference Divider Input Sensitivity vs.

Frequency and Supply Voltage

(Temp = 25_C)

13

12

11

I TOTAL (mA)

10

9

2 2.5 3 3.5 4 4.5 5 5.5 6

SUPPLY VOLTAGE (V)

Figure 31. Current Supply Over V

DD

SR01890

+85_C
+25_C
–40_C

SR01854

0

MINIMUM SIGNAL POWER LEVEL (dBm)

–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55

0

5 10152025303540455055606570

Temp = –40_C
Temp = +85_C
Temp = +25_C

FREQUENCY (MHz)

Figure 30. Reference Divider Input Sensitivity vs.

Frequency and Temperature

= 3.00 V)

(V

DD

SR01891

1999 Nov 04

16

Philips Semiconductors Product specification

2.5GHz low voltage fractional–N dual frequency
synthesizer

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

SA8026

1999 Nov 04

17

Philips Semiconductors Product specification

2.5GHz low voltage fractional–N dual frequency
synthesizer

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

SA8026

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1999

All rights reserved. Printed in U.S.A.

Date of release: 11-99

Document order number: 9397 750 06567

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1999 Nov 04

18