Datasheet S3C8075, S3P8075 Datasheet (Samsung)

S3C8075/P8075 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

SAM8 PRODUCT FAMILY

Samsung's SAM87 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:

— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to
specific interrupt levels.

S3C8075/P8075 MICROCONTROLLERS

S3C8075/P8075 single-chip 8-bit microcontrollers are based on the powerful SAM87 CPU architecture. The
internal register file is logically expanded to increase the on-chip register space. The S3C8075 has 16-Kbyte
mask-programmable ROM. The S3P8075 has 16-Kbyte one-time-programmable EPROM.

Following Samsung's modular design approach, the following peripherals are integrated with the SAM87 core:
— Seven programmable I/O ports (total 56 pins)

— One 8-bit basic timer for oscillation stabilization and watchdog functions
— One synchronous operating mode and three full-duplex asynchronous UART modes
— Two 8-bit timers with interval timer and PWM modes
— Two 16-bit general-purpose timer/counters

OTP

The S3C8075 microcontroller is also available in OTP (One Time Programmable) version, S3P8075. S3P8075
microcontroller has an on-chip 16-Kbyte one-time-programmable EPROM instead of masked ROM. The
S3P8075 is comparable to S3C8075, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW S3C8075/P8075

FEATURES

CPU

• SAM87 CPU core

Memory

• 272-byte general purpose register area

• 16-Kbyte internal program memory

• ROM-less operating mode

External Interface

• 64-Kbyte external data memory area

• 64-Kbyte external program memory area (ROM­less mode)

Instruction Set

• 78instructions

• IDLE and STOP instructions for power-down
mode

Instruction Execution Time

• 500 ns at 12 MHz f

CPU

(Min.)

Interrupts

• 17 interrupt sources

General I/O

• Four nibble-programmable ports

• One bit-programmable port

• Two bit-programmable ports for external
interrupts

Timers

• Two 8-bit timers with interval timer and PWM
modes

Timer/Counters

• Two 16-bit general-purpose timer/counters

Basic Timer

• One 8-bit basic timer (BT) for oscillation
stabilization control and watch dog timer function.

Serial Port

• One synchronous operating mode and three full­duplex asynchronous UART modes

Operating Temperature Range

• – 40°C to + 85°C

• 17 interrupt vectors

• Eight interrupt levels

• Fast interrupt processing

1-2

Operating Voltage Range

• 2.7 V to 5.5 V

Package Types

• 64-pin SDIP, 64-pin QFP

S3C8075/P8075 PRODUCT OVERVIEW

Table 1-1. Comparison Table

Feature S3C80B5 S3C8075

Core SAM8 SAM87
ROM 16 K bytes Same
RAM 272 bytes Same
I/O 54 56 (add two pins)
Port 6 Open drain (9 V drive) Normal C-MOS output
I/O option None Same
Timer 8-bit back-up timer None

Timer A, B
— 8-bit
— Interval/PWM mode

Same
(some differ in interval mode,
see manual)

— Timer A match interrupt
Timer C, D

Same
— Gate function
— Timer/counter

Watchdog timer None Watchdog timer (with BT)
SIO UART

Same
— 8-bit/9-bit UART
— SIO

Interrupt

External × 12

Same
— P2.4–P2.7, P4.0–P4.7

Internal × 6
— Timer A, C, D, SI, SO, Back-up

Internal × 5

— Timer A, C, D, SI, SO

Power down Stop/idle Same
Oscillator Crystal, ceramic Same
CPU clock divider 1/2 1/1, 1/2, 1/8, 1/16
Execution time (Min.)

Operating frequency

0.6 µs at 20 MHz (f
Max. 20 MHz (f

CPU

= 10 MHz) 0.5 µs at 12 MHz (f

CPU

= 10 MHz)

Max. 12 MHz (at 4.5 V)

= 12 MHz)

CPU

(2)

Max. 4 MHz (at 2.7 V)

Operating voltage 4.5–5.5 V 2.7–5.5 V at 4 MHz

4.5–5.5 V at 12 MHz
OTP/MTP MTP OTP
Pin assignment – Different
Package 64SDIP/64QFP Same
Start address 0020h 0100h
P5CON, P6CON BANK0 BANK1
Interrupt pending bit clear Write "1" Write "0"

NOTES:

1. The S3C8075 can replace the S3C80B5. Their functions are mostly the same, but there are some differences.
Table 1-1 shows the comparison of S3C8075 and S3C80B5.

2. Operating frequency is maximum CPU clock; the maximum oscillation frequency is 22.1184 MHz.

1-3

PRODUCT OVERVIEW S3C8075/P8075

BLOCK DIAGRAM

X

IN

X

OUT

TA
TB

TCCK
TDCK

RESET

EA

TIMERS
A and B

TIMERS

C and D

MAIN

OSC

BASIC
TIMER

P0.0–P0.7

(A8–A15)

PORT 0

P1.0–P1.7

(AD0–AD7)

PORT 1

SAM87 BUS

PORT I/O and

INTERRUPT CONTROL

P2.4/INT0–P2.7/INT3

SAM87 CPU

P2.0–P2.3,

PORT 2

PORT 3

PORT 4

PORT 5

P3.0–P3.7

P4.0/INT4 (TCG)
P4.1/INT5 (TDG)
P4.2/INT6–
P4.7/INT11

P5.0–P5.3
P5.4–P5.7

1-4

RxD

TxD

SERIAL

PORT

16-KB ROM

272-BYTE

REGISTER FILE

Figure 1-1. S3C8075 Block Diagram

PORT 6

P6.0–P6.7

S3C8075/P8075 PRODUCT OVERVIEW

P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10

P0.1/A9

P0.0/A8
P4.7/INT11
P4.6/INT10

P4.5/INT9
P4.4/INT8
P4.3/INT7

P4.2/INT6
P4.1/INT5/TDG
P4.0/INT4/TCG

V

DD1

V

SS1

X

OUT

X

EA
P5.6
P5.7

RESET

P3.7/RxD

P3.6/TxD

P3.5/TB
P3.4/TA

P3.3
P3.2

P3.1/TDCK
P3.0/TCCK

P6.0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

IN

20
21
22
23
24
25
26
27
28
29
30
31
32

S3C8075

64-SDIP

(Top View)

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P0.7/A15
P1.0/AD0
P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
V

DD2

V

SS2

P2.0/

AS

P2.1/

DS

P2.2/R/
P2.3/
P2.4/INT0/
P2.5/INT1
P2.6/INT2
P2.7/INT3
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1

W

DM

WAIT

Figure 1-2. S3C8075 Pin Assignments (64-SDIP)

1-5

PRODUCT OVERVIEW S3C8075/P8075

P1.4/AD4

P1.3/AD3

P1.2/AD2

P1.1/AD1

P1.0/AD0

P0.7/A15

P0.6/A14

P0.5/A13

P0.4/A12

P0.3/A11

P0.2/A10

P0.1/A9

P0.0/A8

52

53

54

55

56

57

58

59

60

61

62

63

64

51

P4.7/INT11
P4.6/INT10

P4.5/INT9
P4.4/INT8
P4.3/INT7

P4.2/INT6
P4.1/INT5/TDG
P4.0/INT4/TCG

V

DD1

V

SS1

X

OUT

XIN

EA
P5.6
P5.7

RESET

P3.7/RxD

P3.6/TxD

P3.5/TB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

20

21

22

S3C8075

64-QFP

(Top View)

26

25

24

23

27

28

29

30

31

32

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
V

DD2

V

SS2

P2.0/AS
P2.1/DS
P2.2/R/W
P2.3/DM
P2.4/INT0/
P2.5/INT1
P2.6/INT2
P2.7/INT3

WAIT

P6.7

P6.6

P6.5

P6.4

P6.3

P6.2

P6.1

P6.0

P3.0/TCCK

P3.1/TDCK

P3.2

P3.3

P3.4/TA

Figure 1-3. S3C8075 Pin Assignments (64-QFP)

1-6

S3C8075/P8075 PRODUCT OVERVIEW

Table 1-2. S3C8075 Pin Descriptions (64-SDIP)

Pin

Name

P0.0–P0.7 I/O I/O port with nibble-programmable pins;

Pin

Type

Pin

Description

Circuit

Number

SDIP Pin

Number

E 1–7, 64 A8–A15

Share

Pins

Input or push-pull, open-drain output and
software assignable pull-ups; also
configurable as external interface address
lines A8-A15.

P1.0–P1.7 I/O Same general characteristics as port 0; also

E 56–63 AD0–AD7
configurable as external interface
address/data lines AD0–AD7.

P2.0–P2.3

I/O I/O port with bit-programmable pins; Input

or push-pull output. Lower nibble pins 0–3

D-1 (lower

nibble);

40–47

AS, DS,

DM, R/W

are configurable for external interface

P2.4–P2.7

signals; upper nibble pins 4–7 are bit­programmable for external interrupts INT0–
INT3. P2.4 can also be used for external

D-1 (upper
nibble; with
noise filter)

INT0–INT3,

WAIT

WAIT input.

P3.0–P3.7 I/O I/O port with bit-programmable pins; Input

or push-pull output. Alternate functions
include software-selectable UART transmit
and receive on pins 3.7 and 3.6, timer B

D-1 24– 31 TCCK,

TDCK, TA,

TB, TxD,

RxD
and timer A outputs at pins 3.5 and 3.4, and
timer D and C clock inputs at pins 3.1 and

3.0.

P4.0–P4.7 I/O I/O port with bit-programmable pins; Input

or push-pull output; software-assignable
pull-ups. Alternate functions include

D

(with noise

filter)

8–15 INT4–

INT11,

TCG, TDG
external interrupt inputs INT4-INT11 (with
interrupt enable and pending control) and
timer C and D gate input at P4.0 and P4.1.

P5.0–P5.7 I/O I/O port with nibble-programmable pins;

Input or push-pull, open-drain output;

E 21, 22,

50–55

–

software-assignable pull-ups.

P6.0–P6.7 O Output port with nibble-programmable pins;

E-8 32–39 –
push-pull, open-drain output; software­assignable pull-ups.

RxD I/O Bi-directional serial data input pin – 24 P3.7
TxD I/O Serial data output pin – 25 P3.6
TA, TB I/O Timer A and B output pins 4 27, 26 P3.4, P3.5
TCCK, TDCK I/O Timer C and D external clock input pins D-1 30, 31 P3.0, P3.1
INT0–INT3 I/O External interrupts. I/O pin 2.4 (share pin

with INT0) is also configurable as a WAIT
signal input pin for the external interface.

D-1

(with noise

filter)

40–43 P2.4–P2.7

1-7

PRODUCT OVERVIEW S3C8075/P8075

Table 1-2. S3C8075 Pin Descriptions (Continued)

Pin

Name

Pin

Type

Pin

Description

INT4–INT11 I/O Bit-programmable external interrupt input

pins with interrupt pending and enable
/disable control

XIN, X

RESET

OUT

– System clock input and output pins – 18, 19 –

I System reset pin

(internal pull-up: 280 KΩ)

EA I External access (EA) pin with three modes:

0 V: Normal operation (internal ROM)
5 V: ROM-less operation (external interface)

V
V

DD2
DD1

, V
, V

SS2
SS1

– Power input pins for port output (external) – 49, 48 –
– Power input pins for CPU (internal) – 16, 17 –

Circuit

Number

D

SDIP Pin

Number

8–15 P4.0–P4.7

(with noise

filter)

B 23 –

– 20 –

Share

Pins

1-8

S3C8075/P8075 PRODUCT OVERVIEW

PIN CIRCUIT

V

DD

Pull-Up Resistor

Pull-Up

Enable

Data

(Typical Value: 47 )

V

DD

K

Ω

Open-Drain

Output Disable

Pull-Up

Enable

Open-Drain

Data

In

Figure 1-4. Pin Circuit Type E (Ports 0, 1, 5)

V

DD

In/Out

V

DD

Pull-Up Resistor
(Typical Value: 47 )K

Ω

V

SS

Figure 1-5. Pin Circuit Type E-8 (Ports 6)

In/Out

1-9

PRODUCT OVERVIEW S3C8075/P8075

Select

V

DD

Port 2 (Low Byte) Data

External Interface

(

AS, DS,

R/

W, DM

M
U

)

X

Data

In/Out

Output Disable

V

SS

In

Figure 1-6. Pin Circuit Type D-1 (P2.0–P2.3)

Port 2 (High Byte) Data

Output Disable

Normal Input or

Input

WAIT

External Interrupt

Figure 1-7. Pin Circuit Type D-1 (P2.4–P2.7)

Noise Filter

V

DD

In/Out

V

SS

1-10

S3C8075/P8075 PRODUCT OVERVIEW

Select

V

DD

Port 3 Data

M

Data

U

Control Output

X

In/Out

Output Disable

V

SS

In

Figure 1-8. Pin Circuit Type D-1 (Port 3)

Pull-Up Enable

Data

Output Disable

Input

External

Interrpt Input

Noise Filter

V

DD

Pull-Up Resistor

(Typical Value: 47 )

V

DD

K

Ω

In/Out

V

SS

Figure 1-9. Pin Circuit Type D (Port 4)

1-11

PRODUCT OVERVIEW S3C8075/P8075

V

DD

Pull-up Resistor
(Typical 210 K

Ω)

RESET

Figure 1-10. Pin Circuit Type B (RESETRESET)

1-12

S3C8075/P8075 ELECTRICAL DATA

14 ELECTRICAL DATA

OVERVIEW

In this section, S3C8075 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:

— Absolute maximum ratings
— D.C. electrical characteristics
— I/O capacitance
— A.C. electrical characteristics
— Oscillation characteristics
— Oscillation stabilization time

14-1

ELECTRICAL DATA S3C8075/P8075

Table 14-1. Absolute Maximum Ratings

(TA = 25 °C)

Parameter Symbol Conditions Rating Unit

Supply voltage V
Input voltage V
Output voltage V
Output current high I

DD

O

OH

I

All ports (in input mode) – 0.3 to V
All ports (in output mode) – 0.3 to VDD + 0.3 V
One I/O pin active – 10 mA

– 0.3 to + 6.5 V

+ 0.3

DD

All I/O pins active – 60

Output current low I

OL

One I/O pin active + 30 mA
Total pin current for ports 0–4 + 100

Total pin current for ports 5 and 6 + 100

Operating

T

A

– 40 to + 85 °

C

temperature
Storage temperature T

STG

– 65 to + 150 °

C

14-2

S3C8075/P8075 ELECTRICAL DATA

Table 14-2. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Input high

V

IH1

All input pins except V

IH2

0.8 V

DD

– V

DD

V

voltage

Input low voltage V

Output high

V

voltage

V

V

IH2

IL1
IL2

OH1

X

IN

All input pins except V
X

IN

VDD= 4.5 V to 5.5 V
IOH = – 4 mA

IL2

V

– 0.5

DD

– – 0.2 V

0.4

V

– 1.0 – – V

DD

DD

V

Port 5, 6

V

OH2

V

= 4.5 V to 5.5 V

DD

IOH = – 1 mA
All output pins except

port 5, 6

Output low voltage V

OL1

V

= 4.5 V to 5.5 V

DD

– – 1.0 V
IOL = 15 mA
Ports 5 and 6

V

OL2

IOL = 2 mA

0.4

Ports 0–4

Input high leakage
current

Input low leakage
current

Output high
leakage current

Output low leakage

I

LIH1

I

LIH2

I

LIL1

I

LIL2

I

LOH

I

LOL

VIN = V

DD

All input pins except XIN, X
VIN = V
V

= 0 V

IN

DD

XIN, X

,

OUT

All input pins except XIN, X
V

= 0 V, X

IN

V

OUT

= V

DD

, X

IN

OUT

OUT

OUT

– – 3

– – – 3

– – 5
All output pins

V

= 0 V – – – 5

OUT

µA

20

µA

– 20

µA

µA

current
Pull-up resistor R

L1

V

= 0 V; V

IN

DD

= 5 V

30 47 70

KΩ

Ports 0, 1, 4, 5 and 6

R

L2

V

IN

= 0 V; V

DD

= 5 V

110 210 310

RESET only

14-3

ELECTRICAL DATA S3C8075/P8075

Table 14-2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Supply current

(1)

I

DD1

(2)

V

= 5 V ± 10 %

DD

– 12 25 mA

12-MHz oscillation
4-MHz oscillation 4.5 10
V

= 3 V ± 10 %

DD

6 15

12-MHz oscillation
4-MHz oscillation 2.5 7

(2)

I

DD2

Idle mode; V

= 5 V ± 10 %

DD

3 10

12-MHz oscillation
4-MHz oscillation 1.5 4
Idle mode; VDD = 3 V ± 10 %

1.2 3

12-MHz oscillation
4-MHz oscillation 0.6 1.5

I

DD3

Stop mode:
V

= 5 V ± 10 %

DD

0.1 3

µA

NOTES:

1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.

2. At supply current, the CPU clock frequency is same with oscillation frequency (CPU use non divided clock).

Table 14-3. Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Data retention supply

V

DDDR

Stop mode 2 – 6 V

voltage
Data retention supply

I

DDDR

Stop mode, V

= 2.0 V – – 3

DDDR

current

NOTES:

1. During the oscillator stabilization wait time (t

2. Supply current does not include drawn through internal pull–up resistors and external output current loads.

), all CPU operations must be stopped.

WAIT

µA

14-4

S3C8075/P8075 ELECTRICAL DATA

Idle Mode
(Oscillation
Stabilzation Time)

0.8 V

DD

Normal
Operating
Mode

V

DD

EXT INT

Execution of

Stop Instruction

∼∼∼

∼∼∼

∼

Stop Mode

Data Retention Mode

∼

V

DDDR

0.2 V

DD

V

DD

RESET

NOTE:

t

is the same as 16 x BT clock.

WAIT

t

WAIT

Figure 14-1. Stop Mode Release Timing When Initiated by an External Interrupt

Oscillation
Stabilzation
Time

Normal
Operating
Mode

Execution of

Stop Instruction

NOTE:

t

∼∼∼

∼

∼∼∼

∼

is the same as 4096 x 16 x 1/f

WAIT

Stop Mode

Data Retention Mode

V

DDDR

.

OSC

Reset Occurs

t

WAIT

Figure 14-2. Stop Mode Release Timing When Initiated by a Reset

14-5

ELECTRICAL DATA S3C8075/P8075

Table 14-4. Input/output Capacitance

(T

= – 40 °C to + 85 °C, V

A

DD

= 0 V)

Parameter Symbol Conditions Min Typ Max Unit

Input
capacitance

Output

C

C

OUT

IN

f = 1 MHz; unmeasured
pins are connected to V

SS

– – 10 pF

capacitance
I/O capacitance C

IO

Table 14-5. A.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, V

A

= 2.7 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Interrupt input high,
low width

t

INTH

t

I

NTL

P2.4–P2.7 100 – – ns

,

P4.0–P4.7 100

RESET input low width

t

RSL

Input 10 – –

µs

NOTE: User must keep the larger value with the min value.

t

INTL

Figure 14-3. Input Timing for External Interrupts (Port 2 and 4)

0.2 V

0.8 V

DD

DD

t

INTH

14-6

S3C8075/P8075 ELECTRICAL DATA

t

RSL

RESET

0.2 V

DD

Figure 14-4. Input Timing for RESETRESET

Table 14-6. Oscillation Characteristics

(TA = – 20 °C + 85 °C, V

= 4.5 V to 5.5 V)

DD

Oscillator Clock Circuit Test Condition Min Typ Max Unit

Crystal

Ceramic

External clock

C1

C2

C1

C2

X

X

X

X

X

X

IN

OUT

IN

OUT

IN

OUT

Oscillation frequency 1 – 22.1184 MHz

Oscillation frequency 1 – 22.1184 MHz

XIN input frequency 1 – 22.1184 MHz

14-7

ELECTRICAL DATA S3C8075/P8075

Table 14-7. Main Oscillator Clock Stabilization Time (t

(T

= – 20 °C + 85 °C, VDD = 4.5 V to 5.5 V)

A

ST1

)

Oscillator Test Condition Min Typ Max Unit

Crystal VDD = 4.5 V to 5.5 V – – 20 ms
Ceramic Stabilization occurs when VDD is equal to the minimum

– – 10 ms

oscillator voltage range.

NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation

frequency after a power-on occurs, or when Stop mode is released by a RESET signal.

CPU clock

12 MHz

4 MHz

1 MHz

2 3 4 5 6 71 2.7 4.5

Figure 14-5. Frequency VS. Voltage

5.5

V

DD

14-8

S3C8075/P8075 MECHANICAL DATA

15 MECHANICAL DATA

OVERVIEW

The S3C8075 microcontroller is available in a 64-pin SDIP package (64-SDIP-750) and a 64-pin QFP package
(64-QFP-1420F).

#64 #33

64-SDIP-750

17.00 ± 0.2

#1

58.20 MAX

57.80 ± 0.2

0.45 ± 0.1

(1.34)

1.00 ± 0.1

1.778

#32

19.05

0.51MIN 4.10 ± 0.2

5.08MAX

3.30 ± 0.3

+0.1

0.25

0−15

– 0.05

°

NOTE: Dimensions are in millimeters .

Figure 15-1. 64-SDIP-750 Package Dimensions

15-1

MECHANICAL DATA S3C8075/P8075

13.20 ± 0.3

10.00 ± 0.2

#44

0.80

13.20 ± 0.3

10.00 ± 0.2

44-QFP-1010B

#1

0.35

+0.10

- 0.05

(1.00)

0-8°

+0.10

0.15

- 0.05

0.10 MAX

0.05 MIN

2.05 ± 0.10

2.30 MAX

0.80±0.20

NOTE: Dimensions are in millimeters.

Figure 15-2. 64-QFP-1420F Package Dimensions

15-2

S3C8075/P8075 S3P8075 OTP

16 S3P8075 OTP

OVERVIEW

The S3C8075 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8075

microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data
format.

S3P8075 is fully compatible with S3C8075, both in function and in pin configuration. As it has simple
programming requirements, S3P8075 is ideal for use as an evaluation chip for the S3C8075.

16-1

S3P8075 OTP S3C8075/P8075

S3P8075

SDATA

SCLK

P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10

P0.1/A9

P0.0/A8
P4.7/INT11
P4.6/INT10

P4.5/INT9
P4.4/INT8
P4.3/INT7

P4.2/INT6
/P4.1/INT5/TDG
/P4.0/INT4/TCG

V

DD/VDD1

V

SS/VSS1

X

OUT

X

IN

/EA

V

PP

P5.6
P5.7

RESETRESET /RESET

P3.7/RxD

P3.6/TxD

P3.5/TB
P3.4/TA

P3.3

P3.2
P3.1/TDCK
P3.0/TCCK

P6.0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

64-SDIP

(Top View)

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P0.7/A15
P1.0/AD0
P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
V

DD2

V

SS2

P2.0/

AS

P2.1/

DS

P2.2/R/
P2.3/
P2.4/INT0/
P2.5/INT1
P2.6/INT2
P2.7/INT3
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1

W

DM

WAIT

Figure 16-1. S3P8075 Pin Assignments (64-SDIP Package)

16-2

S3C8075/P8075 S3P8075 OTP

P1.4/AD4

P1.3/AD3

P1.2/AD2

P1.1/AD1

P1.0/AD0

P0.7/A15

P0.6/A14

P0.5/A13

P0.4/A12

P0.3/A11

P0.2/A10

P0.1/A9

P0.0/A8

52

53

54

55

56

57

58

59

60

61

62

63

64

51

P4.7/INT11
P4.6/INT10

P4.5/INT9
P4.4/INT8
P4.3/INT7

SDAT /P4.1/INT5/TDG
SCLK/P4.0/INT4/TCG

P4.2/INT6

VDD/V

DD1

VSS/V

SS1

X

OUT

XIN

VPP/EA

P5.6

RESETRESET /RESET

P5.7

P3.7/RxD

P3.6/TxD

P3.5/TB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

20

21

22

S3P8075

64-QFP

(Top View)

26

25

24

23

27

28

32

31

30

29

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
V

DD2

V

SS2

P2.0/AS
P2.1/DS
P2.2/R/W
P2.3/DM
P2.4/INT0/
P2.5/INT1
P2.6/INT2
P2.7/INT3

WAIT

P6.7

P6.6

P6.5

P6.4

P6.3

P6.2

P6.1

P6.0

P3.0/TCCK

P3.1/TDCK

P3.2

P3.3

P3.4/TA

Figure 16-2. S3P8075 Pin Assignments (64-QFP Package)

16-3

S3P8075 OTP S3C8075/P8075

Table 16-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P4.1 SDAT 14 (7) I/O Serial Data Pin (Output when reading, Input

when writing) Input and Push-pull Output Port
can be assigned.

P4.0 SCLK 15 (8) I Serial Clock Pin (Input Only Pin)

EA

V

PP

20 (13) I EPROM Cell Writing Power Supply Pin

(Indicates OTP Mode Entering) When writing

12.5V is applied and when reading 5 V is applied
(Option).

RESET RESET

V

DD1/VSS1

NOTE: Parentheses indicate 64-QFP pin number.

VDD/V

SS

23 (9) I Chip Initialization
16/17

(9/10)

Logic Power Supply Pin. VDD should be tied to

I

5V during programming.

Table 16-2. Comparison of S3P8075 and S3C8075 Features

Characteristic S3P8075 S3C8075

Program Memory 16 Kbyte EPROM 16 Kbytes mask ROM
Operating Voltage (VDD)

OTP Programming Mode

2.7 V to 5.5 V 2.7 V to 5.5V
VDD = 5 V, V

(TEST) = 12.5V

PP

Pin Configuration 64 SDIP, 64 QFP 64 SDIP, 64 QFP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the V

(TEST) pin of S3P8075, the EPROM programming mode is entered. The

PP

operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15-3 below.

Table 16-3. Operating Mode Selection Criteria

V

DD

V

PP

(TEST)

REG/

MEMMEM

ADDRESS

(A15–A0)

R/WW

MODE

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

16-4

S3C8075/P8075 S3P8075 OTP

D.C. ELECTRICAL CHARACTERISTICS

Table 16-4. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Input High
Voltage

Input Low Voltage

Output High
Voltage

Output Low
Voltage

V

V

V
V

V

V

V

V

IH1

IH2
IL1
IL2

OH1

OH2

OL1

OL2

All input pins except V

X

IN

All input pins except V
X

IN

V

= 4.5 V to 5.5 V

DD

IH2

IL2

IOH = – 4 mA
Port 5, 6

VDD = 4.5 V to 5.5 V
IOH = – 1 mA
All output pins except port 5, 6

V

= 4.5 V to 5.5 V

DD

IOL = 15 mA
Ports 5 and 6

IOL = 2 mA
Ports 0 - 4

0.8 V

V

DD

V

DD

V

DD

DD

– 0.5

– 1.0

– 1.0

V

DD

0.2 V

DD

0.4

1.0 V

0.4

V

V

V

16-5

S3P8075 OTP S3C8075/P8075

Table 16-4. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Input High Leakage
Current

Input Low Leakage
Current

Output High
Leakage Current

Output Low

I

LIH1

I

LIH2

I

LIL1

I

LIL2

I

LOH

I

LOL

V

= V

IN

DD

All input pins except XIN, X
V
V

IN

= 0 V

IN

= V

DD

XIN, X

,

OUT

All input pins except XIN, X
V
V

IN
OUT

= 0 V, X

= V

DD

, X

IN

OUT

All output pins
V

= 0 V

OUT

– – 3 uA

OUT

20

– – – 3 uA

OUT

– 20

– – 5 uA

– – – 5 uA

Leakage Current
Pull-up Resistor

R

L1

V

IN

= 0 V; V

DD

= 5 V

30 47 70

KΩ

Ports 0, 1, 4, 5 and 6

R

L2

V

IN

= 0 V; V

DD

= 5 V

110 210 310

RESET only

Supply Current

(1)

I

DD1

(2)

V

= 5 V ± 10%

DD

– 12 25 mA

12-MHz oscillation
4-MHz oscillation 4.5 10
V

= 3 V ± 10%

DD

6 15

12-MHz oscillation
4-MHz oscillation 2.5 7

I

DD2

(2)

Idle mode; VDD = 5 V ± 10 %

2.5 6

12-MHz oscillation
4-MHz oscillation 1.5 4
Idle mode; VDD = 3 V ± 10 %

1.2 3

12-MHz oscillation
4-MHz oscillation 0.6 1.5

I

DD3

Stop mode:
V

= 5 V ± 10 %

DD

0.1 3 uA

NOTES:

1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.

2. At supply current, the CPU clock frequency is the same as oscillation frequency (CPU use non divided clock).

16-6

S3C8075/P8075 S3P8075 OTP

START

Address= First Location

VDD=5V, VPP=12.5V

x = 0

Program One 1ms Pulse

Increment X

FAIL

Device Failed

Verify Byte

YES

x = 10

NO

FAIL

NO

FAIL

Verify 1 Byte

Last Address

V

= VPP= 5 V

DD

Compare All Byte

PASS

Device Passed

Figure 16-3. OTP Programming Algorithm

Increment Address

16-7

S3P8075 OTP S3C8075/P8075

NOTES

16-8