Page 1
S3C8454/P8454 PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
SAM87 RC PRODUCT FAMILY
Samsung's new SAM87RC family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a
wide range of integrated peripherals, and various mask-programmable ROM sizes. Timer/counters with
selectable operating modes are included to support real-time operations. Many SAM87RC microcontrollers have
an external interface that provides access to external memory and other peripheral devices. The sophisticated
interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and
vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels.
S3C8454 MICROCONTROLLER
The S3C8454 single-chip microcontroller is fabricated using a highly advanced CMOS process. Its design is
based on the powerful SAM87RC CPU core. Stop and Idle power-down modes were implemented to reduce
power consumption. The size of the internal register file is logically expanded, increasing the addressable on-chip
register space to 1040 bytes. A flexible yet sophisticated external interface is used to access up to 64-Kbytes of
program and data memory. The S3C8454 is a versatile microcontroller that is ideal for use in a wide range of
general-purpose applications such as CD-ROM/DVD-ROM drives.
Using the SAM87RC modular design approach, the following peripherals were integrated with the SAM87RC
CPU core:
— Five configurable 8-bit general I/O ports
— One 2-bit general I/O ports
— Full-duplex serial data port with one synchronous operating modes
— Two 8-bit timers with interval timer
— Two 16-bit timers/counters with PWM operating modes or capture modes
— One voltage level detector pin
— Four embedded chip selection pins (CS0–CS4) or normal I/O ports
— Two programmable 8-bit PWM modules with corresponding output pins
— A/D converter with 4 selectable input pins
OTP
The S3C8454 microcontroller is also available in OTP(One Time Programmable) version, S3P8454
The S3P8454 microcontroller has an on-chip 4K-byte one-time-programmable EPROM instead of masked ROM.
The S3P8454 is comparable to S3C8454, both in function and in pin configuration.
1-1
Page 2
PRODUCT OVERVIEW KS88C4504/P4504
FEATURES
CPU
• SAM87RC CPU core
Memory
• 1040-byte internal register file
• 4-Kbyte internal program memory
External Interface
• 64 Kbyte external data memory
• 64 Kbyte external program memory area
(ROMless)
• 60 Kbyte external program memory and 4 Kbyte
internal program memory
ADC
• Can be used as a general input/output port
• 8-bit resolution four channels
SIO
• 8-bit transmit/receive mode
• 8-bit receive mode
General I/O Ports
• Five 8-bit general I/O ports (port 0, 1, 2, 3, 4)
• One 2-bit general I/O port (port 5)
• Port 2 can drive LED directly
Interrupts
• Six edge-driven external interrupts
• Two level-driven external interrupts
• Fast interrupt mode processing
PWM
• Four output channels
(PWM0, PWM1, TCPWM, TDPWM)
• 8-bit resolution with a 4-bit prescaler
(PWM0, PWM1)
• From 16-bit counter (Timer C/D)
(TCPWM, TDPWM)
Embedded chip selection
• To reduce interface glue logic, chip selection
logic is bold
• LSB-first or MSB-first transmission selectable
• Internal or external clock mode
8-bit Timers
• Two 8-bit timers with interval timer mode
(Timer A and B)
16-bit Timer/Counters
• Two programmable 16-bit timer/counters
• Interval, or event counter mode operation
• 16-bit capture and 16-bit PWM mode
• Internal or external clock source
Basic Timer (Watchdog Timer)
• Overflow signal makes a system reset
• 8-bit timer with interval timer mode
Voltage level detector
• To prevent MCU from malfunctioning in an
unstable power level, a voltage level detector
circuit is inserted
Operating Voltage Range
• 2.7 V to 5.5 volts (@12 MHz)
Operating Temperature Range
• – 40 °C to + 85 °C
Package Types
• 80-pin QFP or TQFP
Operating frequency
• 25 MHz (4.5 V to 5.5 V)
1-2
Page 3
S3C8454/P8454 PRODUCT OVERVIEW
TDCAP, TCCAP
TCOUT, TDOUT
BLOCK DIAGRAM
External Address/Data
P5.1
P5.0(
WAIT
P4.0-P4.7/
CS0-CS4
TCCK
TDCK
TCOUT
TDOUT
SCK
SO
SI
)
RESET
EA
Port 5
Port4/
Chip
Selection
Logic
Timers
A and B
Timers
C and D
Serial
Port
AV
SS
(Internal)
AV
REF
(A8-A15)
A/D
Converter
(A0-A7)
External Interface Block
SAM8 BUS
Port I/O
& Interrupt
Control
SAM87 RC CPU
1040-Byte
Register File
SAM8 BUS
4-Kbyte
ROM
Watchdog
Timer
(D0-D7)
PWM
Module
Port 0
Port 1
Port 2
Port 3
V
V
P0.0-P0.3
P0.4-P0.7/
ADC0-ADC3
P1.0-P1.4
P1.5-P1.7/
SI, SO, SCK
P2.0-P2.7/
INT0-INT7
P3.0-P3.7/
TDCK, TCCK
PWM0, PWM1
DD1, VSS1
DD2, VSS2
PWM0 PWM1ADC0/P0.4-
ADC3/P0.7
Figure 1-1. S3C8454 Block Diagram
1-3
Page 4
PRODUCT OVERVIEW KS88C4504/P4504
PIN ASSIGNMENT
A10
A11
A12
A13
A14
A15
80
79
78
77
76
75
A9
74
A8
73
A7
72
A6
71
A5
70
A4
69
A3
68
A2
67
A1
66
A0
65
PM
DM
RD
WR
VLD
P5.1
P5.0/WAIT
CS3/P4.7
CS2/P4.6
CS1/P4.5
CS0/P4.4
VDD1
VSS1
XOUT
XIN
EA
P4.3
P4.2
RESET
P4.1
P4.0
PWM1/P3.7
PWM0/P3.6
TDOUT/P3.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
KS88C4504
80-QFP
(Top View)
30
29
28
27
31
32
33
34
35
36
37
38
39
40
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D7
D6
D5
D4
D3
D2
D1
D0
P0.0
P0.1
P0.2
VDD2
VSS2
P0.3
AVREF
P0.4/ADC0
P0.5/ADC1
P0.6/ADC2
P0.7/ADC3
P1.0
P1.1
P1.2
P1.3
P1.4
1-4
P1.5/SI
P1.6/SO
P1.7/SCK
P2.0/INT0
P2.1/INT1
P2.2/INT2
P2.3/INT3
P2.4/INT4
P2.5/INT5
P2.6/INT6
P2.7/INT7
P3.0/TDCK
P3.1/TCCK/
P3.2/TDCAP
P3.3/TCCAP
P3.4/TCOUT
Figure 1-2. S3C8454 Pin Assignments
Page 5
S3C8454/P8454 PRODUCT OVERVIEW
PIN ASSIGNMENTS (Continued)
A10
A11
A12
A13
A14
A15
80
79
78
77
76
75
A9
74
A8
73
A7
72
A6
71
A5
70
A4
69
A3
68
A2
67
A1
66
A0
65
D7
64
D6
63
D5
62
D4
61
PM
DM
RD
WR
VLD
P5.1
P5.0/WAIT
CS3/P4.7
CS2/P4.6
CS1/P4.5
CS0/P4.4
VDD1
VSS1
XOUT
XIN
EA
P4.3
P4.2
RESET
P4.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
23
22
21
PWM0/P3.6
PWM1/P3.7
P4.0
KS88C4504
28
27
26
25
24
P3.1/TCCK/
P3.2/TDCAP
P3.3/TCCAP
P3.4/TCOUT
TDOUT/P3.5
80-TQFP
(Top View)
32
31
30
29
P2.5/INT5
P2.6/INT6
P2.7/INT7
P3.0/TDCK
36
35
34
33
P2.1/INT1
P2.2/INT2
P2.3/INT3
P2.4/INT4
40
39
38
37
P1.5/SI
P1.6/SO
P1.7/SCK
P2.0/INT0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D3
D2
D1
D0
P0.0
P0.1
P0.2
VDD2
VSS2
P0.3
AVREF
P0.4/ADC0
P0.5/ADC1
P0.6/ADC2
P0.7/ADC3
P1.0
P1.1
P1.2
P1.3
P1.4
Figure 1-3. S3C8454 Pin Assignments
1-5
Page 6
PRODUCT OVERVIEW KS88C4504/P4504
PIN DESCRIPTIONS
Table 1-1. S3C8454/P8454 Pin Descriptions
Pin
Name
Pin
Type
Pin Description Circuit
P0.0–P0.7 I/O Bit programmable port; input or output mode
selected by software; normal input or push-pull
output with software assignable pull-up (P0.0–P0.3)
or pull-down (P0.4–P0.7). Alternately, P0.4–P0.7 can
be use as a ADC input port with
8-bit resolution.
P1.0–P1.7 I/O Bit programmable port; input or output mode
selected by software; normal input or push-pull
output with software assignable pull-up. P1.5–P1.7
can be used as a synchronous SIO port
P1.5/SI
P1.6/SO
P1.7/SCK
P2.0–P2.7 I/O General I/O port with normal input or push-pull output
with software; assignable pull-up. Bit programmable.
Alternately, P2.0–P2.7 can be used as inputs for
external interrupts, INT0–INT7 (with noise filter and
interrupt control). INT0/INT1 is level interrupts.
P3.0–P3.7 I/O General I/O port with bit programmable pins.
Normal input or push-pull output with software
assignable pull-up. Input or output mode is selectable
by software. Respectively, each pin can serve as
(with noise filters):
P3.0/timer D clock input (TDCK)
P3.1/timer C clock input (TCCK)
P3.2/timer D capture input (TDCAP)
P3.3/timer C capture input (TCCAP)
P3.4/timer C out (TCOUT)/PWM out (TCPWM)
P3.5/timer D out (TDOUT)/PWM out (TDPWM)
P3.6/PWM0 output port
P3.7/PWM1 output port
P4.0–P4.7 I/O General I/O port with bit programmable pins.
Normal input or push-pull output with software
assignable pull-up. Input or output mode is selectable
by software. P4.0–P4.7 can alternately be used as
inputs for embedded chip selection output.
P4.4/CS0
P4.5/CS1
P4.6/CS2
P4.7/CS3
Pin
Type
Number
2, 3 56–54,
51, 49–46
Share
Pins
ADC0–
ADC3
3 45–38 SI, SO,
SCK
4 37–30 INT0–
INT7
3, 5 29–22 TDCK
TCCK
TDCAP
TCCAP
TDOUT/
TDPWM
TCOUT/
TCPWM
PWM0
PWM1
3, 5 21, 20,
CS0–CS3
18, 17,
11–8
1-6
Page 7
S3C8454/P8454 PRODUCT OVERVIEW
Table 1-1. S3C8454/P8454 Pin Descriptions (Continued)
Pin
Name
P5.0–P5.1 I/O General I/O port with bit programmable pins.
Pin
Type
Pin
Description
Circuit
Type
QFP Pin
Number
5 7 WAIT
Share
Pins
Normal input or push-pull, output mode.
Alternately It can use as external interface
control signal P5.0/WAIT signal
ADC0–ADC3 I Analog input pins for A/D converter module.
2 49–46 P0.4–P0.7
Alternatively used as general-purpose I/O
AV
REF
– A/D converter reference voltage
50 –
AVSS is connected to ground internally
PWM0, PWM1 O Pulse width modulation output pins 5 23,22 P3.6, P3.7
INT0–INT7 I External interrupt input pins 4 37–30 P2.0–P2.7
TCCK, TDCK I External clock input for timer C and timer D 3 28,29 P3.1/P3.0
TCCAP,TDCAP I Timer C/ timer D capture input 3 26,27 P3.3/P3.2
WAIT
I Input pin for the slow memory timing signal
5 7 P5.0
from the external interface
I
RESET
System reset pin (pull-up resistor: 240 kΩ)
EA I 5V: ROMless operating
1 19 –
– 16 –
0V: internal 4 K and external 60 K
addressing mode
V
DD1
, V
SS1
– Power input pins for CPU operation (internal)
– 12,13 –
and Power input for OTP writing
V
, V
DD2
SS2
XIN, X
OUT
SI, SO, SCK
– Power input pins for port output (external) – 53, 52 –
– Main oscillator pins – 15, 14 –
I/O synchronous SIO communication port 3 40,39,38 P1.5/P1.6
P1.7
A0–A15 O Address output for external device 6 65–80 –
D0–D7 I/O Data I/O for external device 7 57–64 –
PM,DM
RD,WR
CS0–CS3
O External memory selection output – 1, 2 –
O Memory read/write output – 3, 4 –
O Embedded chip selection output 5 11–8 P4.4–P4.7
TCOUT,TDOUT O 16-bit timer PWM mode output 5 25, 24 P3.4, P3.5
VLD – Voltage Level Detect Pin – 5 –
NOTE: V
must be connected to V
DD1
in users application circuit, V
DD2
SS1
& V
SS2
also.
1-7
Page 8
PRODUCT OVERVIEW KS88C4504/P4504
PIN CIRCUITS
Table 1-2. Pin Circuit Assignments for the S3C8454/P8454
Circuit Number Circuit Type S3C8454 Assignments
1 Input
2 I/O A/D converter input pins, ADC0–ADC3, P0.4–P0.7
3 I/O Port 0, 1, 3, 4, and 5
4 I/O P2 (INT0–INT7)
5 I/O P3 (TDCK, TCCK, TDCAP, TCCAP, TCOUT, TDOUT, TCPWM,
6 Output
7 I/O D0–D7
RESET pin
TDPWM, PWM0, PWM1)
A0–A15,PM, DM, RD, WR
1-8
Page 9
S3C8454/P8454 PRODUCT OVERVIEW
VDD
Pull-up
Resistor
(Typical 240 kΩ)
Input
Figure 1-4. Pin Circuit Type 1 (RESETRESET)
VDD
Data
Output
Disable
Normal
Input
ADC Port
Selection
ADC In
Pull-Down
Enable
Enable ADC
Figure 1-5. Pin Circuit Type 2 (ADC0–ADC3)
I/O
Vss
1-9
Page 10
PRODUCT OVERVIEW KS88C4504/P4504
VDD
Pull-Up
Enable
VDD
Data
I/O
Output
Disable
Normal
Input
External
Interrupt
Input
SCK Input
Noise
Filter
Figure 1-6. Pin Circuit Type 3
VDD
Pull-Up
Resistor
Pull-Up
Enable
VDD
Data
I/O
Output
Disable
Vss
Noise Filter
1-10
Normal
Input
Figure 1-7. Pin Circuit Type 4
Page 11
S3C8454/P8454 PRODUCT OVERVIEW
VDD
Pull-Up
Resistor
Pull-Up
Enable
VDD
Data
Selection bits
for ports or
other function
Output
Disable
Input
Other
Function
Vss
Figure 1-8. Pin Circuit Type 5
VDD
In
Out
I/O
Figure 1-9. Pin Circuit Type 6
1-11
Page 12
PRODUCT OVERVIEW KS88C4504/P4504
VDD
Data
I/O
Output
Disable
Normal
Input
Figure 1-10. Pin Circuit Type 7
1-12
Page 13
S3C8454/P8454 ELECTRICAL DATA
18 ELECTRICAL DATA
OVERVIEW
In this section, S3C8454 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— A.C. electrical characteristics
— I/O capacitance
— Oscillation characteristics
— Oscillation stabilization time
18-1
Page 14
ELECTRICAL DATA S3C8454/P8454
Table 18-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter Symbol Conditions Rating Unit
Supply voltage V
Input voltage V
Output voltage V
Output current high I
DD
OH
I
O
All ports (in input mode) – 0.3 to V
All ports (in output mode) – 0.3 to VDD + 0.3 V
One I/O pin active – 18 mA
– 0.3 to + 6.5 V
+ 0.3
DD
All I/O pins active – 60
Output current low I
OL
One I/O pin active + 30 mA
Total pin current for port + 100
Operating
T
A
– 40 to +85 °
C
temperature
Storage temperature T
STG
– 65 to +150 °
C
18-2
Page 15
S3C8454/P8454 ELECTRICAL DATA
Table 18-2. D.C. Electrical Characteristics
(T
= – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Unit
Operating voltage V
DD
f
OSC
= 25 MHz
4.5 – 5.5 V
(instruction clock = 6.25 MHz)
f
= 12 MHz
OSC
2.7 – 5.5
(instruction clock = 3 MHz)
Input high voltage V
V
IH1
IH2
All input pins except V
X
IN
IH2
, V
IH3
0.51 V
V
DD
DD
– 0.5
– V
DD
V
Input low voltage V
Output high voltage V
Output low voltage V
V
Input high leakage
current
Input low leakage
current
Output high leakage
current
Output low leakage
current
Pull-up and pull-down
resistor
V
V
V
OL1
OL2
I
LIH1
I
LIH2
I
LIL1
I
LIL2
I
LOH
I
LOL
R
IH3
IL1
IL2
IL3
OH
L1
Test, RESET
All input pins except V
X
IN
IL2
, V
IL3
Test, RESET
VDD= 5 V
IOH = – 1 mA
IOH = – 100 uA V
V
= 5 V
DD
IOL = 2 mA
All output pins except port 2
V
= 5 V
DD
IOL = 15 mA, port 2
VIN = V
All input pins except X
VIN = V
X
V
IN
= 0 V
IN
DD
IN
DD
All input pins except XIN and
RESET
V
= 0 V,
IN
X
RESET
IN,
V
= V
OUT
DD
All I/O pins and output pins
V
= 0 V
OUT
All I/O pins and output pins
V
= 0 V; V
IN
= 5 V ± 10%
DD
Ports 0-5, TA = 25 °C
0.8V
DD
– – 0.2 V
DD
0.4
0.2V
DD
V
– 1.0 – – V
DD
– 0.5 – –
DD
–
– – 0.4 V
– 0.5 1.0
– – 3
20
– – – 3
– 20
– – 5
– – 0 – 5
30 46 80
V
µA
kΩ
R
L2
V
IN
= 0 V; V
= 5 V ± 10%
DD
120 240 320
TA = 25 °C, RESET only
18-3
Page 16
ELECTRICAL DATA S3C8454/P8454
Table 18-2. D.C. Electrical Characteristics (Continued)
(T
= – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Unit
Supply current
(note)
I
DD1
V
= 5 V ± 10 %
DD
20 40 mA
20 MHz oscillation
V
= 2.7 V
DD
7 14
12 MHz oscillation
I
DD2
Idle mode; V
= 5 V ± 10 %
DD
8 16
20 MHz oscillation
Idle mode; VDD = 2.7 V
3 6
12 MHz oscillation
I
DD3
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Stop mode;
V
= 5 V ± 10 %
DD
LVD enable, T
= 25 °C
A
110 220
µA
Table 18-3. A.C. Electrical Characteristics
(T
= -40 °C to + 85 °C)
A
Parameter Symbol Conditions Min Typ Max Unit
Interrupt input high, low
width
(P2.0–P2.7)
RESET input low width
NOTES:
1. The unit t
2. The oscillator frequency is the same as the CPU clock frequency.
means one CPU clock period.
CPU
t
INTH
t
INTL
t
RSL
V
,
= 5 V 180 – – nS
DD
VDD = 5 V 1000 – – nS
0.8 VDD
0.2 VDD
tINTHtINTL
18-4
Figure 18-1. Input Timing for External Interrupts (Ports 2)
Page 17
S3C8454/P8454 ELECTRICAL DATA
tRSL
RESET
0.2 VDD
Figure 18-2. Input Timing for RESETRESET
Table 18-4. Input/Output Capacitance
(T
= – 40 °C to + 85 °C, V
A
DD
= 0 V)
Parameter Symbol Conditions Min Typ Max Unit
Input capacitance C
Output capacitance C
I/O capacitance C
IN
OUT
IO
f = 1 MHz; unmeasured
pins are connected to V
– – 10 pF
SS
Table 18-5. Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter Symbol Conditions Min Typ Max Unit
Data retention supply
V
DDDR
2 – 5.5 V
voltage
Data retention supply
I
DDDR
Stop mode, V
= 2.0 V – – 50
DDDR
current
NOTES:
1. During the oscillator stabilization wait time (t
2. Supply current does not include drawn through internal pull–up resistors and external output current loads.
), all CPU operations must be stopped.
WAIT
µA
18-5
Page 18
ELECTRICAL DATA S3C8454/P8454
Oscillation
Stabilization
Time
Normal
Operating
Mode
VDD
RESET
~
~
Execution of
STOP Instrction
Reset
Occurs
~
~
Stop Mode
Data Retention Mode
VDDDR
0.2 VDD
NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC.
Figure 18-3. Stop Mode Release Timing Initiated by RESETRESET
tWAIT
18-6
Page 19
S3C8454/P8454 ELECTRICAL DATA
Table 18-6. A/D Converter Electrical Characteristics
(T
= – 40 °C to + 85 °C)
A
Parameter Symbol Conditions Min Typ Max Unit
Resolution – 8 – bit
Total accuracy V
= 5 V – – ± 2 LSB
DD
Integral linearity error ILE Conversion time = 5 us – ± 1
Integral linearity error DLE AV
Offset error of top EOT AV
= 5 V – ± 1
REF
= 0 V ± 1 ± 2
SS
Offset error of bottom EOB ± 0.5 ± 2
Conversion time
(1)
Analog input voltage V
Analog input impedance R
Analog reference voltage AV
Analog ground AV
Analog input current I
Analog block I
current
(2)
t
CON
IAN
ADIN
ADC
AN
REF
SS
17 – 170
AVss – AV
– 2 1000 –
– 2.5 – V
– V
AV
= VDD = 5 V – – 10 uA
REF
AV
= VDD = 5 V 1 3 mA
REF
AV
= VDD = 3 V 0.5 1.5 mA
REF
AV
= VDD = 5 V
REF
SS
– VSS+ 0.3 V
100 500 nA
REF
DD
µs
V
MΩ
V
When power down mode
NOTES:
1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends.
2. I
is an operating current during A/D conversion.
ADC
18-7
Page 20
ELECTRICAL DATA S3C8454/P8454
VDD
Reference
Voltage
Input
Analog
Input Voltage
NOTE: The symbol 'R' signifies an offset resistor with a value of from 50 to 100.
If this resistor is omitted, the absolute accuracy will be maximum of 3 LSBs.
10 pF 103
+
-
C
C
101
R
AVREF
VDD
ADC0-ADC3
S3C8454
VSS
Figure 18-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy
18-8
Page 21
S3C8454/P8454 ELECTRICAL DATA
Table 18-7. Synchronous SIO Electrical Characteristics
(T
= – 40 °C to + 85 °C, VDD = 4.5 V to 5.5 V, VSS = 0 V, f
A
= 10 MHz oscillator)
OSC
Parameter Symbol Conditions Min Typ Max Unit
SCK cycle time t
Serial clock high width t
Serial clock low width T
Serial output data delay
CYC
SCKH
SCKL
T
OD
– 200 – – nS
– 60 – –
– 60 – –
– – – 50
time
Serial input data set up
T
ID
– 40 – –
time
Serial input data hold
T
IH
– 100 – –
time
tCYC
SCK
SI
SO
tOD
tSCKL
tID tIH
Input Data
Output Data
tSCKH
Figure 18-5. Serial Data Transfer Timing
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
18-9
Page 22
ELECTRICAL DATA S3C8454/P8454
(TA = – 40 °C + 85 °C, V
Table 18-8. Main Oscillator Frequency (f
= 4.5 V to 5.5 V)
DD
OSC1
)
Oscillator Clock Circuit Test Condition Min Typ Max Unit
Crystal
Ceramic
External clock
XIN
XOUT
C1 C2
XIN
XOUT
C1 C2
XIN XOUT
CPU clock oscillation
4 – 25 MHz
frequency
CPU clock oscillation
4 – 25 MHz
frequency
XIN input frequency 4 – 25 MHz
Table 18-9. Main Oscillator Clock Stabilization Time (t
(T
= -40 °C + 85 °C, VDD = 4.5 V to 5.5 V)
A
ST1
)
Oscillator Test Condition Min Typ Max Unit
Crystal VDD = 4.5 V to 5.5 V – – 10 ms
Ceramic Stabilization occurs when VDD is equal to the minimum
– – 4 ms
oscillator voltage range.
External clock XIN input high and low level width (tXH, tXL) 50 – – ns
NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation
frequency after a power-on occurs, or when Stop mode is ended by a RESET signal. The RESET should therefore
be held at low level until the t
time has elapsed.
ST1
18-10
Page 23
S3C8454/P8454 ELECTRICAL DATA
1/fOSC1
tXHtXL
XIN
Figure 18-6. Clock Timing Measurement at X
Table 18-10. Characteristics of Voltage Level Detect circuit
(TA = – 40 °C + 85 °C)
Parameter Symbol Conditions Min Typ Max Unit
Operating Voltage of VLD V
Detect Voltage V
Current consumption I
DDVLD
VLD
VLD
VDD - 0.5 V
0.4 V
IN
– 2.7 – 5.5 V
– 1.15 1.40 1.51 V
VDD = 5.5 V – 100 200 uA
18-11
Page 24
ELECTRICAL DATA S3C8454/P8454
fOSC
2.7
B
4.5
25 MHz
18 MHz
16 MHz
14 MHz
12 MHz
4 MHz
1 2 3 4 5 6 7
Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
A
Supply Voltage (V)
Figure 18-7. Operating Voltage Range
fCPU
6.25 MHz
4.5 MHz
4 MHz
3.5 MHz
3 MHz
1 MHz
18-12
Page 25
S3C8454/P8454 MECHANICAL DATA
19 MECHANICAL DATA
OVERVIEW
The S3C8454 microcontroller is available in a 80-pin QFP package (80-QFP-1420C) and a 80-pin TQFP
package (80-TQFP-1212AN).
23.90 ± 0.30
17.90 ± 0.30
14.00 ± 0.20
#80
0.80
#1
20.00 ± 0.20
80-QFP-1420C
0.35 + 0.10
0.15 MAX
(0.80)
0-8
+ 0.10
- 0.05
0.15
0.10 MAX
0.80 ± 0.20
0.05 MIN
2.65 ± 0.10
3.00 MAX
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 19-1. 80-QFP-1420C Package Dimensions
19-1
Page 26
MECHANICAL DATA S3C8454/P8454
14.00 BSC
12.00 BSC
14.00 BSC
#80
0.50
#1
12.00 BSC
80-TQFP-1212
0.17-0.27
0-7
0.09-0.20
0.60 ± 0.15
0.05-0.15
(1.25)
1.00 ± 0.05
19-2
1.20 MAX
NOTE: Dimensions are in millimeters.
Figure 19-2. 80-TQFP-1212AN Package Dimensions
Page 27
S3C8454/P8454 S3P8454 OTP
20 S3P8454 OTP
OVERVIEW
The S3P8454 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8454
microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data
format.
S3P8454 is fully compatible with S3C8454, both in function and in pin configuration. As it has simple
programming requirements, S3P8454 is ideal for use as an evaluation chip for the S3C8454.
20-1
Page 28
S3P8454 OTP S3C8454/P8454
A10
A11
A12
A13
A14
A15
80
79
78
77
76
75
A9
74
A8
73
A7
72
A6
71
A5
70
A4
69
A3
68
A2
67
A1
66
A0
65
PM
DM
RD
WR
VLD
P5.1
P5.0/WAIT
CS3/P4.7
CS2/P4.6
SDAT/CS1/P4.5
SCLK/CS0/P4.4
VDD1/VDD1
VSS1/VSS1
XOUT
XIN
VPP/EA
P4.3
P4.2
RESETRESET/RESET
P4.1
P4.0
PWM1/P3.7
PWM0/P3.6
TDOUT/P3.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
S3P8454
30
29
28
80-QFP
(Top View)
34
33
32
31
35
36
37
38
39
40
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D7
D6
D5
D4
D3
D2
D1
D0
P0.0
P0.1
P0.2
VDD2
VSS2
P0.3
AVREF
P0.4/ADC0
P0.5/ADC1
P0.6/ADC2
P0.7/ADC3
P1.0
P1.1
P1.2
P1.3
P1.4
P2.6/INT6
P2.7/INT7
P3.0/TDCK
P3.1/TCCK
P3.2/TDCAP
P3.3/TCCAP
P3.4/TCOUT
NOTE: The bolds indicates OTP pin name.
Figure 20-1. S3P8454 Pin Assignments (80-QFP Package)
20-2
P2.2/INT2
P2.3/INT3
P2.4/INT4
P2.5/INT5
P1.7/SCK
P2.0/INT0
P2.1/INT1
P1.5/SI
P1.6/SO
Page 29
S3C8454/P8454 S3P8454 OTP
A10
A11
A12
A13
A14
A15
80
79
78
77
76
75
A9
74
A8
73
A7
72
A6
71
A5
70
A4
69
A3
68
A2
67
A1
66
A0
65
D7
64
D6
63
D5
62
D4
61
PM
DM
RD
WR
VLD
P5.1
P5.0/WAIT
CS3/P4.7
CS2/P4.6
SDAT/CS1/P4.5
SCLK/CS0/P4.4
VDD1/VDD1
VSS1/VSS1
XOUT
XIN
VPP/EA
P4.3
P4.2
RESETRESET/RESET
P4.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
23
22
21
PWM0/P3.6
PWM1/P3.7
P4.0
28
27
26
25
24
P3.1/TCCK
P3.2/TDCAP
P3.3/TCCAP
P3.4/TCOUT
TDOUT/P3.5
S3P8454
80-TQFP
(Top View)
32
31
30
29
P2.5/INT5
P2.6/INT6
P2.7/INT7
P3.0/TDCK
36
35
34
33
P2.1/INT1
P2.2/INT2
P2.3/INT3
P2.4/INT4
40
39
38
37
P1.5/SI
P1.6/SO
P1.7/SCK
P2.0/INT0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D3
D2
D1
D0
P0.0
P0.1
P0.2
VDD2
VSS2
P0.3
AVREF
P0.4/ADC0
P0.5/ADC1
P0.6/ADC2
P0.7/ADC3
P1.0
P1.1
P1.2
P1.3
P1.4
Figure 20-2. S3P8454 Pin Assignments (80-TQFP Package)
20-3
Page 30
S3P8454 OTP S3C8454/P8454
Table 20-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip During Programming
Pin Name Pin Name Pin No. I/O Function
P4.5 SDAT 10 I/O Serial data pin (Output when reading, Input when
writing) Input and push-pull output port can be assigned.
P4.4 SCLK 11 I Serial clock pin (Input only pin)
EA
V
PP
16 I EPROM cell writing power supply pin (Indicates OTP
mode entering) When writing 12.5 V is applied and
when reading 5 V is applied (Option).
RESET RESET
V
DD1/VSS1
VDD/V
SS
19 I Chip Initialization
12/13 I
Logic Power Supply Pin. VDD should be tied to 5 V
during programming.
Table 20-2. Comparison of S3P8454 and S3C8454 Features
Characteristic S3P8454 S3C8454
Program Memory 4 Kbyte EPROM 4 Kbytes mask ROM
Operating Voltage (VDD)
2.7 V to 5.5 V 2.7 V to 5.5V
OTP Programming Mode
VDD = 5 V, V
(TEST) = 12.5V
PP
Pin Configuration 80 QFP, 80 TQFP 80 QFP, 80 TQFP
EPROM Programmability User Program 1 time Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V
(TEST) pin of S3P8454, the EPROM programming mode is entered. The
PP
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 20-3 below.
Table 20-3. Operating Mode Selection Criteria
V
DD
V
PP
(TEST)
REG
/MEM
Address
(A15–A0)
R/W Mode
5 V 5 V 0 0000H 1 EPROM read
12.5 V 0 0000H 0 EPROM program
12.5 V 0 0000H 1 EPROM verify
12.5 V 1 0E3FH 0 EPROM read protection
NOTE: "0" means Low level; "1" means High level.
20-4
Page 31
S3C8454/P8454 S3P8454 OTP
D.C. ELECTRICAL CHARACTERISTICS
Table 20-4. D.C. Electrical Characteristics
(T
= – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Unit
Operating voltage
Input high voltage
V
DD
V
IH1
f
= 25 MHz
OSC
(instruction clock = 6.25 MHz)
f
= 12 MHz
OSC
(instruction clock = 3 MHz)
All input pins except V
IH2
, V
IH3
4.5 – 5.5 V
2.7 – 5.5
0.51 VDD
–
V
DD
V
Input low voltage
Output high voltage
Output low voltage
Input high leakage
current
Input low leakage
current
Output high leakage
current
Output low leakage
current
Pull-up and pull-down
resistor
V
V
V
V
V
V
V
V
I
LIH1
I
LIH2
I
LIL1
I
LIL2
I
LOH
I
LOL
R
IH2
IH3
IL1
IL2
IL3
OH
OL1
OL2
L1
X
IN
Test, RESET
All input pins except V
X
IN
IL2
, V
IL3
Test, RESET
VDD= 5 V
IOH = – 1 mA
IOH = – 100 uA V
V
= 5 V, IOL = 2 mA
DD
All output pins except port 2
V
= 5 V, IOL = 15 mA, port 2
DD
VIN = V
All input pins except X
VIN = V
V
= 0 V
IN
DD
IN
DD, XIN
All input pins except XIN and
RESET
V
= 0 V, X
IN
V
OUT
= V
DD
RESET
IN,
All I/O pins and output pins
V
= 0 V
OUT
All I/O pins and output pins
V
= 0 V; V
IN
= 5 V ± 10%
DD
Ports 0-5, TA = 25 °C
V
– 0.5
DD
0.8V
DD
– –
0.2 V
0.4
0.2V
V
DD
DD
DD
– 1.0
– 0.5
– – V
– –
–
– – 0.4 V
– 0.5 1.0
– – 3
20
– – – 3
– 20
– – 5
– – 0 – 5
30 46 80
DD
V
µA
kΩ
R
L2
V
IN
= 0 V; V
= 5 V ± 10%
DD
120 240 320
TA = 25 °C, RESET only
20-5
Page 32
S3P8454 OTP S3C8454/P8454
Table 20-4. D.C. Electrical Characteristics (Continued)
(T
= – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Unit
Output high leakage
current
Output low leakage
current
Pull-up and pulldown resistor
I
LOH
ILOL
R
L1
V
= V
OUT
DD
All I/O pins and output pins
V
= 0 V
OUT
All I/O pins and output pins
VIN = 0 V; VDD = 5 V ± 10 %
Ports 0-5, TA = 25 °C
– – 5
– – 0 – 5
30 46 80
µA
kΩ
R
L2
VIN = 0 V; VDD = 5 V ± 10 %
120 240 320
TA = 25 °C, RESET only
Supply current
(note)
I
DD1
V
= 5 V ± 10 %
DD
– 20 40 mA
20 MHz oscillation
V
= 2.7 V
DD
7 14
12 MHz oscillation
I
DD2
Idle mode; V
= 5 V ± 10 %
DD
8 16
20 MHz oscillation
Idle mode; VDD = 2.7 V
3 6
12 MHz oscillation
I
DD3
Stop mode; V
= 5 V ± 10%,
DD
110 220
µA
LVD enable
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
20-6
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