Page 1
S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW
1PRODUCT OVERVIEW
The S3C7524/C7528/C7534/C7538 single-chip CMOS microcontroller has been designed for high-performance
using SAM 47 (Samsung Arrangeable Microcontrollers). SAM 47, Samsung's newest 4-bit CPU core is notable
for its low energy consumption and low operating voltage.
You can select from two ROM sizes: 4K or 8K bytes
Except for the difference in ROM size, the features and functions of the S3C7524 and the S3C7528, the
S3C7534 and the S3C7538 are identical.
With it's DTMF generator, watchdog timer function, and versatile 8-bit timer/counters, theS3C7524/C7528
/C5304/C5308 offers an excellent design solution for a wide variety of telecommunication applications.
Up to 35 pins of the available 42-pin SDIP or 44-pin QFP package for the S3C7524/C7528, and up to 23 pins of
the available 30-pin SDIP or 32-pin SOP package for the S3C7534/C7538 can be assign to I/O. Six vectored
interrupts for S3C7524/C7528 and four vectored interrupts for S3C7534/C7538 provide fast response to internal
and external events. In addition, the S3C7524/C7528/C7534/C7538 's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The S3C7524/C7528 microcontroller is also available in OTP (One Time Programmable) version, S3P7528. The
S3C7534/C7538 microcontroller is also available in OTP (One Time Programmable) version, S3P7538. The
S3P7528/P7538 microcontroller has an on-chip 8K-byte one-time-programable EPROM instead of masked ROM.
The S3P7528 is comparable to S3C7524/C7528, both in function and in pin configuration. Also, the S3P7538 is
comparable to the S3C7534/C7538, both in function and in pin configuration.
1-1
Page 2
PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538
FEATURES SUMMARY
Memory
• 768 × 4-bit RAM
• 4,096 × 8-bit ROM (S3C7524/C7534)
8,192 × 8-bit ROM (S3C7528/C7538)
35 I/O Pins
• Input only: 4 pins (S3C7524/C7528)
1 pins (S3C7534/C7538)
• I/O: 23 pins (S3C7524/C7528)
14 pins (S3C7534/C7538)
• N-channel open-drain I/O: 8 pins
Memory-Mapped I/O Structure
• Data memory bank 15
DTMF Generator
• 16 dual-tone frequencies for tone dialing
8-Bit Basic Timer
• Programmable interval timer
• Watchdog timer
Interrupts
• 3 external interrupt vectors (S3C7524/C7528)
1 external interrupt vectors (S3C7534/C7538)
• 3 internal interrupt vectors
• 2 quasi-interrupts
Power-Down Modes
• Idle: Only CPU clock stops
• Stop: System clock stops
Oscillation Sources
• Crystal, or ceramic for main system clock
• Main system clock frequency: 0.4–6.0 MHz
(typical)
• CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
• 0.95, 1.91, and 15.3 µs at 4.19 MHz
• 1.12, 2.23, 17.88 µs at 3.58 MHz
• 0.67, 1.33, 10.7 µs at 6.0 MHz
Two 8-Bit Timer/Counters
• Programmable 8-bit timer
• External event counter function
• Arbitrary clock frequency output
Watch Timer
• Real-time and interval time measurement
• Four frequency outputs to the BUZ pin
Bit Sequential Carrier
• Supports 8-bit serial data transfer in arbitrary
format
Operating Temperature
• – 40 °C to 85 °C
Operating Voltage Range
• 2.0 V to 5.5 V
Package Types
• 42 SDIP, 44 QFP (S3C7524/C7528)
• 30 SDIP, 32 SOP (S3C7534/C7538)
1-2
Page 3
S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW
BLOCK DIAGRAM
P6.0–P6.3 /
KS0–KS3
P7.0–P7.3 /
KS4–KS7
P8.0–P8.3
P9.0–P9.2
INT0, INT1, INT2, INT4
8-BIT
TIMER/
COUNTER 0
8-BIT
TIMER/
COUNTER 1
I/O PORT 6
I/O PORT 7
I/O PORT 8
I/O PORT 9
RESET
Xin Xout
INTERRUPT
CONTROL
BLOCK
INTERNAL
INTERRUPTS
INSTRUCTION DECODER
ARITHMETIC
AND
LOGIC UNIT
768 x 4-BIT
DATA
MEMORY
PROGRAM MEMORY
S3C7524/C7534: 4 KBytes
S3C7528/C7538: 8 KBytes
CLOCK
STACK
POINTER
PROGRAM
COUNTER
PROGRAM
STATUS WORD
FLAGS
BASIC
TIMER
WATCH
TIMER
WATCH-DOG
TIMER
INPUT
PORT 1
I/O PORT 2
I/O PORT 3
I/O PORT 4
I/O PORT 5
DTMF
GENERATOR
P1.0 / INT0
P1.1 / INT1
P1.2 / INT2
P1.3 / INT4
P2.0 / TCLO0
P2.1 / TCLO1
P2.2 / CLO
P2.3 / BUZ
P3.0 / TCL0
P3.1 / TCL1
P3.2
P3.3
P4.0 / BTCO
P4.1−P4.3
P5.0–P5.3
DTMF
NOTE:
S3C7534/C7538 does not use P1.1/INT1, P1.2/INT2, P1.3/INT3, P3.2, P3.3, INT1, INT2,
INT4, P8.0-P8.3, and P9.0-P9.2.
Figure 1–1. S3C7524/C7528 Simplified Block Diagram
1-3
Page 4
PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538
PIN ASSIGNMENTS
P1.0 / INT0
P1.1 / INT1
P1.2 / INT2
P1.3 / INT4
P2.0 / TCLO0
P2.1 / TCLO1
P2.2 / CLO
P2.3 / BUZ
P3.0 / TCL0
P3.1 / TCL1
VDD
VSS
X
OUT
XIN
TEST
P4.0 / BTCO
P4.1
RESET
P3.2
P3.3
P4.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
S3C7524/C7528
(42-SDIP-600)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P9.2
P9.1
P9.0
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
P6.1 / KS1
P6.0 / KS0
P5.3
P5.2
P5.1
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
1-4
Figure 1–2. S3C7524/C7528 Pin Assignment Diagrams (42–SDIP)
Page 5
S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW
P2.1 / TCLO1
P2.0 / TCLO0
P1.3 / INT4
P1.2 / INT2
P1.1 / INT1
P1.0 / INT0
NC
P9.2
P9.1
P9.0
DTMF
44
43
42
41
40
39
38
37
36
35
34
P2.2 / CLO
P2.3 / BUZ
P3.0 / TCL0
P3.1 / TCL1
VDD
VSS
X
OUT
XIN
TEST
P4.0 / BTCO
P4.1
1
2
3
4
5
KS57C5204/C5208
6
7
(44-QFP-1010B)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
33
32
31
30
29
28
27
26
25
24
23
22
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
P6.1 / KS1
P6.0 / KS0
P5.3
P5.2
P5.1
RESET
P3.2
P3.3
NC
P4.2
P4.3
P8.0
P8.1
P8.2
P8.3
P5.0
Figure 1–3. S3C7524/C7528 Pin Assignment Diagrams (44–QFP)
1-5
Page 6
PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538
VSS
X
OUT
XIN
TEST
P4.0 / BTCO
P4.1
RESET
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
P6.0 / KS0
P6.1 / KS1
1
2
3
4
S3C7534/C7538
(30-SDIP-400)
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD
P3.1 / TCL1
P3.0 / TCL0
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
Figure 1–4. S3C7534/C7538 Pin Assignment Diagrams (30–SDIP)
VSS
X
OUT
XIN
TEST
P4.0 / BTCO
P4.1
RESET
P4.2
NC
P4.3
P5.0
P5.1
P5.2
P5.3
P6.0 / KS0
P6.1 / KS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
S3C7534/C7538
(32-SOP-405A)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
P3.1 / TCL1
P3.0 / TCL0
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
NC
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
Figure 1–5. S3C7534/C7538 Pin Assignment Diagrams (32–SOP)
1-6
Page 7
S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7524/C7528 Pin Descriptions
Pin
Name
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
P4.0
P4.1
P4.2
P4.3
P5.0–P5.3
P6.0–P6.3
P7.0–P7.3
P8.0–P8.3
P9.0–P9.2
Pin
Reset
Type
Value
I I 4-bit input port.
1-bit and 4-bit read and test is possible.
Each pull-up resistors are assignable by software.
I/O I 4-bit I/O port.
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 2 and 3 can be paired to enable 8-bit data
transfer.
I/O I 4-bit I/O ports.
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
N-channel open-drain or push-pull output can be
selected by software (1-bit unit)
Ports 4 and 5 can be paired to support 8-bit data
transfer.
I/O I 4-bit I/O ports.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 6 and 7 can be paired to enable 8-bit data
transfer.
I/O I 4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 8 and 9 can be paired to enable 8-bit data
transfer.
Description Pin
Number
1 (39)
2 (40)
3 (41)
4 (42)
5 (43)
6 (44)
7 (1)
8 (2)
9 (3)
10 (4)
19 (13)
20 (14)
16 (10)
17 (11)
21 (15)
22 (17)
27–30
(22–25)
31–34
(26–29)
35–38
(30–33)
23–26
(18–21)
40–42
(35–37)
Share
Circuit
Pin
INT0
INT1
INT2
INT4
TCLO0
TCLO1
CLO
BUZ
TCL0
TCL1
BTCO E-2
KS0–KS3
KS4–KS7
– D-2
Type
A-4
D-2
D-4
D-4
1-7
Page 8
PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538
Table 1-1. S3C7524/C7528 Pin Descriptions (Continued)
Pin
Name
Pin
Type
Reset
Value
Description Pin
Number
Share
Pin
Circuit
Type
DTMF O – DTMF output. 39 (34) – G-6
BTCO I/O I Basic timer clock output 16 (10) P4.0 E-2
INT0
INT1
I I External interrupts. The triggering edge for INT0 and
INT1 is selectable.
1 (39)
2 (40)
P1.0
P1.1
A-3
INT2 I I Quasi-interrupt with detection of rising edges 3 (41) P1.2 A-3
INT4 I I External interrupt with detection of rising and falling
4 (42) P1.3 A-3
edges.
TCLO0 I/O I Timer/counter 0 clock output 5 (43) P2.0 D-2
TCLO1 I/O I Timer/counter 1 clock output 6 (44) P2.1 D-2
CLO I/O I Clock output 7 (1) P2.2 D-2
BUZ I/O I 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at
8 (2) P2.3 D-2
the watch timer clock frequency of 4.19 MHz for
buzzer sound
TCL0 I/O I External clock input for timer/counter 0 9 (3) P3.0 D-4
TCL1 I/O I External clock input for timer/counter 1 10 (4) P3.1 D-4
KS0–KS3
KS4–KS7
V
DD
V
SS
RESET
X
in
X
out
I/O I Quasi-interrupt inputs with falling edge detection 31–34
(26–29)
35–38
(30–33)
P6.0–
P6.3
P7.0–
P7.3
– – Power supply 11 (5) – –
– – Ground 12 (6) – –
– –
RESET signal
– – Crystal, or ceramic oscillator signal for main system
clock. (For external clock input, use Xin and input
Xin's reverse phase to X
out
)
18 (12) – B
14 (8)
– –
13 (7)
D-4
TEST – – Test signal input 15 (9) – –
NC – – No connection (16, 38) – –
NOTE: Parentheses indicate pin number for 44 QFP package.
1-8
Page 9
S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW
Table 1-2. S3C7534/C7538 Pin Descriptions
Pin
Name
Pin
Type
P1.0 I 1-bit input port.
1-bit and 4-bit read and test is possible.
Each bit pull-up resistors are assignable.
P2.0
P2.1
P2.2
P2.3
I/O 4-bit I/O port.
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software
assignable to input pins and are automatically
disabled for output pins.
P3.0
P3.1
P4.0
P4.1
P4.2
P4.3
P5.0–P5.3
Ports 2 and 3 can be paired to enable 8-bit data
transfer.
I/O 4-bit I/O ports.
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software
assignable to input pins and are automatically
disabled for output pins.
The N-channel open-drain or push-pull output
can be selected by software (1-bit unit).
Ports 4 and 5 can be paired to enable 8-bit data
transfer.
P6.0–P6.3
I/O 4-bit I/O ports.
1-bit and 4-bit read/write and test is possible.
P7.0–P7.3
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software
assignable to input pins and are automatically
disabled for output pins.
Ports 6 and 7 can be paired to enable 8-bit data
transfer.
Description Pin
Number
23 (25) INT0 A-4
24 (26)
25 (27)
26 (28)
27 (29)
28 (30)
29 (31)
5 (5)
6 (6)
8 (8)
9 (10)
10–13
(11–14)
14–17
(15–18)
18–21
(19–22)
Share
Circuit
Pin
TCLO0
TCLO1
CLO
BUZ
TCL0
TCL1
BTCO E-2
KS0–KS3
KS4–KS7
Type
D-2
D-4
D-4
1-9
Page 10
PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538
Table 1-1. S3C7534/C7538 Pin Descriptions (Continued)
Pin
Name
I/O
Type
Description Pin
Number
Share
Pin
Circuit
Type
DTMF O DTMF output. 22 (23) – G-6
INT0 I External interrupt input.
23 (25) P1.0 A-3
The triggering edge for INT0 is selectable.
TCLO0 I/O Timer/counter 0 clock output 24 (26) P2.0 D-2
TCLO1 I/O Timer/counter 1 clock output 25 (27) P2.1 D-2
CLO I/O Clock output 26 (28) P2.2 D-2
BUZ I/O 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the
27 (29) P2.3 D-2
watch timer clock frequency of 4.19 MHz for buzzer
sound
TCL0 I/O External clock input for timer/counter 0 28 (30) P3.0 D-4
TCL1 I/O External clock input for timer/counter 1 29 (31) P3.1 D-4
BTCO I/O Basic timer clock output 5 (5) P4.0 E-2
V
DD
V
SS
X
in
X
out
– Power supply 30 (32) – –
– Ground 1 (1) – –
– Crystal, or ceramic oscillator signal for main system
clock. (For external clock input, use Xin and input Xin's
reverse phase to X
out
)
3 (3)
2 (2)
– –
NC – No connection (9, 24) – –
TEST – Test signal input 4 (4) – –
RESET
KS0–KS3
KS4–KS7
–
RESET signal
I/O Quasi-interrupt inputs with falling edge detection 14–17
7 (7) – B
P6.0–
(15–18)
18–21
(19–22)
P6.3
P7.0–
P7.3
D-4
NOTE: Parentheses indicate the pin number for 32-SOP package.
1-10
Page 11
S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
V
V
DD
P-CHANNEL
DD
PULL-UP
RESISTOR
IN
N-CHANNEL
Figure 1–6. Pin Circuit Type A
V
DD
PULL-UP
RESISTOR
IN
SCHMITT TRIGGER
P-CHANNEL
IN
SCHMITT TRIGGER
Figure 1–8. Pin Circuit Type A-4
DATA
OUTPUT
DISABLE
RESISTOR
ENABLE
V
DD
P-CHANNEL
N-CHANNEL
OUT
Figure 1–7. Pin Circuit Type B
Figure 1–9. Pin Circuit Type C
1-11
Page 12
PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308 MICROCONTROLLER
P-CHANNEL
DTMF OUT
V
DD
RESISTOR
ENABLE
DATA
OUTPUT
CIRCUIT
TYPE C
DISABLE
Figure 1–10. Pin Circuit Type D-2
V
DD
PULL-UP
RESISTOR
P-CHANNEL
I/O
PNE
DATA
OUTPUT
DISABLE
V
DD
PULL-UP
DD
RESISTOR
PULL-UP
RESISTOR
ENABLE
I/O
V
P-CHANNEL
N-CHANNEL
Figure 1–12. Pin Circuit Type E-2
RESISTOR
ENABLE
DATA
OUTPUT
CIRCUIT
TYPE C
DISABLE
SCHMITT TRIGER
Figure 1–11. Pin Circuit Type D-4
PULL-UP
RESISTOR
I/O
OUTPUT
DISABLE
Figure 1–13. Pin Circuit Type G-6
1-12
Page 13
S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA
13 ELECTRICAL DATA
In this section, information on S3C7524/C7528 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— System clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at X
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
in
and X
out
13–1
Page 14
ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538
Table 13-1. Absolute Maximum Ratings
(T
= 25 °C)
A
Parameter Symbol Conditions Rating Units
Supply Voltage
Input Voltage
Output Voltage
Output Current High
V
DD
I
V
V
I1
O
OH
All I/O ports
One I/O port active – 15 mA
– – 0.3 to + 6.5 V
– 0.3 to V
–
– 0.3 to VDD + 0.3
DD
+ 0.3
V
V
All I/O ports active – 35
Output Current Low
I
OL
One I/O port active + 30 (Peak value) mA
(note)
+ 15
All I/O ports active + 100 (Peak value)
(note)
+ 60
Operating Temperature
Storage Temperature
T
A
T
stg
– – 40 to + 85
– – 65 to + 150
°
C
°
C
NOTE: The values for output current low ( IOL ) are calculated as peak value × Duty .
Table 13-2. D.C. Electrical Characteristics
(T
= – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Units
Input high
voltage
Input low
voltage
V
IH1
V
IH2
V
IH3
V
IL1
V
IL2
V
IL3
All input pins except those
specified below for V
IH2
– V
Ports 1, 3, 6, 7, and RESET
Xin and X
out
All input pins except those
specified below for V
IL2–VIL3
Ports 1, 3, 6, 7, and RESET
Xin and X
out
IH3
0.7 V
DD
0.8 V
DD
V
– 0.1
DD
– –
–
V
DD
V
DD
V
DD
0.3 V
0.2 V
DD
DD
0.1
V
V
13–2
Page 15
S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA
DD
L2
I
DD
Table 13-2. D.C. Electrical Characteristics (Continued)
(T
= – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Units
Output high
voltage
Output low
voltage
V
V
OH
OL1
IOH = – 1 mA
Ports except 1
V
= 4.5 V to 5.5 V
DD
IOL = 15 mA, Ports 4 and 5 only
V
DD
– 1.0
– – V
– 0.4 2 V
Input high
leakage current
Input low
leakage current
Output high
leakage current
Output low
leakage current
Pull-up resistor
V
I
LIH1
I
LIH2
I
I
I
LOH
I
R
R
OL2
LIL1
LIL2
LOL
L1
VDD = 2.0 to 5.5 V, IOL = 1.6mA
VDD = 4.5 V to 5.5 V
IOL= 4 mA, all out ports except 4,5
VDD = 2.0 to 5.5 V, IOL = 1.6mA
VI = V
DD
All input pins except those specified
below
VI = V
DD
Xin and X
V
= 0
I
out
V
All input pins except below and RESET
V
= 0 V
I
X
i
V
O
and X
n
= V
DD
out
only
All out pins
V
= 0 V
O
Xin and X
V
= 5 V; V
DD
out
only
= 0 V
I
except RESET
V
= 3 V
V = 5 V; V
V
= 3 V
= 0 V; RESET
– – 0.4
– – 2 V
– – 0.4
– – 3 µA
20
– – – 3 µA
– 20
– – 3 µA
– – – 3 µA
25 47 100
50 95 200
100 220 400
200 450 800
kΩ
13–3
Page 16
ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538
DD
DD
Table 13-2. D.C. Electrical Characteristics (Concluded)
(T
= – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Units
Supply
current
(1)
I
DD1
(DTMF on)
Run mode; V
= 5 V ± 10%
DD
3.58 MHz crystal oscillator,
(2)
– 2.9 5.0 mA
C1 = C2 = 22 pF
V
= 3 V ± 10%
I
DD2
(DTMF off) crystal oscillator, C1 = C2 = 22 pF 3.58 MHz 1.8 4.0
Run mode; V
V
= 3 V ± 10%
= 5 V ± 10%
DD
6.0 MHz – 2.6 8.0 mA
6.0 MHz 1.8 4.0
1.6 3.0
3.58 MHz 1.2 2.3
IDD3
Idle mode; = VDD = 5 V ± 10%
6.0 MHz – 0.7 2.5 mA
crystal oscillator, C1 = C2 = 22 pF 3.58 MHz 0.6 1.8
VDD = 3 V ± 10%
6.0 MHz 0.3 1.5
3.58 MHz 0.2 1.0
I
DD4
Stop mode; VDD = 5 V ± 10%
Stop mode; VDD = 3 V ± 10%
– 0.01 3 µA
0.01 2
Row tone level
V
ROW
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2 V
RL = 5kΩ
Ratio of column
to row tone
dB
CR
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2 V
RL = 5kΩ
Distortion
(Dual tone)
THD
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2 V
RL = 5kΩ, 1MHz band
NOTES
1. D.C. electrical values for Supply Current (I
2. For D.C. electrical values, the power control register (PCON) must be set to 0011B.
DD1
to I
) do not include current drawn through internal pull-up registers.
DD3
– 16.0 – 14.0 – 11.0 dBV
1 2 3
– – 5 %
13–4
Page 17
S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA
Table 13-3. Main System Clock Oscillator Characteristics
(T
= – 40 °C + 85 °C, VDD = 2.0 V to 5.5 V)
A
Oscillator Clock
Configuration
Ceramic
Xin Xout
Oscillator
C1 C2
Crystal
Xin Xout
Oscillator
C1 C2
External
Xin Xout
Clock
Parameter Test Condition Min Typ Max Units
Oscillation frequency
Stabilization time
(2)
Oscillation frequency
Stabilization time
(2)
Xin input frequency
(1)
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 3 V
(1)
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 3 V
(1)
VDD = 2.7 V to 5.5 V
0.4 – 6.0 MHz
0.4 – 4.2
– – 4 ms
0.4 – 6.0 MHz
0.4 – 4.2
– – 10 ms
0.4 – 6.0 MHz
Xin input high and low
VDD = 2.0 V to 5.5V
– 83.3 – 1250 ns
0.4 – 4.2
level width (tXH, tXL)
NOTES
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
13–5
Page 18
ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538
SS
Table 13-4. Input/Output Capacitance
(TA = 25 °C, V
= 0 V )
DD
Parameter Symbol Condition Min Typ Max Units
C
C
OUT
IN
f = 1 MHz; Unmeasured pins
– – 15 pF
are returned to V
– – 15 pF
Input
Capacitance
Output
Capacitance
I/O Capacitance
C
IO
– – 15 pF
Table 13-5. A.C. Electrical Characteristics
(T
= – 40 °C to + 85 °C, V
A
= 2.0 V to 5.5 V)
DD
Parameter Symbol Conditions Min Typ Max Units
Instruction Cycle
(1)
Time
TCL0, TCL1 Input
t
f
CY
TI0
f
,
TI1
V
= 2.7 V to 5.5 V
DD
VDD = 2.0 V to 5.5 V
VDD = 2.7 V to 5.5 V
0.67 – 64 µs
0.95
0 – 1.5 MHz
Frequency
TCL0, TCL1 Input
High, Low Width
t
TIH0
t
TIH1
, t
, t
TIL0
TIL1
VDD = 2.0 V to 5.5V
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
0.48 – – µs
1.8
1 MHz
Interrupt Input
High, Low Width
RESET Input Low
Width
t
INTH
t
RSL
, t
INTL
INT0, INT1, INT2, INT4,
10 – – µs
KS0–KS7
Input 10 – – µs
13–6
Page 19
S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA
CPU CLOCK
1.5 MHz
1.05 MHz
15.625 kHz
Main Osc. Freq.
6 MHz
4.2 MHz
1 2 3 4 5 6 7
2.7 V
SUPPLY VOLTAGE (V)
CPU CLOCK = oscillator frequency x 1/n (n = 4, 8, 64)
Figure 13-1. Standard Operating Voltage Range
Table 13-6. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter Symbol Conditions Min Typ Max Unit
Data retention supply voltage
Data retention supply current
Release signal set time
Oscillator stabilization wait
(1)
time
NOTES
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
V
DDDR
I
DDDR
t
SREL
t
WAIT
– 1.5 – 5.5 V
V
DDDR
= 1.5 V
– 0 – – µs
Released by RESET
Released by interrupt
– 0.1 10 µA
–
217/fx
(2)
– ms
ms
13–7
Page 20
ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
V
DD
RESET
V
DD
IDLE MODE
EXECUTION OF
STOP INSTRUCTION
STOP MODE
DATA RETENTION MODE
V
DDDR
t
SREL
Figure 13-2. Stop Mode Release Timing When Initiated By RESETRESET
IDLE MODE
STOP MODE
DATA RETENTION MODE
t
WAIT
OPERATING
MODE
NORMAL
OPERATING
MODE
13–8
V
EXECUTION OF
DDDR
STOP INSTRUCTION
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
t
SREL
t
WAIT
Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request
Page 21
S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA
Timing Waveforms (continued)
0.8 V
0.2 V
DD
DD
MEASUREMENT
POINTS
0.8 V
0.2 V
DD
DD
Figure 13-4. A.C. Timing Measurement Points (Except for Xin)
1 / f
x
t
XL
X
in
t
XH
V
DD
0.1 V
0.1 V
-
TCL
Figure 13-5. Clock Timing Measurement at X
1 / f
TI
t
TIL
t
TIH
Figure 13-6. TCL Timing
in
0.8 V
0.2 V
DD
DD
13–9
Page 22
ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538
t
RSL
RESET
0.2 V
DD
Figure 13-7. Input Timing for RESETRESET Signal
INT0, 1, 2, 4
K0 to K7
t
INTL
0.8 V
0.2 V
DD
DD
t
INTH
Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts
13–10
Page 23
S3C7524/C7528/P7528/C7534/C7538/P7538 MECHANICAL DATA
14 MECHANICAL DATA
This section contains the following information about the device package:
— Package dimensions in millimeters
— Pad diagram
— Pad/pin coordinate data table
(1.77)
#42 #22
42-SDIP-600
14.00 ± 0.20
39.50 MAX
39.10 ± 0.20
0.50 ± 0.10
1.00 ± 0.10
1.78
0-15
15.24
#21#1
3.50 ± 0.20
5.08 MAX
0.51 MIN
3.30 ± 0.30
+ 0.10
0.25
- 0.05
NOTE: Dimensions are in millimeters.
Figure 14-1. 42-SDIP-600 Package Dimensions
14–1
Page 24
MECHANICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538
13.20 ± 0.30
0-8
10.00 ± 0.20
0.15
+ 0.10
- 0.05
13.20 ± 0.30
44-QFP-1010B
10.00 ± 0.20
#44
#1
0.80
NOTE: Dimensions are in millimeters.
Figure 14-2. 44-QFP-1010B Package Dimensions
0.15 MAX
0.35
+ 0.10
- 0.05
0.10 MAX
0.80 ± 0.20
0.05 MIN
(1.00)
2.05 ± 0.10
2.30 MAX
14–2
Page 25
S3C7524/C7528/P7528/C7534/C7538/P7538 MECHANICAL DATA
(1.30)
8.94 ± 0.20
#30
#1
30-SDIP-400
27.88 MAX
27.48 ± 0.20
0.56 ± 0.10
1.12 ± 0.10
#16
#15
1.778
10.16
3.81 ± 0.20
0.51 MIN
5.21 MAX
3.30 ± 0.30
0-15
+ 0.10
0.25
- 0.05
NOTE: Dimensions are in millimeters.
Figure 14-3. 30-SDIP-400 Package Dimensions
14–3
Page 26
MECHANICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538
0-8
#32
#17
12.00 ± 0.30
(0.43)
32-SOP-450A
#1
20.30 MAX
19.90
± 0.20
0.40 ± 0.10
NOTE: Dimensions are in millimeters.
#16
1.27
8.34 ± 0.20
+ 0.10
0.25
- 0.05
2.00 ± 0.10
0.05 MIN
11.43
0.90 ± 0.20
2.20 MAX
0.10 MAX
14–4
Figure 14-4. 32-SOP-450A Package Dimensions
Page 27
S3C7524/C7528/P7528/C7534/C7538/P7538 S3P7528/P7538 OTP
15 S3P7528/P7538 OTP
OVERVIEW
The S3P7528/P7538 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C7524/C7528/C7534/C7538 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM
is accessed by a serial data format.
The S3P7528/P7538 is fully compatible with the S3C7528/C7538, both in function and in pin configuration.
Because of its simple programming requirements, the S3P7528/P7538 is ideal for use as an evaluation chip for
the S3C7528/C7538.
P1.0 / INT0
P1.1 / INT1
P1.2 / INT2
P1.3 / INT4
P2.0 / TCLO0
P2.1 / TCLO1
P2.2 / CLO
P2.3 / BUZ
SDAT / P3.0 / TCL0
SCLK / P3.1 / TCL1
V
DD / VDD
V
SS / VSS
X
OUT
XIN
V
TEST
PP /
P4.0 / BTCO
P4.1
RESETRESET / RESET
NOTE: The bold words indicate OTP pin names.
P3.2
P3.3
P4.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
(42-SDIP-600)
42
41
40
39
38
37
36
S3P7528
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P9.2
P9.1
P9.0
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
P6.1 / KS1
P6.0 / KS0
P5.3
P5.2
P5.1
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
Figure 15-1. S3P7528 Pin Assignments (42-SDIP)
15–1
Page 28
S3P7528/P7538 OTP S3C7524/C7528/P7528/C7534/C7538/P7538
/ V
V
V
P4.0 / BTCO
RESETRESET / RESET
P6.0 / KS0
P6.1 / KS1
SS
/ TEST
PP
X
OUT
P4.1
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
SS
X
NC
IN
Figure 15-2. S3P7528 Pin Assignments (44-QFP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
(32-SOP-405A)
KS57P5308
29
28
27
26
25
24
23
22
21
20
19
18
17
V
V
DD /
P3.1 / TCL1 /
P3.0 / TCL0 /
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
NC
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
DD
SCLK
SDAT
15–2
Page 29
S3C7524/C7528/P7528/C7534/C7538/P7538 S3P7528/P7538 OTP
/ V
V
V
PP
P4.0 / BTCO
RESET RESET / RESET
P6.0 / KS0
P6.1 / KS1
SS
/ TEST
X
OUT
P4.1
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
X
SS
IN
Figure 15-3. S3P7538 Pin Assignments (30-SDIP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
(30-SDIP-400)
S3C7538
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD /
V
P3.1 / TCL1 /
P3.0 / TCL0 /
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
DD
SCLK
SDAT
15–3
Page 30
S3P7528/P7538 OTP S3C7524/C7528/P7528/C7534/C7538/P7538
/ V
V
V
PP
P4.0 / BTCO
RESETRESET / RESET
P6.0 / KS0
P6.1 / KS1
SS
X
/ TEST
SS
OUT
X
IN
P4.1
P4.2
NC
P4.3
P5.0
P5.1
P5.2
P5.3
Figure 15-4. S3P7538 Pin Assignments (32-SOP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
(32-SOP-405A)
S3P7538
29
28
27
26
25
24
23
22
21
20
19
18
17
V
V
DD /
P3.1 / TCL1 /
P3.0 / TCL0 /
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
NC
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
DD
SCLK
SDAT
15–4
Page 31
S3C7524/C7528/P7528/C7534/C7538/P7538 S3P7528/P7538 OTP
Table 15-1. S3P7528 Pin Descriptions Used to Read/Write the EPROM
Main Chip During Programming
Pin Name Pin Name Pin No. I/O Function
P3.0 SDAT 9 (3) I/O Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P3.1 SCLK 10 (4) I/O Serial clock pin. Input only pin.
V
TEST
PP
(TEST)
15 (9) I Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
RESET RESET
V
/ V
DD
SS
NOTE: Parentheses indicate pin numbers of 44 QFP package.
VDD / V
SS
18 (12) I Chip initialization
11/12
(5/6)
I
Logic power supply pin. VDD should be tied to +5
V during programming.
Table 15-2. S3P7538 Pin Descriptions Used to Read/Write the EPROM
Main Chip During Programming
Pin Name Pin Name Pin No. I/O Function
P3.0 SDAT 28 (30) I/O Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P3.1 SCLK 29 (31) I/O Serial clock pin. Input only pin.
V
TEST
PP
(TEST)
4 (4) I Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
RESET RESET
V
/ V
DD
SS
NOTE: Parentheses indicate pin numbers of 32 SDIP package.
VDD / V
SS
7 (7) I Chip initialization
30/1
(32/1)
I
Logic power supply pin. VDD should be tied to +5
V during programming.
15–5
Page 32
S3P7528/P7538 OTP S3C7524/C7528/P7528/C7534/C7538/P7538
Table 15-3. Comparison of S3P7528 and S3C7528 Features
Characteristic S3P7528 S3C7528
Program Memory 8 K byte EPROM 8 K byte mask ROM
Operating Voltage (VDD)
2.0 V to 5.5 V 2.0 V to 5.5 V
OTP Programming Mode
VDD = 5 V, V
(TEST) = 12.5 V
PP
–
Pin Configuration 42 SDIP / 44 QFP 42 SDIP / 44 QFP
EPROM Programmability User Program 1 time Programmed at the factory
Table 15-4. Comparison of S3P7538 and S3C7538 Features
Characteristic S3P7538 S3C7538
Program Memory 8 K byte EPROM 8 K byte mask ROM
Operating Voltage (VDD)
OTP Programming Mode
2.0 V to 5.5 V 2.0 V to 5.5 V
VDD = 5 V, VPP (TEST) = 12.5 V
–
Pin Configuration 30 SOP / 32 SOP 30 SOP / 32 SOP
EPROM Programmability User Program 1 time Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P7528, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15-3 below.
Table 15-5. Operating Mode Selection Criteria
V
DD
Vpp
(TEST)
REG/
MEMMEM
Address
(A15-A0)
R/WW
5 V 5 V 0 0000H 1 EPROM read
12.5V 0 0000H 0 EPROM program
12.5V 0 0000H 1 EPROM verify
12.5V 1 0E3FH 0 EPROM read protection
NOTE: "0" means Low level; "1" means High level.
Mode
15–6
Page 33
S3C7524/C7528/P7528/C7534/C7538/P7538 S3P7528/P7538 OTP
START
Address= First Location
VDD=5V, VPP=12.5V
x = 0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
Device Failed
Verify Byte
FAIL
Verify 1 Byte
Last Address
V
= VPP= 5 V
DD
Compare All Byte
PASS
Device Passed
FAIL
NO
Increment Address
Figure 15-5. OTP Programming Algorithm
15–7
Page 34
S3P7528/P7538 OTP S3C7524/C7528/P7528/C7534/C7538/P7538
NOTES
15–8
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