Datasheet S3C7414, S3C7424, S3C7434, S3P7414, S3P7424 Datasheet (Samsung)

S3C7414/P7414/C7424/P7424/C7434/P7434 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

The S3C7414/C7424/C7434 single-chip CMOS microcontroller has been designed for very high performance
using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontroller).

With an A/D converter, LED direct drive pins, an 8-bit serial I/O interface, and an 8-bit timer/counter, the
S3C7414/C7424/C7434 offers you an excellent design solution for a wide variety of home appliance applications
— electric fans, cookers, boilers, and air conditioners, for example.

Up to 35 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts
provide fast response to internal and external events.

In addition, the S3C7414/C7424/C7434's advanced CMOS technology provides for low power consumption and a
wide operating voltage range.

OTP

The S3C7414/C7424/C7434 microcontroller is also available in OTP (One Time Programmable) version,
S3P7414/P7424/P7434. S3P7414/P7424/P7434 microcontroller has an on-chip 4-Kbyte one-time-programmable
EPROM instead of masked ROM. The S3P7414/P7424/P7434 is comparable to S3C7414/C7424/C7434, in
function, in D.C. electrical characteristics and in pin configuration.

DEVELOPMENT SUPPORT

The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based develop­ment environment for S3C7-series microcontrollers that is powerful, reliable, and portable. In addition to its
window-based program development structure, the SMDS toolset includes versatile debugging, trace, instruction
timing, and performance measurement applications.

The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and
accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard
hex files that also contain program control data for SMDS compatibility.

1-1

PRODUCT OVERVIEW S3C7414/P7414/C7424/P7424/C7434/P7434

FEATURES SUMMARY

Memory

• 256 × 4-bit RAM

• 4,096 × 8-bit ROM

35 I/O Pins

• I/O: 31 pins including 8 LED direct drive pins
(S3C7414/C7434)
18 pins including 8 LED direct drive pins
(S3C7424)

• Input only: 4 pins

A/D Converter

• 6-channel with 8-bit resolution

• 22.89 µs conversion speed at 4.19 MHz

Basic Timer

• One 8-bit basic timer

• Watchdog timer functions

• Four interval clock selection

Timer/Counters

• Two 8-bit timer/counter (TC0, TC1)

• Programmable 8-bit timer

• External event counter

• Arbitrary clock frequency output

• PWM output mode (TC1)

Watch Timer

• One watch timer 8-bit

• Time interval generation: 0.5 s, 3.9 ms at

4.19 MHz

• Four frequency outputs to BUZ pin

Built-in reset circuit (S3C7434 only)

• Built-in power-on reset circuit

Interrupts

• Five internal vectored interrupts
(INTB, INTT0, INTT1, INTS, INTAD)

• Three external vectored interrupts
(INT0, INT1, INT4)

• Two quasi-interrupts (INT2, INTW)

Bit Sequential Carrier

• Supports 16-bit serial data transfer in
arbitrary format

Memory-Mapped I/O Structure

• Data memory bank 15

Two Power-Down Modes

• Idle mode (only CPU clock stops)

• Stop mode (system oscillation stops)

Oscillation Sources

• Crystal, Ceramic, or RC for system clock

• Crystal, Ceramic: 0.4–6.0 MHz

• RC: 4 MHz (typ)

• CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

• 0.95, 1.91, 15.3 µs at 4.19 MHz

• 0.67, 1.33, 10.7 µs at 6.0 MHz

Operating Temperature

• – 40 °C to 85 °C

8-bit Serial I/O Interface

• 8-bit transmit/receive mode

• 8-bit receive mode

• LSB-first or MSB-first transmission selectable

• Internal or external clock source

1-2

Operating Voltage Range

• 1.8 V to 5.5 V (S3C7414/C7424)

• 2.5 V to 5.5 V (S3C7434)

Package Type

• 42-pin SDIP, 44-pin QFP (S3C7414/C7434)
30-pin SDIP, 28-pin SOP (S3C7424)

S3C7414/P7414/C7424/P7424/C7434/P7434 PRODUCT OVERVIEW

Table 1-1. Comparision Table

Feature S3C7414 S3C7424 S3C7434

Core SAM47 SAM47 SAM47
ROM 4 K bytes Same Same
RAM 256 nibbles Same Same
I/O 35 (4 input only) 21 (3 input only) 35 (4 input only)
POR

(1)

None None Built in/ Typ: 2.0 V
SIO 8-bit SIO x 1 Same Same
Timer0 8-bit timer/counter Same Same
Timer1(PWM) 8-bit timer/counter

Same Same

(8-bit PWM x 1)
Watchdog timer Watch-dog

Same Same

4 selectable interval
ADC 8-bit x 6 8-bit x 4 8-bit x 6
AV

SS

Interrupt External x 3

(2)

None

Internal x 5

Quasi x 2 (KS0–KS3)

Same Same
External x 2

Internal x 5
Quasi x 1 ( – )

External x 3
Internal x 5

Quasi x 2 (KS0–KS3)
Power down Stop/Idle Same Same
Oscillator Crystal, Ceramic, RC Same Same
Operating frequency 0.4–6 MHz Same Same
Operating voltage 1.8–5.5 V 1.8–5.5 V 2.5–5.5 V
OTP/MTP OTP Same Same
Package 42SDIP/44QFP 30SDIP/28SOP 42SDIP/44QFP

NOTES

1. POR (power on reset)/Typ 2.0 V low voltage detector.

2. Internal A/D converter ground (bonded to VSS internally)

1-3

PRODUCT OVERVIEW S3C7414/P7414/C7424/P7424/C7434/P7434

BLOCK DIAGRAM

INT0, INT1, INT2,INT4

COUNTER 0

COUNTER 1

P4.0-4.3

P5.0-5.3

P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3

P7.0-7.3 I/O PORT 7

P8.0/TCL0

P8.1/TCLO0

P8.2

I/O PORT 4

I/O PORT 5

I/O PORT 6

I/O PORT 8 I/O PORT 3

8-BIT

TIMER/

8-BIT

TIMER/

RESET

INTERRUPT

CONTROL

BLOCK

INTERNAL

INTERRUPTS

INSTRUCTION DECODER

ARITHMETIC

LOGIC UNIT

256 x 4-BIT

DATA

MEMORY

X

AND

INXOUT

CLOCK

BASIC

TIMER

INSTRUCTION

REGISTER

PROGRAM
COUNTER

PROGRAM

STATUS WORD

STACK

POINTER

4 K BYTE

PROGRAM

MEMORY

WATCH

TIMER

I/O PORT 2

I/O PORT 0

SERIAL

I/O

INPUT

PORT 1

I/O PORT 2

A/D

CONVERTER

P0.0/

SCK

P0.1/SO
P0.2/SI
P0.3/BUZ

P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4

P2.0-P2.3/
AD0-AD3

AV

REF

P3.0/AD4
P3.1/AD5
P3.2/CLO/TCL1
P3.3/PWM / TCLO1

1-4

Figure 1-1. S3C7414/C7424/C7434Simplified Block Diagram

S3C7414/P7414/C7424/P7424/C7434/P7434 PRODUCT OVERVIEW

PIN ASSIGNMENTS

P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P3.0/AD4
P3.1/AD5

AVREF

P3.2/CLO/TCL1

P3.3/PWM/TCLO1

P4.0

VDD

VSS

XOUT

XIN

TEST

P4.1
P4.2

RESET

P4.3
P5.0
P5.1

Figure 1-2. S3C7414 Pin Assignment (42-SDIP)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

S3C7414

(42-SDIP)

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

P8.2
P8.1/TCLO0
P8.0/TCL0
P7.3
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P0.1/SO
P0.0/SCK
P5.3
P5.2

1-5

PRODUCT OVERVIEW S3C7414/P7414/C7424/P7424/C7434/P7434

NC

P3.1/AD5

P3.0/AD4

P2.3/AD3

P2.2/AD2

P2.1/AD1

P2.0/AD0

P8.2

P8.1/TCLO0

P8.0/TCL0

P7.3

AVREF

P3.2/CLO/TCL1

P3.3/PWM/TCLO1

P4.0

VDD
VSS

XOUT

XIN

TEST

P4.1
P4.2

Figure 1-3. S3C7414 Pin Assignment (44-QFP)

4443424140393837363534

1
2
3
4
5
6
7
8
9
10
11

S3C7414

(44-QFP)

1213141516171819202122

P4.3

P5.0

P5.1

P5.2

P5.3

RESET

P0.0/SCK

P0.2/SI

P0.1/SO

P0.3/BUZ

NC

33
32
31
30
29
28
27
26
25
24
23

P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0

1-6

S3C7414/P7414/C7424/P7424/C7434/P7434 PRODUCT OVERVIEW

VSS

XOUT

XIN

TEST

P4.1
P4.2

RESET

NC
P4.3
P5.0
P5.1
P5.2
P5.3

P0.0/SCK

P0.1/SO

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

S3C7424

(30-SDIP)

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

VDD
P4.0
P3.3/PWM/TCLO1
P3.2/CLO/TCL1
AVREF
NC
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI

Figure 1-4. S3C7424 Pin Assignment (30-SDIP)

VSS

XOUT

XIN

TEST

P4.1
P4.2

RESET

P4.3
P5.0
P5.1
P5.2
P5.3

P0.0/SCK

P0.1/SO

1
2
3
4
5
6
7
8
9
10
11
12
13
14

S3C7424

(28-SOP)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

VDD
P4.0
P3.3/PWM/TCLO1
P3.2/CLO/TCL1
AVREF
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI

Figure 1-5. S3C7424 Pin Assignment (28-SOP)

1-7

PRODUCT OVERVIEW S3C7414/P7414/C7424/P7424/C7434/P7434

P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P3.0/AD4
P3.1/AD5

AVREF

P3.2/CLO/TCL1

P3.3/PWM/TCLO1

P4.0

VDD

VSS

XOUT

XIN

TEST

P4.1
P4.2

RESET

P4.3
P5.0
P5.1

Figure 1-6. S3C7434 Pin Assignment (42-SDIP)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

S3C7434

(42-SDIP)

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

P8.2
P8.1/TCLO0
P8.0/TCL0
P7.3
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P0.1/SO
P0.0/SCK
P5.3
P5.2

1-8

S3C7414/P7414/C7424/P7424/C7434/P7434 PRODUCT OVERVIEW

NC

P3.1/AD5

P3.0/AD4

P2.3/AD3

P2.2/AD2

P2.1/AD1

P2.0/AD0

P8.2

P8.1/TCLO0

P8.0/TCL0

P7.3

AVREF

P3.2/CLO/TCL1

P3.3/PWM/TCLO1

P4.0

VDD

VSS

XOUT

XIN

TEST

P4.1
P4.2

Figure 1-7. S3C7434 Pin Assignment (44-QFP)

4443424140393837363534

1
2
3
4
5
6
7
8
9
10
11

S3C7434

(44-QFP)

1213141516171819202122

P4.3

P5.0

P5.1

P5.2

P5.3

RESET

P0.0/SCK

P0.2/SI

P0.1/SO

P0.3/BUZ

NC

33
32
31
30
29
28
27
26
25
24
23

P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0

1-9

PRODUCT OVERVIEW S3C7414/P7414/C7424/P7424/C7434/P7434

PIN DESCRIPTIONS

Table 1-2. S3C7414/C7434 Pin Descriptions

Pin Name Pin Type Description Number Share Pin

P0.0
P0.1
P0.2
P0.3

P1.0
P1.1
P1.2
P1.3

P2.0
P2.1
P2.2
P2.3

P3.0
P3.1
P3.2
P3.3

P4.0
P4.1
P4.2
P4.3
P5.0–P5.3

P6.0–P6.3
P7.0–P7.3
P8.0

P8.1
P8.2

I/O 4-bit I/O port.

1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.

24 (18)
25 (19)
26 (20)

27 (21)
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.

I 4-bit input port.

1-bit and 4-bit read and test is possible.
3-bit pull-up resistors are individually assignable by
software to pins P1.0, P1.1, and P1.2.

I/O 4-bit I/O port.

N-channel open-drain output.
1-bit or 4-bit write and test is possible.
Individual pins are software configurable as AD input

28 (23)

29 (24)

30 (25)

31 (26)

1 (38)
2 (39)
3 (40)

4 (41)
or output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.

I/O Same as Port 0 (P0.0–P0.3) 5 (42)

6 (43)

8 (2)
9 (3)

I/O 4-bit I/O ports.

Ports 4 and 5 can be configured individually as n­channel open-drain or as CMOS push-pull output by
software.
1-bit and 4-bit read/write and test is possible.
Ports 4 and 5 can be paired to enable 8-bit data

10 (4)

16 (10)
17 (11)
19 (13)

20–23

(14–17)
transfer.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.

I/O Same as Port 0 except port 8 is a 3-bit I/O port 32–35

(27–30)

36–39

(31–34)

40 (35)
41 (36)
42 (37)

SCK

SO

SI

BUZ

INT0
INT1
INT2
INT4

AD0
AD1
AD2
AD3

AD4
AD5

CLO/TCL1

PWM/TCLO1

–

KS0–KS3

–

TCL0

TCLO0

–

1-10

S3C7414/P7414/C7424/P7424/C7434/P7434 PRODUCT OVERVIEW

Table 1-2. S3C7414/C7434 Pin Descriptions (Continued)

Pin Name Pin Type Description Number Share Pin

SCK

I/O Serial I/O interface clock signal 24 (18) P0.0

SO I/O Serial data output 25 (19) P0.1
SI I/O Serial data input 26 (20) P0.2
BUZ I/O 2 kHz, 4kHz, 8kHz, or 16 kHz frequency output at the

27 (21) P0.3

watch timer clock frequency of 32.768 kHz

INT0, INT1 I External interrupts. The triggering edge for INT0 and

INT1 is selectable. Only INT0 is synchronized with the

28–29

(23–24)

P1.0, P1.1

system clock.
INT2 I Quasi-interrupt input with rising edge detection 30 (25) P1.2
INT4 I External interrupts with detection of rising and falling

31 (26) P1.3

edges
AD0–AD3

I/O A/D converter analog inputs 1–4

P2.0–P2.3

(38–41)

AD4–AD5

5–6

P3.0–P3.1

(42–43)
TCL0 I/O External clock input for timer/counter0 40 (35) P8.0
TCLO0 I/O Timer/counter clock output 41 (36) P8.1
CLO I/O Clock output 8 (2) P3.2
TCL1 I/O External clock input for timer/counter1 8 (2) P3.2
PWM I/O PWM output 9 (3) P3.3
TCLO1 I/O Timer/counter clock output1 9 (3) P3.3
KS0–KS3 I/O Quasi-interrupt input with falling edge detection 32–35

P6.0–P6.3

(27–30)
V

DD

V

SS

RESET

XIN, X

out

AV

REF

TEST I

– Main power supply 11 (5) –
– Ground 12 (6) –

I Reset signal 18 (12) –

– Crystal, ceramic, or RC oscillator signal for system

clock.

14, 13

(8, 7)

– A/D converter analog reference voltage 7 (1) –

Test signal input (must be connected to V

SS

)

15 (9) –

–

NC – No connection (no bonding pin) (22, 44) –

NOTE: Parentheses indicate 44-QFP pin number.

1-11

PRODUCT OVERVIEW S3C7414/P7414/C7424/P7424/C7434/P7434

Table 1-3. S3C7424 Pin Descriptions

Pin Name Pin Type Description Number Share Pin

P0.0
P0.1
P0.2
P0.3

P1.0
P1.1
P1.2

P2.0
P2.1
P2.2
P2.3

P3.2
P3.3

P4.0
P4.1
P4.2
P4.3

P5.0–P5.3

I/O 4-bit I/O port.

1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.

14 (13)
15 (14)
16 (15)

17 (16)
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.

I 4-bit input port.

1-bit and 4-bit read and test is possible.
3-bit pull-up resistors are individually assignable by

18 (17)

19 (18)

20 (19)
software to pins P1.0, P1.1, and P1.2.

I/O 4-bit I/O port.

N-channel open-drain output.
1-bit or 4-bit write and test is possible.
Individual pins are software configurable as AD input

21 (20)

22 (21)

23 (22)

24 (23)
or output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.

I/O Same as Port 0 (P0.0–P0.3) 27 (25)

28 (26)

I/O 4-bit I/O ports.

Ports 4 and 5 can be configured individually as n­channel open-drain or as CMOS push-pull output by
software.

29 (27)

5 (5)
6 (6)

9 (8)
1-bit and 4-bit read/write and test is possible.
Ports 4 and 5 can be paired to enable 8-bit data
transfer.

10–13

(9–12)
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.

SCK

SO

SI

BUZ

INT0
INT1
INT2

AD0
AD1
AD2
AD3

CLO/TCL1

PWM/TCLO1

–

1-12

S3C7414/P7414/C7424/P7424/C7434/P7434 PRODUCT OVERVIEW

Table 1-3. S3C7424 Pin Descriptions (Continued)

Pin Name Pin Type Description Number Share Pin

SCK

I/O Serial I/O interface clock signal 14 (13) P0.0

SO I/O Serial data output 15 (14) P0.1
SI I/O Serial data input 16 (15) P0.2
BUZ I/O 2 kHz, 4kHz, 8kHz, or 16 kHz frequency output at the

17 (16) P0.3

watch timer clock frequency of 32.768 kHz

INT0, INT1 I External interrupts. The triggering edge for INT0 and

INT1 is selectable. Only INT0 is synchronized with the

18, 19

(17, 18)

P1.0, P1.1

system clock.
INT2 I Quasi-interrupt input with rising edge detection 20 (19) P1.2
AD0–AD3 I/O A/D converter analog inputs 21–24

P2.0–P2.3

(20–23)
CLO I/O Clock output 27 (25) P3.2
TCL1 I/O External clock input for timer/counter1 27 (25) P3.2
PWM I/O PWM output 28 (26) P3.3
TCLO1 I/O Timer/counter clock output1 28 (26) P3.3
V

DD

V

SS

RESET

XIN, X

OUT

AV

REF

TEST I

– Main power supply 30 (28) –
– Ground 1 (1) –

I Reset signal 7 (7) –

– Crystal, ceramic, or RC oscillator signal for system

clock.

3, 2

(3, 2)

– Internal A/D converter analog reference voltage 26 (24) –

Test signal input (must be connected to V

SS

)

4 (4) –

–

NC – No connection (no bonding pin) 8, 25 –

NOTE: Parentheses indicate 28-SOP pin number.

1-13

PRODUCT OVERVIEW S3C7414/P7414/C7424/P7424/C7434/P7434

Table 1-4. Overview of S3C7414/C7424/C7434Pin Data

Pin Names Share Pins I/O Type Reset Value Circuit Type

P0.0–P0.3
P1.0

P1.1
P1.2

SCK, SO, SI, BUZ

(note)

INT0

(note)

INT1

(note)

INT2

I/O Input Type D

I Input Type A-1

P1.3 INT4 I Input Type A
P2.0–P2.3 AD0–AD3 I/O AD input Type F-3
P3.0

P3.1
P3.2
P3.3

P4.0–P4.3

AD4

I/O Input Type F

AD5

CLO/TCL1

TCLO1/PWM

– I/O Input Type E

Type F
Type D
Type D

P5.0–P5.3
P6.0

P6.1
P6.2
P6.3

KS0
KS1
KS2
KS3

(note)
(note)
(note)
(note)

P7.0–P7.3 –

(note)

P8.0
P8.1
P8.2

VDD, V
XIN, X

RESET

AV

REF

SS

OUT

TCL0

TCLO0

–
– – – –

– – – –
–

– –

TEST – I –

I/O

I/O
I/O

I –

Input

Input
Input

Type B-2

– –

Type D

Type D
Type D

(note)

–

NC – – – –

NOTE: A noise filter circuit is built-in.

1-14

S3C7414/P7414/C7424/P7424/C7434/P7434 PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

V

DD

V

DD

P-CHANNEL

IN

N-CHANNEL

Figure 1-8. Pin Circuit Type A

V

DD

PULL-UP
RESISTOR
ENABLE

DATA

1M

Ω

RESET

7pF

Figure 1-10. Pin Circuit Type B-2

V

DD

P-CHANNEL

OUT

IN

CIRCUIT TYPE A

Figure 1-9. Pin Circuit Type A-1

N-CHANNEL

OUTPUT
DISABLE

Figure 1-11. Pin Circuit Type C

1-15

PRODUCT OVERVIEW KS57C4104/P4104/C4204/P4204 MICROCONTROLLER (Preliminary Spec)

V

DD

V

DD

PULL-UP

RESISTOR

ENABLE

PULL-UP

RESISTOR

ENABLE

DATA

OUTPUT

DISABLE

CIRCUIT

TYPE C

I/O

DATA

OUTPUT

DISABLE

DATA

CIRCUIT

TYPE C

IN/OUT

PNE

DATA

OUTPUT
DISABLE

CIRCUIT TYPE A

Figure 1-12. Pin Circuit Type D

V

DD

V

DD

IN/OUT

PULL-UP
RESISTOR
ENABLE

TO ADC

Figure 1-14. Pin Circuit Type F

PULL-UP

RESISTOR

ENABLE

DATA

OUTPUT
DISABLE

DATA

ADC INPUT SELECT

V

DD

IN/OUT

1-16

INPUT

Figure 1-13. Pin Circuit Type E

TO ADC

ADC INPUT SELECT

Figure 1-15. Pin Circuit Type F-3

S3C7414/P7414/C7424/P7424/C7434/P7434 ELECTRICAL DATA

14 ELECTRICAL DATA

OVERVIEW

In this section, information on S3C7414/C7424/C7434 electrical characteristics is presented as tables and
graphics. The information is arranged in the following order:

Standard Electrical Characteristics

— Absolute maximum ratings
— D.C. electrical characteristics
— System clock oscillator characteristics
— Operating voltage range
— A.C. electrical characteristics
— A/D converter electrical characteristics
— I/O capacitance

Stop Mode Characteristics and Timing Waveforms

— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET

— Stop mode release timing when initiated by an interrupt request

Miscellaneous Timing Waveforms

— A.C timing measurement points (except for XIN)
— Clock timing measurement at X
— TCL0/1 timing
— Input timing for RESET signal

— Input timing for external interrupts and quasi-interrupts
— S3C7434 power-on RESET timing

— Serial data transfer timing

IN

14-1

ELECTRICAL DATA S3C7414/P7414/C7424/P7424/C7434/P7434

Table 14-1. S3C7414/C7424 Absolute Maximum Ratings

(T

= 25 °C)

A

Parameter Symbol Conditions Rating Units

Supply Voltage
Input Voltage
Output Voltage
Output Current High

V

DD

I

V

V

O

OH

All I/O ports

I

One pin – 15 mA

– – 0.3 to + 6.5 V

– 0.3 to V

–

– 0.3 to VDD + 0.3

DD

+ 0.3

V
V

All output pins – 35

Output Current Low

I

OL

One pin

peak value

(note)

+ 30 mA

rms value + 15

All pins

peak value

(note)

+ 100

rms value + 60

Operating Temperature
Storage Temperature

T

A

T

stg

– – 40 to + 85
– – 65 to + 150

°

C

°

C

NOTE: The values for Output Current Low (IOL) are calculated as Peak Value × Duty .

14-2

S3C7414/P7414/C7424/P7424/C7434/P7434 ELECTRICAL DATA

Table 14-2. S3C7414/C7424 D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Input High
Voltage

Input Low
Voltage

Output High
Voltage

V

IH1

V

IH2

V

IH3

V

IL1

V

IL2

V

IL3

V

OH

All input pins except those specified
below for V

IH2–VIH3

Ports 0, 1, 3, 6 and RESET
X

IN, XOUT

All input pins except those specified
below for V

IL2–VIL3

Ports 0, 1, 3, 6 and RESET
X

IN, XOUT

VDD = 4.5 V to 5.5 V
IOH = – 1 mA

0.7 V

DD

0.8 V

DD

V

– 0.1 V

DD

–

– –

V

DD

– 1.0

– – V

V

DD

V

DD
DD

0.3 V

0.2 V

0.1

DD

DD

V

V

Ports 0, 2–8

Output Low
Voltage

V

OL

V

= 4.5 V to 5.5 V

DD

I

= 15 mA

OL

– 0.4 2 V

Ports 4 and 5 only
I

= 4 mA

OL

0.2

All output ports except ports 4 and 5

Input High
Leakage Current

Input Low
Leakage Current

I

LIH1

I

LIH2

I

LIL1

VI = V

DD

All input pins except those specified
below for I

VI = V
XIN and X

DD

LIH2

OUT

only

VI = 0 V
All input pins except XIN and X

OUT

– – 3 µA

20

– – – 3 µA

,

RESET

Output High
Leakage Current

Output Low
Leakage Current

Pull-up Resistor

Pull-up Resistor

I

LIL2

I

LOH

I

LOL

R

R

L1

L2

V

= 0 V

I

X

and X

IN

V

O

= V

OUT

DD

All output pins
V

= 0 V

O

All output pins
V

= 0 V; V

I

V

= 0 V; V

I

V

= 0 V; V

I

V

= 0 V; V

I

DD

DD

DD

DD

only

= 5 V except RESET
= 3 V except RESET
= 5 V; RESET
= 3 V; RESET

– 20

– – 3 µA

– – – 3 µA

25 50 100

50 100 200
100 250 400
200 500 800

kΩ

kΩ

14-3

ELECTRICAL DATA S3C7414/P7414/C7424/P7424/C7434/P7434

Table 14-2. S3C7414/C7424 D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Supply
Current

(1)

I

DD1

Run mode; V

= 5.0 V ± 10%

DD

6.0MHz – 3.0 8.0
Crystal oscillator; C1=C2=22pF 4.19MHz 2.3 5.5
V

= 3 V ± 10%

DD

6.0MHz 1.4 4.0

mA

4.19MHz 1.1 3.0

I

DD2

Idle mode; V

= 5.0 V ± 10%

DD

6.0MHz – 1.1 2.5

mA

Crystal oscillator; C1=C2=22pF 4.19MHz 1.0 1.8
V

= 3 V ± 10%

DD

6.0MHz 0.5 1.5

4.19MHz 0.4 1.0

I

DD3

NOTES:

1. D.C. electrical values for Supply current (I
output port drive currents and ADC.

2. The supply current assumes a CPU clock of fx/4.

Stop mode; V
Stop mode; V

= 5.0 V ± 10%

DD

= 3.0 V ± 10%

DD

to I

DD1

) do not include current drawn through internal pull-up registers,

DD3

– 0.1 5.0

0.1 3.0

µA

14-4

S3C7414/P7414/C7424/P7424/C7434/P7434 ELECTRICAL DATA

Table 14-3. S3C7414/C7424 System Clock Oscillator Characteristics

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Oscillator Clock

Configuration

Ceramic

Xin Xout

Oscillator

C1 C2

Crystal

Xin Xout

Oscillator

C1 C2

External

Xin Xout

Clock

Parameter Test Condition Min Typ Max Units

(1)

Oscillation frequency

Stabilization time

(2)

Oscillation frequency

Stabilization time
XIN input frequency

(2)

(1)

VDD = 2.7 V to 5.5 V

VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 3.0 V

(1)

VDD = 2.7 V to 5.5 V

VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 3.0 V
VDD = 2.7 V to 5.5 V

0.4 – 6.0 MHz

0.4 – 4.2

0.4 – 3.0
– – 4 ms

0.4 – 6.0 MHz

0.4 – 4.2

0.4 – 3.0
– – 10 ms

0.4 – 6.0 MHz

XIN input high and low

VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V

– 83.3 – 1250 ns

0.4 – 4.2

0.4 – 3.0

level width (tXH, tXL)

RC

Xin Xout

Oscillator

R

NOTES:

1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.

Oscillation frequency
limitation

VDD = 5 V
R = 8.2 KΩ

– 4 – MHz

14-5

ELECTRICAL DATA S3C7414/P7414/C7424/P7424/C7434/P7434

Main Oscillator Frequency

CPU CLOCK

1.5 MHz

(Divided by 4)
6 MHz

1.05 MHz

0.75 MHz

15.6 kHz
1 2 3 4 5 6

2.7 5.5

1.8

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

4.2 MHz
3 MHz

Figure 14-1. S3C7414/C7424 Standard Operating Voltage Range

Table 14-4. S3C7414/C7424 A.C. Electrical Characteristics

(TA = – 40 °C to + 85 °C, V

= 1.8 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Units

Instruction Cycle
Time

t

CY

V

= 2.7 V to 5.5 V

DD

VDD = 1.8 V to 5.5 V

0.67 – 64

1.33

µs

TCL0/1 Input
Frequency
TCL0/1 Input High,
Low Width

SCK Cycle Time

14-6

f

TI

t

TIH, tTIL

t

KCY

V

= 2.7 V to 5.5 V

DD

VDD = 1.8 V to 5.5 V
V

= 2.7 V to 5.5 V

DD

VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V

External SCK source
Internal SCK source

VDD = 1.8 V to 5.5 V
External SCK source

Internal SCK source

0 – 1.5 MHz

0.75 MHz

0.48 – –

1.8

800 – – ns

670

3200

3800

µs

S3C7414/P7414/C7424/P7424/C7434/P7434 ELECTRICAL DATA

Table 14-4. S3C7414/C7424 A.C. Electrical Characteristics (Continued)

(TA = – 40 °C to + 85 °C, V

= 1.8 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Units

SCK High, Low
Width

tKH, t

KLVDD

= 2.7 V to 5.5 V

External SCK source
Internal SCK source

VDD = 1.8 V to 5.5 V

335 – – ns

t

/2 – 50

KCY

1600

External SCK source

t

/2 – 150

KCY

100 – – ns

150
150

SI Setup Time to
SCK High

t

SIK

Internal SCK source
VDD = 2.7 V to 5.5 V

External SCK source
Internal SCK source

VDD = 1.8 V to 5.5 V
External SCK source

500
400 – – ns

400
600

SI Hold Time to
SCK High

t

KSI

Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source

Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source

500

– – 300 ns

250

1000

Output Delay for
SCK to SO

t

KSO

Internal SCK source

(1)

VDD = 2.7 V to 5.5 V
External SCK source

Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source

1000

Interrupt Input
High, Low Width

t

INTH

t

INTL

Internal SCK source

,

INT0

(2)

– –

INT1, INT2, INT4, KS0–KS3 10

RESET Input

t

RSL

Input 10 – –

Low Width

µs

µs

NOTES:

1. R(1KΩ) and C (100pF) are the load resistance and load capacitance of the SO output line.

2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.

14-7

ELECTRICAL DATA S3C7414/P7414/C7424/P7424/C7434/P7434

Table 14-5. S3C7434 Absolute Maximum Ratings

(T

= 25 °C)

A

Parameter Symbol Conditions Rating Units

Supply Voltage
Input Voltage
Output Voltage
Output Current High

V

DD

I

V

V

O

OH

All I/O ports

I

One pin – 15 mA

– – 0.3 to + 6.5 V

– 0.3 to V

–

– 0.3 to VDD + 0.3

DD

+ 0.3

V
V

All output pins – 35

Output Current Low

I

OL

One pin

peak value

(note)

+ 30 mA

rms value + 15

All pins

peak value

(note)

+ 100

rms value + 60

Operating Temperature
Storage Temperature

T

A

T

stg

– – 40 to + 85
– – 65 to + 150

°

C

°

C

NOTE: The values for Output Current Low (IOL) are calculated as Peak Value × Duty .

14-8

S3C7414/P7414/C7424/P7424/C7434/P7434 ELECTRICAL DATA

Table 14-6. S3C7434 D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.5 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Input High
Voltage

Input Low
Voltage

Output High
Voltage

V

IH1

V

IH2

V

IH3

V

IL1

V

IL2

V

IL3

V

OH

All input pins except those specified
below for V

IH2–VIH3

Ports 0, 1, 3, 6 and RESET
X

IN, XOUT

All input pins except those specified
below for V

IL2–VIL3

Ports 0, 1, 3, 6 and RESET
X

IN, XOUT

VDD = 4.5 V to 5.5 V
IOH = – 1 mA

0.7 V

DD

0.8 V

DD

V

– 0.1 V

DD

–

– –

V

DD

– 1.0

– – V

V

DD

V

DD
DD

0.3 V

0.2 V

0.1

DD

DD

V

V

Ports 0, 2–8

Output Low
Voltage

V

OL

V
I

DD

OL

= 3.5 V

= 15 mA

– 0.4 2 V

Ports 4 and 5 only
I

OL

= 4 mA

0.2

All output ports except ports 4 and 5

Input High
Leakage Current

Input Low
Leakage Current

I

LIH1

I

LIH2

I

LIL1

VI = V

DD

All input pins except those specified
below for I

VI = V
XIN and X

DD

LIH2

OUT

only

VI = 0 V
All input pins except XIN and X

OUT,

– – 3 µA

20

– – – 3 µA

RESET

Output High
Leakage Current

Output Low
Leakage Current

Pull-Up Resistor

Pull-Up Resistor

I

LIL2

I

LOH

I

LOL

R

R

L1

L2

V

= 0 V

I

X

and X

IN

V

O

= V

OUT

DD

All output pins
V

= 0 V

O

All output pins
V

= 0 V; V

I

V

= 0 V; V

I

V

= 0 V; V

I

V

= 0 V; V

I

DD

DD

DD

DD

only

= 5 V except RESET
= 3 V except RESET
= 5 V; RESET
= 3 V; RESET

– 20

– – 3 µA

– – – 3 µA

25 50 100

50 100 200
100 250 400
200 500 800

kΩ

kΩ

14-9

ELECTRICAL DATA S3C7414/P7414/C7424/P7424/C7434/P7434

Table 14-6. S3C7434 D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 2.5 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Supply
Current

(1)

I

DD1

Run mode; V

= 5.0 V ± 10%

DD

6.0MHz – 3.1 8.0
Crystal oscillator; C1 = C2 = 22pF 4.19MHz 2.4 5.5
V

= 3 V ± 10%

DD

6.0MHz 1.5 4.0

mA

4.19MHz 1.2 3.0

I

DD2

Idle mode; V

= 5.0 V ± 10%

DD

6.0MHz – 1.2 2.5

mA

Crystal oscillator; C1 = C2 = 22pF 4.19MHz 1.1 1.8
V

= 3 V ± 10%

DD

6.0MHz 0.6 1.5

4.19MHz 0.5 1.0

I

DD3

NOTES:

1. D.C. electrical values for Supply current (I
output port drive currents and ADC.

2. The supply current assumes a CPU clock of fx/4.

Stop mode; V
Stop mode; V

= 5.0 V ± 10%

DD

= 3.0 V ± 10%

DD

to I

DD1

) do not include current drawn through internal pull-up registers,

DD3

– 120 200

100 150

µA

Table 14-7. S3C7434 Power-On Reset Circuit Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.5 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Power-On Reset

V

DDH

Voltage High
Power-On Reset

V

DDL

Voltage Low
Power Supply

t

r

Voltage Rise Time
Power Supply

t

off

Voltage Off Time

I

Power-On Reset Circuit
Cunsumption Current

NOTES:

1. 217/fx (= 31.3 ms at fx = 4.19 MHz)

2. Current consumed when power-on reset circuit is provided internally.

(2)

DDPR

V

= 5 V ± 10%

DD

V

= 3 V ± 10%

DD

2.5 5.5 V

0 2.0 2.2 V

10

(1)

us

0.5 s

120 200 uA
100 150 uA

14-10

S3C7414/P7414/C7424/P7424/C7434/P7434 ELECTRICAL DATA

Table 14-8. S3C7434 System Clock Oscillator Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.5 V to 5.5 V)

A

Oscillator Clock

Configuration

Ceramic

Xin Xout

Oscillator

C1 C2

Crystal

Xin Xout

Oscillator

C1 C2

External

Xin Xout

Clock

Parameter Test Condition Min Typ Max Units

(1)

Oscillation frequency

Stabilization time

(2)

Oscillation frequency

Stabilization time
XIN input frequency

(2)

(1)

VDD = 2.7 V to 5.5 V

VDD = 2.5 V to 5.5 V
VDD = 3.0 V

(1)

VDD = 2.7 V to 5.5 V

VDD = 2.5 V to 5.5 V
VDD = 3.0 V
VDD = 2.7 V to 5.5 V

0.4 – 6.0 MHz

0.4 – 4.2
– – 4 ms

0.4 – 6.0 MHz

0.4 – 4.2
– – 10 ms

0.4 – 6.0 MHz

XIN input high and low

VDD = 2.5 V to 5.5 V

– 83.3 – 1250 ns

0.4 – 4.2

level width (tXH, tXL)

RC
Oscillator

NOTES:

1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.

Xin Xout

R

Oscillation frequency
limitation

VDD = 5 V
R = 8.2 KΩ

– 4 – MHz

14-11

ELECTRICAL DATA S3C7414/P7414/C7424/P7424/C7434/P7434

Main Oscillator Frequency

CPU CLOCK

1.5 MHz

(Divided by 4)
6 MHz

1.05 MHz

0.75 MHz

15.6 kHz

4.2 MHz
3 MHz

1 2 3 4 5 6

1.8

2.7 5.5

2.5

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 14-2. S3C7434 Standard Operating Voltage Range

14-12

S3C7414/P7414/C7424/P7424/C7434/P7434 ELECTRICAL DATA

Table 14-9. S3C7434 A.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, V

A

= 2.5 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Units

Instruction Cycle

t

CY

VDD = 2.7 V to 5.5 V

0.67 – 64 µs

Time
TCL0/1 Input

f

TI0

VDD = 2.7 V to 5.5 V

0 – 1.5 MHz

Frequency
TCL0/1 Input

TIH0

, t

TIL0VDD

= 2.7 V to 5.5 V

0.48 – – µs

t

High, Low Width
SCK Cycle Time

t

KCY

VDD = 2.7 V to 5.5 V

800 – – ns

External SCK source

670
325 – – ns

t

/2 – 50

KCY

100 – – ns

150
400 – – ns

400

– – 300 ns

250

(NOTE)

– – µs

SCK High, Low
Width

SI Setup Time to
SCK High

SI Hold Time to
SCK High

Output Delay for
SCK to SO

Interrupt Input
High, Low Width

RESET Input

tKH, t

t

SIK

t

KSI

t

KSO

t

INTH

t

INTL

t

RSL

Internal SCK source
VDD = 2.7 V to 5.5 V

KL

External SCK source
Internal SCK source

VDD = 2.7 V to 5.5 V
External SCK source

Internal SCK source
V

= 2.7 V to 5.5 V

DD

External SCK source
Internal SCK source

VDD = 2.7 V to 5.5 V
External SCK source

Internal SCK source

,

INT0
INT1, INT2, INT4, KS0–KS3 10

Input 10 – – µs

Low Width

NOTE: Minimum value for INT0 is based on a clock of 2t

or 128/fx as assigned by the IMOD0 register setting.

CY

14-13

ELECTRICAL DATA S3C7414/P7414/C7424/P7424/C7434/P7434

Table 14-10. A/D Converter Electrical Characteristics

(T

= – 10 °C to + 70 °C, VDD = 3.5 V to 5.5 V, VSS = AVSS = 0 V)

A

Parameter Symbol Condition Min Typ Max Units

Resolution – – 8 8 8 bit
Absolute accuracy

Conversion time

(1)

(2)

Analog input voltage
Analog input impedance

NOTES:

1. Absolute accuracy does not include the quantization error (± 1/2 LSB).

2. Conversion time is the time required from the moment a conversion operation starts until it ends (EOC = 0).

3. 'fx' is the abbreviation for system clock.

t

CON

V

IAN

R

–

AN

2.5 V < AV

< V

REF

DD

– –
–

– –

AV

SS

96/fx

–

± 1.5

(3)

AV

– – 1000 –

LSB

– µs

REF

V

MΩ

Table 14-11. Input/Output Capacitance

(TA = 25 °C, V

DD

= 0 V )

Parameter Symbol Condition Min Typ Max Units

C

C

IN

OUT

f = 1 MHz; Unmeasured pins
are returned to V

SS

– – 15 pF

– – 15 pF

Input
Capacitance

Output
Capacitance

I/O Capacitance

C

IO

– – 15 pF

Table 14-12. RAM Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

(1)

V

DDDR

I

DDDR

t

SREL

t

WAIT

– 1.8 – 5.5 V
– – 0.1 10 µA
– 0 – – ms

When released by

–

217/fx

– ms

Data retention supply voltage
Data retention supply current
Release signal set time
Oscillation stabilization time

RESET

When released by

–

(2)

– ms

interrupt

NOTES:

1. During oscillation stabilization time, CPU operation must be stopped to avoid unstable operation upon oscillation start.

2. The basic timer causes a delay of 217/fx after a reset.

14-14

S3C7414/P7414/C7424/P7424/C7434/P7434 ELECTRICAL DATA

TIMING WAVEFORMS

INTERNAL RESET

OPERATION

V

DD

RESET

V

DD

~

~

~

~

EXECUTION OF

STOP INSTRUCTION

STOP MODE

DATA RETENTION MODE

V

DDDR

t

SREL

IDLE MODE

t

WAIT

Figure 14-3. Stop Mode Release Timing When Initiated By RESETRESET

IDLE MODE

~

~

~

~

STOP MODE

DATA RETENTION

OPERATING
MODE

NORMAL
OPERATING
MODE

EXECUTION OF

STOP INSTRUCTION

POWER-DOWN MODE TERMINATING
(INTERRUPT REQUEST)

V

DDDR

t

SREL

t

WAIT

Figure 14-4. Stop Mode Release Timing When Initiated By Interrupt Request

14-15

ELECTRICAL DATA S3C7414/P7414/C7424/P7424/C7434/P7434

0.8 V

0.2 V

DD

DD

MEASUREMENT

POINTS

0.8 V

0.2 V

DD

DD

Figure 14-5. A.C. Timing Measurement Points (Except for XIN)

1 / f

x

t

XL

X

IN

t

XH

V

DD

0.4 V

– 0.5 V

TCL0

Figure 14-6. Clock Timing Measurement at X

1 / f

TI0

t

TIL0

t

TIH0

Figure 14-7. TCL0/1 Timing

IN

0.8 V

0.2 V

DD
DD

14-16

S3C7414/P7414/C7424/P7424/C7434/P7434 ELECTRICAL DATA

t

RSL

RESET

0.2 V

DD

Figure 14-8. Input Timing for RESETRESET Signal

INT0, 1, 2, 4
KS0 to KS3

Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts

t

INTL

0.8 V

0.2 V

DD

DD

t

INTH

14-17

ELECTRICAL DATA S3C7414/P7414/C7424/P7424/C7434/P7434

SCK

t

off

V

DD

V

V

DDH

DDL

t

r

Figure 14-10. S3C7434 Power-On RESETRESET Timing

t

KCY

t

KL

t

KH

0.8 V

0.2 V

DD
DD

SI

SO

t

KSO

t

SIK

INPUT DATA

t

KSI

0.8 V

0.2 V

DD
DD

OUTPUT DATA

Figure 14-11. Serial Data Transfer Timing

14-18

S3C7414/P7414/C7424/P7424/C7434/P7434 MECHANICAL DATA

15 MECHANICAL DATA

This section contains the following information about the device package:
— Package dimensions in millimeters

— Pad diagram

(1.77)

#42 #22

42-SDIP-600

14.00 ± 0.2

#1 #21

39.50 MAX

39.10 ± 0.2

0.50 ± 0.1

1.00 ± 0.1

NOTE: Dimensions are in millimeters.

1.778

15.24

3.50 ± 0.2

0.51MIN

3.30 ± 0.3 5.08MAX

+0.1

0.25

0-15

– 0.05

°

Figure 15-1. 42-SDIP-600 Package Dimensions

15-1

MECHANICAL DATA S3C7414/P7414/C7424/P7424/C7434/P7434

13.20 ± 0.3

10.00 ± 0.2

#44

0.80

13.20 ± 0.3

10.00 ± 0.2

44-QFP-1010

#1

0.35

+0.10

- 0.05

(1.00)

0-8°

+0.10

0.15

- 0.05

0.10 MAX

0.05 MIN

2.05 ± 0.10

2.30 MAX

0.80±0.20

NOTE: Dimensions are in millimeters.

Figure 15-2. 44-QFP-1010 Package Dimensions

15-2

S3C7414/P7414/C7424/P7424/C7434/P7434 MECHANICAL DATA

#30 #16

30-SDIP-400

8.94 ± 0.2

#1 #15

27.88 MAX

27.48 ± 0.2

± 0.1

0.56

(1.30)

NOTE: Dimensions are in millimeters.

1.12 ± 0.1

1.778

10.16

0.51MIN 3.81 ± 0.2

5.08MAX

3.30 ± 0.3

+0.1

0.25

0-15

– 0.05

°

Figure 15-3. 30-SDIP-400 Package Dimensions

15-3

MECHANICAL DATA S3C7414/P7414/C7424/P7424/C7434/P7434

#28 #15

28-SOP-375

10.45 ± 0.3

#1 #14

(0.56) 0.41

18.02 MAX

17.62 ± 0.2

± 0.1

1.27

7.70 ± 0.2

+0.10

0.15

- 0.05

2.15 ± 0.2

0.05MIN

0-8°

9.53

0.60 ± 0.20

2.55MAX

0.10 MAX

NOTE: Dimensions are in millimeters.

Figure 15-4. 28-SOP-375 Package Dimensions

15-4

S3C7414/P7414/C7424/P7424/C7434/P7434 S3P7414/P7424/P7434 OTP

16 S3P7414/P7424/P7434 OTP

OVERVIEW

The S3P7414/P7424/P7434 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of

the S3C7414/C7424/C7434 microcontroller. It has an on-chip OTP ROM instead of masked ROM. Samsung′s
own serial protocol used for OTP program pin information regarding OTP program can be referred OTP pin
description.

The S3P7414/P7424/P7434 is fully compatible with the S3C7414/C7424/C7434, in function, in D.C. electrical
characteristics and in pin configuration. Because of its simple programming requirements, the
S3P7414/P7424/P7434 is ideal for use as an evaluation chip for the S3C7414/C7424/C7434.

16-1

S3P7414/P7424/P7434 OTP S3C7414/P7414/C7424/P7424/C7434/P7434

P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P3.0/AD4
P3.1/AD5

AVREF

P3.2/CLO/TCL1

SDAT/P3.3/PWM/TCLO1

SCLK/P4.0

VDD/VDD

VSS/VSS

XOUT

XIN

VPP/TEST

P4.1
P4.2

RESETRESET/RESET

P4.3
P5.0
P5.1

NOTE: The bolds indicate an OTP pin name.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

S3P7414

(42-SDIP)

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

P8.2
P8.1/TCLO0
P8.0/TCL0
P7.3
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P0.1/SO
P0.0/SCK
P5.3
P5.2

Figure 16-1. S3P7414 Pin Assignments (42-SDIP)

16-2

S3C7414/P7414/C7424/P7424/C7434/P7434 S3P7414/P7424/P7434 OTP

NC

P3.1/AD5

P3.0/AD4

P2.3/AD3

P2.2/AD2

P2.1/AD1

P2.0/AD0

P8.2

P8.1/TCLO0

P8.0/TCL0

P7.3

AVREF

P3.2/CLO/TCL1

SDAT/P3.3/PWM/TCLO1

SCLK/P4.0

VDD/VDD

VSS/VSS

XOUT

XIN

VPP/TEST

P4.1
P4.2

Figure 16-2. S3P7414 Pin Assignments (44-QFP)

4443424140393837363534

1
2
3
4
5
6
7
8
9
10
11

NOTE: The bolds indicate an OTP pin name.

S3P7414

(44-QFP)

1213141516171819202122

P4.3

P5.0

P5.1

P5.2

P5.3

RESET

P0.1/SO

P0.0/SCK

33
32
31
30
29
28
27
26
25
24
23

NC

P0.2/SI

P0.3/BUZ

P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0

16-3

S3P7414/P7424/P7434 OTP S3C7414/P7414/C7424/P7424/C7434/P7434

VSS/VSS

XOUT

XIN

VPP/TEST

P4.1
P4.2

RESETRESET/RESET

NC
P4.3
P5.0
P5.1
P5.2
P5.3

P0.0/SCK

P0.1/SO

NOTE: The bolds indicate an OTP pin name.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

S3P7424

(30-SDIP)

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

VDD/VDD
P4.0/SCLK
P3.3/PWM/TCLO1/SDAT
P3.2/CLO/TCL1
AVREF
NC
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI

Figure 16-3. S3P7424 Pin Assignments (30-SDIP)

VSS/VSS

XOUT

XIN

VPP/TEST

P4.1
P4.2

RESETRESET/RESET

P4.3
P5.0
P5.1
P5.2
P5.3

P0.0/SCK

P0.1/SO

NOTE: The bolds indicate an OTP pin name.

1
2
3
4
5
6
7
8
9
10
11
12
13
14

S3P7424

(28-SOP)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

VDD/VDD
P4.0/SCLK
P3.3/PWM/TCLO1/SDAT
P3.2/CLO/TCL1
AVREF
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI

Figure 16-4. S3P7424 Pin Assignments (28-SOP)

16-4

S3C7414/P7414/C7424/P7424/C7434/P7434 S3P7414/P7424/P7434 OTP

P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P3.0/AD4
P3.1/AD5

AVREF

P3.2/CLO/TCL1

SDAT/P3.3/PWM/TCLO1

SCLK/P4.0

VDD/VDD

VSS/VSS

XOUT

XIN

VPP/TEST

P4.1
P4.2

RESETRESET/RESET

P4.3
P5.0
P5.1

NOTE: The bolds indicate an OTP pin name.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

S3P7434

(42-SDIP)

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

P8.2
P8.1/TCLO0
P8.0/TCL0
P7.3
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P0.1/SO
P0.0/SCK
P5.3
P5.2

Figure 16-5. S3P7434 Pin Assignments (42-SDIP)

16-5

S3P7414/P7424/P7434 OTP S3C7414/P7414/C7424/P7424/C7434/P7434

NC

P3.1/AD5

P3.0/AD4

P2.3/AD3

P2.2/AD2

P2.1/AD1

P2.0/AD0

P8.2

P8.1/TCLO0

P8.0/TCL0

P7.3

AVREF

P3.2/CLO/TCL1

SDAT/P3.3/PWM/TCLO1

SCLK/P4.0

VDD/VDD

VSS/VSS

XOUT

XIN

VPP/TEST

P4.1
P4.2

Figure 16-6. S3P7434 Pin Assignments (44-QFP)

4443424140393837363534

1
2
3
4
5
6
7
8
9
10
11

NOTE: The bolds indicate an OTP pin name.

S3P7434

(44-QFP)

1213141516171819202122

P4.3

P5.0

P5.1

P5.2

P5.3

RESET

P0.1/SO

P0.0/SCK

33
32
31
30
29
28
27
26
25
24
23

NC

P0.2/SI

P0.3/BUZ

P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0

16-6

S3C7414/P7414/C7424/P7424/C7434/P7434 S3P7414/P7424/P7434 OTP

Table 16-1. Pin Descriptions of S3P7414/P7434 Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P3.3 SDAT 9 (3) I/O Serial data pin. Output port when reading and input

port when writing. Can be assigned as a Input /
push-pull output port.

P4.0 SCLK 10 (4) I/O Serial clock pin. Input only pin.

V

TEST

PP

(TEST)

15 (9) I Power supply pin for EPROM cell writing (indicates

that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)

RESET RESET

VDD/V

SS

VDD/V

SS

18 (12) I Chip initialization

11/12 (5/6) I

Logic power supply pin. VDD should be tied to +5 V
during programming.

NOTE: Parentheses indicate 44-QFP pin number.

Table 16-2. Pin Descriptions of S3P7424 Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P3.3 SDAT 28 (26) I/O Serial data pin. Output port when reading and input

port when writing. Can be assigned as a Input /
push-pull output port.

P4.0 SCLK 29 (27) I/O Serial clock pin. Input only pin.

V

TEST

PP

(TEST)

4 (4) I Power supply pin for EPROM cell writing (indicates

that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)

RESET RESET

VDD/V

SS

VDD/V

SS

7 (7) I Chip initialization

30/1 (28/1) I

Logic power supply pin. VDD should be tied to +5 V
during programming.

NOTE: Parentheses indicate 28-SOP pin number.

16-7

S3P7414/P7424/P7434 OTP S3C7414/P7414/C7424/P7424/C7434/P7434

Table 16-3. Comparison of S3P7414/P7424 and S3C7414/C7424 Features

Characteristic S3P7414/P7424 S3C7414/C7424

Program Memory 4 K byte EPROM 4 K byte mask ROM
Operating Voltage (VDD)

1.8 V to 5.5 V 1.8 V to 5.5 V

OTP Programming Mode

VDD = 5 V, VPP(TEST)=12.5V

Pin Configuration 42 SDIP, 44 QFP, 30 SDIP, 28 SOP 42 SDIP, 44 QFP, 30 SDIP, 28 SOP
EPROM Programmability User Program 1 time Programmed at the factory

Table 16-4. Comparison of S3P7434 and S3C7434 Features

Characteristic S3P7434 S3C7434

Program Memory 4 K byte EPROM 4 K byte mask ROM
Operating Voltage (VDD)

OTP Programming Mode

2.5 V to 5.5 V 2.5 V to 5.5 V
VDD = 5 V, VPP(TEST)=12.5V

Pin Configuration 42 SDIP, 44 QFP 42 SDIP, 44 QFP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP(TEST) pin of the S3P7414/P7424/P7434, the EPROM programming mode is
entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins

listed in Table 16-4 below.

Table 16-5. Operating Mode Selection Criteria

V

DD

V

PP

(TEST)

REG/
MEM

Address
(A15-A0)

R/W Mode

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

16-8

S3C7414/P7414/C7424/P7424/C7434/P7434 S3P7414/P7424/P7434 OTP

START

Address= First Location

VDD=5V, VPP=12.5V

x = 0

Program One 1ms Pulse

Increment X

FAIL

Device Failed

Verify Byte

YES

x = 10

NO

FAIL

NO

FAIL

Verify 1 Byte

Last Address

V

= VPP= 5 V

DD

Compare All Byte

PASS

Device Passed

Figure 16-7. OTP Programming Algorithm

Increment Address

16-9

S3P7414/P7424/P7434 OTP S3C7414/P7414/C7424/P7424/C7434/P7434

Table 16-6. S3P7414/P7424 D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Supply
Current

(1)

I

DD1

Run mode; V

= 5.0 V ± 10%

DD

6.0MHz – 3.0 8.0
Crystal oscillator; C1=C2=22pF 4.19MHz 2.3 5.5
V

= 3 V ± 10%

DD

6.0MHz 1.4 4.0

mA

4.19MHz 1.1 3.0

I

DD2

Idle mode; V

= 5.0 V ± 10%

DD

6.0MHz – 1.1 2.5

mA

Crystal oscillator; C1=C2=22pF 4.19MHz 1.0 1.8
V

= 3 V ± 10%

DD

6.0MHz 0.5 1.5

4.19MHz 0.4 1.0

I

DD3

NOTES:

1. D.C. electrical values for Supply current (I
output port drive currents and ADC.

2. The supply current assumes a CPU clock of fx/4.

Stop mode; V
Stop mode; V

= 5.0 V ± 10%

DD

= 3.0 V ± 10%

DD

to I

DD1

) do not include current drawn through internal pull-up registers,

DD3

– 0.1 5.0

0.1 3.0

µA

CPU CLOCK

1.5 MHz

1.05 MHz

0.75 MHz

15.6 kHz

Figure 16-8. S3P7414/P7424 Standard Operating Voltage Range

1 2 3 4 5 6

2.7 5.5

1.8

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

Main Oscillator Frequency
(Divided by 4)

6 MHz

4.2 MHz
3 MHz

16-10

S3C7414/P7414/C7424/P7424/C7434/P7434 S3P7414/P7424/P7434 OTP

Table 16-7. S3P7434 D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.5 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Supply
Current

(1)

I

DD1

Run mode; V

= 5.0 V ± 10%

DD

6.0MHz – 3.1 8.0
Crystal oscillator; C1=C2=22pF 4.19MHz 2.4 5.5
V

= 3 V ± 10%

DD

6.0MHz 1.5 4.0

mA

4.19MHz 1.2 3.0

I

DD2

Idle mode; V

= 5.0 V ± 10%

DD

6.0MHz – 1.2 2.5

mA

Crystal oscillator; C1=C2=22pF 4.19MHz 1.1 1.8
V

= 3 V ± 10%

DD

6.0MHz 0.6 1.5

4.19MHz 0.5 1.0

I

DD3

NOTES:

1. D.C. electrical values for Supply current (I
output port drive currents and ADC.

2. The supply current assumes a CPU clock of fx/4.

Stop mode; V
Stop mode; V

= 5.0 V ± 10%

DD

= 3.0 V ± 10%

DD

to I

DD1

) do not include current drawn through internal pull-up registers,

DD3

– 120 200

100 150

µA

CPU CLOCK

1.5 MHz

1.05 MHz

15.6 kHz

Main Oscillator Frequency
(Divided by 4)

6 MHz

4.2 MHz

1 2 3 4 5 6

2.5 5.5

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 16-9. S3P7434 Standard Operating Voltage Range

16-11

S3P7414/P7424/P7434 OTP S3C7414/P7414/C7424/P7424/C7434/P7434

NOTES

16-12