Page 1
S3C7324/P7324 PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
OVERVIEW
The S3C7324 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With features such as LCD direct drive capability, 4-channel A/D converter, 24-bit AM/FM frequency counter and
watch timer, the S3C7324 offers an excellent design solution for a wide variety of applications that require LCD
functions and audio applications.
Up to 32 pins of the 64-pin QFP package, it can be dedicated to I/O. Five vectored interrupts provide fast
response to internal and external events. In addition, the S3C7324 's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The S3C7324 microcontroller is also available in OTP (One Time Programmable) version, S3P7324 . The
S3P7324 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The
S3P7324 is comparable to S3C7324, both in function and in pin configuration.
1-1
Page 2
PRODUCT OVERVIEW S3C7324/P7324
FEATURES
Memory
— 256 × 4-bit RAM
— 4096 × 8-bit ROM
I/O Pins
— Input only: 8 pins
— I/O: 16 pins
— Output only: 8 pins sharing with segment driver
outputs
LCD Controller/Driver
— Maximum 14-digit LCD direct drive capability
— 28 segment and 4 common pins
— Display modes: Static, 1/2 duty (1/2 bias)
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
— Internal resistor circuit for LCD bias
8-Bit Basic Timer
— Programmable interval timer
— Watchdog timer
Bit Sequential Carrier
— Support 16-bit serial data transfer in arbitrary
format
Interrupts
— Two internal vectored interrupts
— Three external vectored interrupts
— Two quasi-interrupts
Memory-Mapped I/O Structure
— Data memory bank 15
Two Power-Down Modes
— Idle mode (only CPU clock stops)
— Stop mode (main system clock stops)
— Subsystem clock stops
Oscillation Sources
— Crystal, ceramic, or RC for main system clock
— Crystal or external oscillator for subsystem clock
— Main system clock frequency: 4.19 MHz (typical)
8-Bit Timer
— Programmable 8-bit timer
Watch Timer
— Real-time and interval time measurement
— Four frequency outputs to BUZ pin
— Clock source generation for LCD
24-Bit Frequency Counter (FC)
— Level = 300mVpp (Min.)
— AMF input range = 0.5 MHz to 10 MHz
— FMF input range = 30 MHz to 150 MHz
A/D Converter
— 4-channels with 8-bit resolution
— 17 µs (Min.) conversion speed
— Subsystem clock frequency: 32.768 kHz
— CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
— 0.95, 1.91, 15.3 µs at 4.19 MHz (main)
— 122 µs at 32.768 kHz (subsystem)
Operating Temperature
— – 40 °C to 85 °C
Operating Voltage Range
— 1.8 V to 5.5 V at 3 MHz
— 3.0 V to 5.5 V at FC mode
Package Type
— 64-pin QFP
1-2
Page 3
S3C7324/P7324 PRODUCT OVERVIEW
BLOCK DIAGRAM
X
N
I
XT
IN
X
OUT
XT
RESET
OUT Watchdog
Timer
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P2.0
P2.1
P2.2/FMF
P2.3/AMF
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
P4.0-P4.3
P5.0-P5.3
P6.0/BUZ
P6.1/KS0
P6.2/KS1
P6.3/KS2
I/O Port 1
Input
Port 2
Input
Port 3
A/D
Converter
I/O
Port 4, 5
I/O Port 6
Interrupt
Control
Block
Internal
Interrupts
Instruction Decoder
Arithmetic
Logic Unit
256 x 4-Bit
Data
Memory
and
Clock
Instruction
Register
Program
Counter
Program
Status Word
Stack
Pointer
4-Kbyte
Program
Memory
Basic
Timer
Freq.
Counter
8-Bit
Timer
LCD Driver/
Countroller
Output
Port 8,9
Watch
Timer
FMF
AMF
COM0-COM3
SEG0-SEG19
P8.0-P8.3/
SEG27-SEG24
P9.0-P9.3/
SEG23-SEG20
Figure 1-1. S3C7324 Simplified Block Diagram
1-3
Page 4
PRODUCT OVERVIEW S3C7324/P7324
PIN ASSIGNMENTS
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
64
63
62
61
60
59
58
57
56
55
54
53
52
P2.0
P2.1
P2.2/FMF
P2.3/AMF
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
VDD
VSS
X
OUT
XIN
TEST
XTIN
XT
OUT
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
S3C7324
(Top View)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
P9.3/SEG20
P9.2/SEG21
P9.1/SEG22
P9.0/SEG23
P8.3/SEG24
P8.2/SEG25
P8.1/SEG26
P8.0/SEG27
1-4
20
21
22
23
24
25
26
27
28
29
30
31
32
P4.0
P4.1
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
P6.1/KS0
P6.2/KS1
P1.3/INT4
P6.0/BUZ
P6.3/KS2
Figure 1-2. S3C7324 64-QFP Pin Assignment
Page 5
S3C7324/P7324 PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7324 Pin Descriptions
Pin Name Pin
P1.0
P1.1
P1.2
P1.3
Type
I/O 4-bit I/O port.
1-bit or 4-bit read, write, and test are
possible. Each pin can be specified as
input or output port. Pull-up resistors can
Description Number Share
Pin
17
18
19
20
INT0
INT1
INT2
INT4
Reset
Value
Circuit
Type
Input D-4
be configured by software.
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
P4.0–P4.3
P5.0–P5.3
I 4-bit input port. 1-bit and 4-bit read and
test are possible.
Pull-up resistors can be configured by
software.
I 4-bit input port.
1-bit and 4-bit read and test are possible
Pull-up resistors can be configured by
software.
I/O 4-bit I/O ports. N-channel open-drain
output up to 5 V. 1-bit and 4-bit read,
1
2
3
4
5
6
7
8
21–24
25–28
–
–
FMF
AMF
ADC0
ADC1
ADC2
ADC3
–
–
Input A-4
A-4
B-4
B-4
Input F-13
Input E-2
write, and test are possible. Ports 4 and
5 can be paired to support 8-bit data.
Pull-up resistors can be configured by
software.
P6.0
P6.1
P6.2
P6.3
I/O 1-bit and 4-bit read, write, and test are
possible. Each pin can be specified as
input or output port. Pull-up resistors can
be configured by software.
29
30
31
32
BUZ
KS0
KS1
KS2
Input D-2
D-4
D-4
D-4
SEG0–SEG19 O LCD segment signal output 60–41 – Output H-16
P8.0–P8.3
P9.0–P9.3
O 4-bit output ports. 1-bit and 4-bit write
and test are possible. Ports 8 and 9 can
33–36
37–40
SEG27–
SEG20
Output H-16
be paired to support 8-bit data.
COM0–COM3 O LCD common signal output 64–61 – Output H-16
V
V
X
DD
SS
OUT
, X
IN
– Main power supply 9 – – –
– Main ground 10 – – –
– Crystal, ceramic, or RC oscillator pins for
11,12 – – –
main system clock. (For external clock
input, use XIN and input XIN's reverse
XT
OUT
, XT
phase to X
IN
– Crystal oscillator pin for a subsystem
clock. (For external clock input, use XT
OUT
)
15,14 – – –
IN
and input XTIN's reverse phase to
XT
)
OUT
1-5
Page 6
PRODUCT OVERVIEW S3C7324/P7324
Table 1-1. S3P7324 Pin Descriptions (Continued)
Pin Name Pin
Type
SEG20–SEG27 O LCD segment signal output 40–33 P9.0–P9.3
Description Number Share
Pin
Reset
Value
Circuit
Type
Output H-16
P8.0–P8.3
ADC0–ADC3 I ADC input ports 5–8 P3.0–P3.3 Input F-13
FMF
AMF
INT4 I External interrupt input with detection of
I External FM/AM frequency inputs 3
20 P1.3 Input A-4
P2.2
4
P2.3
Input B-4
rising or falling edges.
INT2 I Quasi-interrupt with detection of rising
19 P1.2 Input A-4
edge signals.
INT1
INT0
I External interrupt. The triggering edges
for INT0 and INT1 are able to be
18
17
P1.1
P1.0
Input A-4
selected. Only INT0 is synchronized with
the system clock.
BUZ O 2, 4, 8, or 16 kHz frequency output for
29 P6.0 Input D-2
buzzer sound with 4.19 MHz main
system clock.
KS0–KS2 I Quasi-interrupt input with falling edge
30–32 P6.1–P6.3 Input D-4
detection.
RESET
TEST – System test pin(must be connected to
I System reset signal 16 – Input B
13 – – –
V
SS)
NOTE: Pull-up resistors for all I/O ports automatically disabled if they are configured to output mode.
1-6
Page 7
S3C7324/P7324 PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
V
DD
V
P-CHANNEL
IN
DD
Figure 1-3. Pin Circuit Type A
V
DD
Pull-up
Enable
In
N-CHNNEL
IN
Figure 1-5. Pin Circuit Type B
Type A
Feedback
Enable
Pull-down
Enable
Figure 1-4. Pin Circuit Type A-4
Figure 1-6. Pin Circuit Type B-4
1-7
Page 8
PRODUCT OVERVIEW S3C7324/P7324
V
DD
V
DD
Pull-up
Data
Enable
Output
Disable
Figure 1-7. Pin Circuit Type C
V
DD
Pull-up
Enable
Data
Output
Disable
Circuit
TYPE C
I/O
Out
Data
Output
Disable
Data
Output
Circuit
TYPE C
Disable
Figure 1-9. Pin Circuit Type D-4
V
DD
PNE
V
DD
I/O
Pull-up
Enable
I/O
1-8
Figure 1-8. Pin Circuit Type D-2
Figure 1-10. Pin Circuit Type E-2
Page 9
S3C7324/P7324 PRODUCT OVERVIEW
V
DD
Pull-up Enable
Data
ADCEN
ADC Select
To ADC
Figure 1-11. Pin Circuit Type F-13
In
1-9
Page 10
PRODUCT OVERVIEW S3C7324/P7324
V
DD
V
LC0
V
LC1
SEG/COM
and Port Data
V
LC2
Figure 1-12. Pin Circuit Type H-16
Out
1-10
Page 11
S3C7324/P7324 ELECTRICAL DATA
15 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7324 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at X
— Clock timing measurement at XT
— Input timing for RESET
— Input timing for external interrupts
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
IN
IN
15-1
Page 12
ELECTRICAL DATA S3C7324/P7324
Table 15-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter Symbol Conditions Rating Units
Supply Voltage
Input Voltage
Output Voltage
Output Current High
V
DD
V
I
V
IN
O
OH
All I/O ports
One I/O port active – 15 mA
– – 0.3 to + 6.5 V
– 0.3 to V
–
– 0.3 to VDD + 0.3
DD
+ 0.3
All I/O ports active – 30
Output Current Low
I
OL
One I/O port active + 30 (Peak value)
(note)
+ 15
Total value for ports 1, 4, 5 and 6 + 100 (Peak value)
(note)
+ 60
Operating Temperature
Storage Temperature
T
A
T
stg
– – 40 to + 85
– – 65 to + 150
°
C
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value × Duty .
Table 15-2. D.C. Electrical Characteristics
(T
= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Units
Input high
voltage
V
IH1
All input pins except those
specified below
V
IH2
P1, P3, RESET, P2.0−1 and
0.7 V
0.8 V
DD
DD
–
V
DD
V
DD
P6.1−3
Input low
voltage
V
IH3
V
IL1
V
IL2
XIN, X
, XTIN, and XT
OUT
OUT
All input pins except those
specified below
P1, P3, RESET, P2.0−1 and
V
– 0.1 V
DD
– –
DD
0.3 V
0.2 V
DD
DD
P6.1−3
Output high
voltage
V
V
OH1
IL3
XIN, X
, XTIN, and XT
OUT
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
OUT
0.1
V
DD
– 1.0
– – V
Ports 1, 4, 5, and 6
V
OH2
VDD = 4.5 V to 5.5 V
V
– 2.0
DD
IOH = –100 µA Port 8 and 9
V
V
15-2
Page 13
S3C7324/P7324 ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (Continued)
(T
= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Units
Output low
voltage
V
OL1
V
= 4.5 V to 5.5 V
DD
IOL = 15 mA, Ports 1, 4, 5, and 6
– 0.4 2 V
Input high
leakage
current
(note)
Input low
leakage
current
(note)
Output high
leakage
current
(note)
Output low
leakage
current
(note)
Pull-up
resistor
V
OL2
I
LIH1
I
LIL1
I
LOH1
I
LOL
R
R
L1
L2
V
= 4.5 V to 5.5 V
DD
IOL = 100 µA ; Ports 8and 9
VIN = V
DD
All input pins
V
= 0 V
IN
All input pins
V
= V
OUT
DD
All output pins
V
= 0 V
OUT
All output pins
V
= 0 V; V
IN
DD
= 5 V
Ports 1, 2, 3, 4, 5, and 6
V
= 3 V
DD
V
= 0 V; V
IN
RESET
V
= 3 V
DD
DD
= 5 V
– – 1
– – 3
– – – 3
– – 3
– 3
20 40 80
30 95 200
100 230 400
200 480 800
µA
KΩ
NOTE: Except for XIN, X
, XTIN, and XT
OUT
OUT
15-3
Page 14
ELECTRICAL DATA S3C7324/P7324
Table 15-2. D.C. Electrical Characteristics (Continued)
(T
= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Units
LCD voltage
dividing
R
LCD
TA = 25 øC
60 84 130
KΩ
resistor
COM output
impedance
R
COM
VDD = 5 V
VDD = 3 V
−
3 6
5 15
SEG output
impedance
COM output
voltage
deviation
SEG output
voltage
deviation
Oscillator
feedback
resistor
R
SEG
VDD = 5 V
VDD = 3 V
VDC VDD = 5 V (VLC0-COMi)
Io = ± 15uA (I = 0–3)
VDS
VDD = 5 V (VLC0-SEGi)
Io = ± 15uA (I = 0–27)
R
R
OSC1
OSC2
V
= 5.0 V; TA = 25; XIN = VDD,
DD
X
= 0 V
OUT
V
= 5.0 V; TA = 25; XTIN = VDD,
DD
XT
= 0 V
OUT
– 3 6
5 15
–
–
± 45 ± 90
± 45 ± 90
300 600 1500
1230 2630 4000
mV
KΩ
15-4
Page 15
S3C7324/P7324 ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (Concluded)
(T
= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Units
Supply
Current
(1)
I
DD1
Main operating:
FC enable
4.19 MHz – 5.2 10 mA
PCON = 0011B, SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
(2)
I
DD2
Main operating:
PCON = 0011B, SCMOD = 0000B
6.0 MHz – 3.5 8
4.19 MHz 2.5 5.5
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
I
DD3
I
DD4
I
DD5
IDD6
I
DD7
V
= 3 V ± 10%
DD
(2)
Main idle mode
PCON = 0111B, SCMOD =0000B
(3)
:
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
V
= 3 V ± 10%
DD
(2)
Sub operating mode:
PCON = 0011B, SCMOD = 1001B
V
= 3 V ± 10%
DD
32 kHz crystal oscillator
(2)
Sub idle mode:
PCON = 0111B, SCMOD = 1001B
V
= 3 V ± 10%
DD
32 kHz crystal oscillator
(2)
Stop mode:
CPU = fxt/4, SCMOD = 1101B
VDD = 5 V ± 10%
(2)
Stop mode:
CPU = fx/4, SCMOD = 0100B
VDD = 5 V ± 10%
6.0 MHz 1.6 4
4.19 MHz 1.2 3
6.0 MHz – 1.0 2.5
4.19 MHz 0.9 2.0
6.0 MHz 0.5 1.0
4.19 MHz 0.4 0.8
– 15 30 uA
– 6 15
– 0.5 3
–
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors.
2. AMF or FMF is a normal input mode.
3. Data includes the power consumption for sub-system clock oscillation.
15-5
Page 16
ELECTRICAL DATA S3C7324/P7324
Table 15-3. Main System Clock Oscillator Characteristics
(T
= – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
A
Oscillator Clock
Configuration
Ceramic
X
INXOUT
Oscillator
C1 C2
Crystal
Oscillator
External
XINX
C1 C2
X
IN
OUT
X
Clock
OUT
Parameter Test Condition Min Typ Max Units
Oscillation frequency
(1)
Stabilization time
(2)
Stabilization occurs
– 0.4 – 6.0 MHz
– – 4 ms
when VDD is equal to
the minimum oscillator
voltage range.
Oscillation frequency
(1)
Stabilization time
(2)
XIN input frequency
VDD = 2.7 V to 5.5 V
V
DD
(1)
– 0.4 – 6.0 MHz
– – 10 ms
= 1.8 V to 2.7 V
– – 30
– 0.4 – 6.0 MHz
XIN input high and low
– 83.3 – – ns
level width (tXH, tXL)
RC
X
X
IN
OUT
Frequency
(1)
Oscillator
R
NOTES:
1. Oscillation frequency and X
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
15-6
input frequency data are for oscillator characteristics only.
IN
VDD = 5 V
R = 15 KΩ, VDD = 5 V
R = 25 KΩ, VDD = 3 V
0.4
−
2.0
1.0
2.5 MHz
Page 17
S3C7324/P7324 ELECTRICAL DATA
Table 15-4. Subsystem Clock Oscillator Characteristics
(T
= – 40 °C + 85 °C, V
A
= 1.8 V to 5.5 V)
DD
Oscillator Clock
Parameter Test Condition Min Typ Max Units
Configuration
Crystal
XTINXT
OUT
Oscillator
C1 C2
External
XTINXT
Clock
NOTES:
1. Oscillation frequency and XT
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
Oscillation frequency
(1)
Stabilization time
OUT
XTIN input frequency
(1)
XTIN input high and
low level width (t
t
)
XTH
input frequency data are for oscillator characteristics only.
IN
(2)
XTL
– 32 32.768 35 kHz
V
= 2.7 V to 5.5 V
DD
V
= 1.8 V to 2.7 V
DD
– 1.0 2 s
– – 10
– 32 – 100 kHz
– 5 – 15
,
µs
15-7
Page 18
ELECTRICAL DATA S3C7324/P7324
Table 15-5. Input/Output Capacitance
(TA = 25 °C, V
DD
= 0 V )
Parameter Symbol Condition Min Typ Max Units
Input
capacitance
Output
C
C
OUT
IN
f
= 1 MHz; Unmeasured
CLK
pins are returned to V
– – 15 pF
SS
– – 15 pF
capacitance
I/O capacitance
C
IO
– – 15 pF
Table 15-6. A.C. Electrical Characteristics
(T
= – 40 °C to + 85 °C, V
A
= 1.8 V to 5.5 V)
DD
Parameter Symbol Conditions Min Typ Max Units
Instruction cycle
(1)
time
Interrupt input
t
INTH
t
CY
, t
V
= 2.7 V to 5.5 V
DD
VDD = 1.8 V to 5.5 V
INT0
INTL
0.67 – 64
1.3 64
(2)
– –
high, low width INT1, INT2, INT4, KS0–KS2 10
RESET Input Low
t
RSL
Input 10 – –
Width
µs
µs
µs
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
2. Minimum value for INT0 is based on a clock of 2t
or 128/fxx as assigned by the IMOD0 register setting.
CY
Table 15-6. A.C. Electrical Characteristics (continued)
(T
= – 10 °C to + 70 °C, V
A
= 3.5 V to 5.5 V)
DD
Parameter Symbol Conditions Min Typ Max Units
A/D converting
– – 8 8 8 bits
Resolution
Absolute accuracy – – – –
AD conversion
t
CON
– 17
34/fxx
(note)
± 2
–
LSB
time
Analog input
V
IAN
–
V
SS
–
V
DD
voltage
Analog input
R
AN
– 2 1000 –
impedance
NOTE: fxx stands for the system clock (fx or fxt).
µs
V
MΩ
15-8
Page 19
S3C7324/P7324 ELECTRICAL DATA
Table 15-6. A.C. Electrical Characteristics (continued)
(T
= – 40 °C to + 85 °C, V
A
= 3.0 V to 5.5 V)
DD
Parameter Symbol Conditions Min Typ Max Units
Input voltage
(peak to peak)
Frequency
V
f
AMF
f
FMF
IN
AMF/FMF mode, sine
0.3 –
wave input
AMF mode, sine wave
input; VIN = 300mV
P-P
FMF mode, sine wave
input; VIN = 300mV
P-P
0.5 – 10 MHz
30 150
V
DD
V
CPU CLOCK
1.5 MHz
1.0475 MHz
750 kHz
500 kHz
250 kHz
15.6 kHz
Main OSC. Freq.
6 MHz
4.19 MHz
3 MHz
400 kHz
1
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
When FC operates, operating voltage range is 3.0 V to 5.5 V.
2 3 4 5 6 7
SUPPLY VOLTAGE (V)
Figure 15-1. Standard Operating Voltage Range
Table 15-7. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter Symbol Conditions Min Typ Max Unit
Data retention supply voltage
Data retention supply current
V
DDDR
I
DDDR
Normal operation 1.8 – 5.5 V
V
DDDR
= 1.8 V
– 0.1 1
µA
15-9
Page 20
ELECTRICAL DATA S3C7324/P7324
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
V
DD
RESET
V
DD
STOP MODE
DATA RETENTION MODE
V
EXECUTION OF
STOP INSTRUCTION
DDDR
t
SREL
Figure 15-2. Stop Mode Release Timing When Initiated by RESETRESET
IDLE MODE
STOP MODE
DATA RETENTION MODE
IDLE MODE
t
WAIT
NORMAL
OPERATING
MODE
OPERATING
MODE
15-10
V
EXECUTION OF
DDDR
STOP INSTRUCTION
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
t
SREL
t
WAIT
Figure 15-3. Stop Mode Release Timing When Initiated by an Interrupt Request
Page 21
S3C7324/P7324 ELECTRICAL DATA
0.8 V
0.2 V
DD
DD
MEASUREMENT
POINTS
0.8 V
0.2 V
DD
DD
Figure 15-4. A.C. Timing Measurement Points (Except for Xin and XTin)
1 / f
x
t
XL
X
in
t
XH
V
DD
0.1 V
– 0.1 V
XT
Figure 15-5. Clock Timing Measurement at X
1 / f
xt
t
XTL
in
t
Figure 15-6. Clock Timing Measurement at XT
XTH
in
in
V
DD
0.1 V
– 0.1 V
15-11
Page 22
ELECTRICAL DATA S3C7324/P7324
t
RSL
RESET
0.2 V
DD
Figure 15-7. Input Timing for RESETRESET Signal
INT0, 1, 2, 4
KS0 to KS2
t
INTL
0.8 V
0.2 V
DD
DD
t
INTH
Figure 15-8. Input Timing for External Interrupts and Quasi-Interrupts
15-12
Page 23
S3C7324/P7324 MECHANICAL DATA
16 MECHANICAL DATA
OVERVIEW
The S3C7324 microcontroller is available in a 64-pin QFP package (Samsung: 64-QFP-1420F).
Package dimensions are shown in Figure 16-1.
23.90 ± 0.3
14.00 ± 0.2
17.90 ± 0.3
#64
1.00
#1
20.00 ± 0.2
64-QFP-1420F
+0.10
0.40
- 0.05
± 0.15MAX
(1.00)
(1.00
0-8°
+0.10
0.15
- 0.05
0.10 MAX
0.80 ± 0.20
)
0.05~0.25
2.65 ± 0.10
3.00 MAX
NOTE: Dimensions are in millimeters.
Figure 16-1. 64-QFP-1420F Package Dimensions
0.80 ± 0.20
16-1
Page 24
S3C7324/P7324 S3P7324 OTP
17 S3P7324 OTP
OVERVIEW
The S3P7324 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C7324microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial
data format.
The S3P7324 is fully compatible with the S3C7324, both in function and in pin configuration. Because of its
simple programming requirements, the S3P7324 is ideal for use as an evaluation chip for the S3C7324.
17-1
Page 25
S3P7324 OTP S3C7324/P7324
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
64
63
62
61
60
59
58
57
56
55
54
53
52
P2. 0
P2.1
P2.2/FMF
P2.3/AMF
P3.0/ADC0
P3.1/ADC1
SDAT/P3.2/ADC2
SCLK /P3.3/ADC3
VDD/VDD
VSS/VSS
X
OUT
XIN
VPP/TEST
XTIN
XT
RESETRESET /RESET
OUT
P1.0/INT0
P1.1/INT1
P1.2/INT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
(Top View)
21
22
23
S3P7324
24
25
26
27
28
29
30
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
31
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
P9.3/ SEG20
P9.2/ SEG21
P9.1/SEG22
P9.0/ SEG23
P8.3/ SEG24
P8.2/ SEG25
P8.1/SEG26
P8.0/ SEG27
32
P4.0
P4.1
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
P6.1/KS0
P6.2/KS1
P1.3/INT4
P6.0/BUZ
P6.3/KS2
Figure 17-1. S3P7324 Pin Assignments (64-QFP)
17-2
Page 26
S3C7324/P7324 S3P7324 OTP
Table 17-1. Pin Descriptions Used to Read/Write the EPROM
Main Chip During Programming
Pin Name Pin Name Pin No. I/O Function
P3.2 SDAT 7 I/O Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input or push-pull output port.
P3.3 SCLK 8 I/O Serial clock pin. Input only pin.
V
TEST
PP
(TEST)
13 I Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
RESET RESET
V
DD
/ V
SS
VDD / V
SS
16 I Chip initialization
9/10 I
Logic power supply pin. VDD should be tied to +5
V during programming.
Table 17-2. Comparison of S3P7324 and S3C7324 Features
Characteristic S3P7324 S3C7324
Program Memory 4K bytes EPROM 4K bytes mask ROM
Operating Voltage (VDD)
OTP Programming Mode
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
VDD = 5 V, VPP (TEST) = 12.5 V
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
–
Pin Configuration 64 QFP 64 QFP
EPROM Programmability User Program 1 time Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the S3P7324, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 17-3 below.
Table 17-3. Operating Mode Selection Criteria
V
DD
V
PP
(TEST)
REG/
MEM
Address
(A15-A0)
R/WW
Mode
5 V 5 V 0 0000H 1 EPROM read
12.5 V 0 0000H 0 EPROM program
12.5 V 0 0000H 1 EPROM verify
12.5 V 1 0E3FH 0 EPROM read protection
NOTE: "0" means low level; "1" means high level.
17-3
Page 27
S3P7324 OTP S3C7324/P7324
Table 17-4. D.C. Electrical Characteristics
(T
= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Units
Input high
voltage
V
IH1
All input pins except those
specified below
V
IH2
P1, P3, RESET, P2.0−1 and
0.7 V
0.8 V
DD
DD
–
V
DD
V
DD
V
P6.1−3
Input low
voltage
V
IH3
V
IL1
V
IL2
XIN, X
, XTIN, and XT
OUT
OUT
All input pins except those
specified below
P1, P3, RESET, P2.0−1 and
V
– 0.1 V
DD
– –
DD
0.3 V
0.2 V
DD
DD
V
P6.1−3
Output high
voltage
V
V
OH1
IL3
XIN, X
, XTIN, and XT
OUT
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
OUT
0.1
V
DD
– 1.0
– – V
Ports 1, 4, 5, and 6
V
OH2
VDD = 4.5 V to 5.5 V
V
– 2.0
DD
IOH = –100 µA Port 8 and 9
17-4
Page 28
S3C7324/P7324 S3P7324 OTP
Table 17-4. D.C. Electrical Characteristics (Continued)
(T
= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Units
Output low
voltage
V
OL1
V
= 4.5 V to 5.5 V
DD
IOL = 15 mA, Ports 1, 4, 5, and 6
– 0.4 2 V
Input high
leakage
current
(note)
Input low
leakage
current
(note)
Output high
leakage
current
(note)
Output low
leakage
current
(note)
Pull-up
resistor
V
OL2
I
LIH1
I
LIL1
I
LOH1
I
LOL
R
R
L1
L2
V
= 4.5 V to 5.5 V
DD
IOL = 100 µA ; Ports 8 and 9
VIN = V
DD
All input pins
V
= 0 V
IN
All input pins
V
= V
OUT
DD
All output pins
V
= 0 V
OUT
All output pins
V
= 0 V; V
IN
DD
= 5 V
Ports 1, 2, 3, 4, 5, and 6
V
= 3 V
DD
V
= 0 V; V
IN
RESET
V
= 3 V
DD
DD
= 5 V
– – 1
– – 3
– – – 3
– – 3
– – – 3
20 40 80
30 95 200
100 230 400
200 480 800
µA
KΩ
NOTE: Except for XIN, X
, XTIN, and XT
OUT
OUT
17-5
Page 29
S3P7324 OTP S3C7324/P7324
Table 17-4. D.C. Electrical Characteristics (Continued)
(T
= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Units
LCD voltage
dividing
R
LCD
TA = 25 øC
60 84 130
KΩ
resistor
COM output
impedance
R
COM
VDD = 5 V
VDD = 3 V
−
3 6
5 15
SEG output
impedance
COM output
voltage
deviation
SEG output
voltage
deviation
Oscillator
feedback
resistor
R
VDC
VDS
R
R
SEG
OSC1
OSC2
VDD = 5 V
VDD = 3 V
VDD = 5 V (VLC0-COMi)
Io = ± 15uA (I = 0–3)
VDD = 5 V (VLC0-SEGi)
Io = ± 15uA (I = 0–27)
V
= 5.0 V; TA = 25; XIN = VDD,
DD
X
= 0 V
OUT
V
= 5.0 V; TA = 25; XTIN = VDD,
DD
XT
OUT
= 0 V
– 3 6
5 15
–
–
± 45 ± 90
± 45 ± 90
300 600 1500
1230 2630 4000
mV
KΩ
17-6
Page 30
S3C7324/P7324 S3P7324 OTP
Table 17-4. D.C. Electrical Characteristics (Concluded)
(T
= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Units
Supply
Current
(1)
I
DD1
Main operating:
FC enable
4.19 MHz – 5.2 10 mA
PCON = 0011B, SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
(2)
I
DD2
Main operating:
PCON = 0011B, SCMOD = 0000B
6.0 MHz – 3.5 8
4.19 MHz 2.5 5.5
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
I
DD3
I
DD4
I
DD5
IDD6
V
= 3 V ± 10%
DD
(2)
Main idle mode
PCON = 0111B, SCMOD =0000B
(3)
:
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
V
= 3 V ± 10%
DD
(2)
Sub operating mode:
PCON = 0011B, SCMOD = 1001B
V
= 3 V ± 10%
DD
32 kHz crystal oscillator
(2)
Sub idle mode:
PCON = 0111B, SCMOD = 1001B
V
= 3 V ± 10%
DD
32 kHz crystal oscillator
(2)
Stop mode:
CPU = fxt/4, SCMOD = 1101B
VDD = 5 V ± 10%
6.0 MHz 1.6 4
4.19 MHz 1.2 3
6.0 MHz – 1.0 2.5
4.19 MHz 0.9 2.0
6.0 MHz 0.5 1.0
4.19 MHz 0.4 0.8
– 15 30 uA
– 6 15
– 0.5 3
(2)
I
DD7
Stop mode:
CPU = fx/4, SCMOD = 0100B
–
VDD = 5 V ± 10%
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors.
2. AMF or FMF is a normal input mode.
3. Data includes the power consumption for sub-system clock oscillation.
17-7
Page 31
S3P7324 OTP S3C7324/P7324
Table 17-5. Main System Clock Oscillator Characteristics
(T
= – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
A
Oscillator Clock
Configuration
Ceramic
X
INXOUT
Oscillator
C1 C2
Crystal
XINX
OUT
Oscillator
C1 C2
External
IN
X
X
Clock
OUT
Parameter Test Condition Min Typ Max Units
Oscillation frequency
(1)
Stabilization time
(2)
Stabilization occurs
– 0.4 – 6.0 MHz
– – 4 ms
when VDD is equal to
the minimum oscillator
voltage range.
Oscillation frequency
(1)
Stabilization time
(2)
XIN input frequency
VDD = 2.7 V to 5.5 V
V
DD
(1)
– 0.4 – 6.0 MHz
– – 10 ms
= 1.8 V to 2.7 V
– – 30
– 0.4 – 6.0 MHz
XIN input high and low
– 83.3 – – ns
level width (tXH, tXL)
RC
Oscillator
NOTES:
1. Oscillation frequency and X
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
17-8
X
X
IN
OUT
R
Frequency
input frequency data are for oscillator characteristics only.
IN
(1)
VDD = 5 V
R = 15 KΩ, VDD = 5 V
R = 25 KΩ, VDD = 3 V
0.4
−
2.0
1.0
2.5 MHz
Page 32
S3C7324/P7324 S3P7324 OTP
Table 17-6. Subsystem Clock Oscillator Characteristics
(T
= – 40 °C + 85 °C, V
A
= 1.8 V to 5.5 V)
DD
Oscillator Clock
Parameter Test Condition Min Typ Max Units
Configuration
Crystal
XTINXT
OUT
Oscillator
C1 C2
External
XTINXT
Clock
NOTES:
1. Oscillation frequency and XT
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
Oscillation frequency
(1)
Stabilization time
OUT
XTIN input frequency
(1)
XTIN input high and
low level width (t
t
)
XTH
input frequency data are for oscillator characteristics only.
IN
(2)
XTL
– 32 32.768 35 kHz
V
= 2.7 V to 5.5 V
DD
V
= 1.8 V to 2.7 V
DD
– 1.0 2 s
– – 10
– 32 – 100 kHz
– 5 – 15
,
µs
17-9
Page 33
S3P7324 OTP S3C7324/P7324
Table 17-7. Input/Output Capacitance
(TA = 25 °C, V
DD
= 0 V )
Parameter Symbol Condition Min Typ Max Units
Input
capacitance
Output
C
C
OUT
IN
f
= 1 MHz; Unmeasured
CLK
pins are returned to V
– – 15 pF
SS
– – 15 pF
capacitance
I/O capacitance
C
IO
– – 15 pF
Table 17-8. A.C. Electrical Characteristics
(T
= – 40 °C to + 85 °C, V
A
= 1.8 V to 5.5 V)
DD
Parameter Symbol Conditions Min Typ Max Units
Instruction cycle
(1)
time
Interrupt input
t
INTH
t
CY
, t
V
= 2.7 V to 5.5 V
DD
VDD = 1.8 V to 5.5 V
INT0
INTL
0.67 – 64
1.3 64
(2)
– –
high, low width INT1, INT2, INT4, KS0–KS2 10
RESET Input Low
t
RSL
Input 10 – –
Width
µs
µs
µs
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
2. Minimum value for INT0 is based on a clock of 2t
or 128/fxx as assigned by the IMOD0 register setting.
CY
Table 17-8. A.C. Electrical Characteristics (continued)
(T
= – 10 °C to + 70 °C, V
A
= 3.5 V to 5.5 V)
DD
Parameter Symbol Conditions Min Typ Max Units
A/D converting
– – 8 8 8 bits
Resolution
Absolute accuracy – – – –
AD conversion
t
CON
– 17
34/fxx
(note)
± 2
–
time
Analog input
V
IAN
–
V
SS
–
V
DD
voltage
Analog input
R
AN
– 2 1000 –
impedance
NOTE: fxx stands for the system clock (fx or fxt).
LSB
µs
V
MΩ
17-10
Page 34
S3C7324/P7324 S3P7324 OTP
Table 17-8. A.C. Electrical Characteristics (continued)
(T
= – 40 °C to + 85 °C, V
A
= 3.0 V to 5.5 V)
DD
Parameter Symbol Conditions Min Typ Max Units
Input voltage
(peak to peak)
Frequency
V
f
AMF
f
FMF
IN
AMF/FMF mode, sine
0.3 –
wave input
AMF mode, sine wave
input; VIN = 300mV
P-P
FMF mode, sine wave
input; VIN = 300mV
P-P
0.5 – 10 MHz
30 150
V
DD
V
CPU CLOCK
1.5 MHz
1.0475 MHz
750 kHz
500 kHz
250 kHz
15.6 kHz
Main OSC. Freq.
6 MHz
4.19 MHz
3 MHz
400 kHz
1
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
When FC operates, operating voltage range is 3.0 V to 5.5 V.
2 3 4 5 6 7
SUPPLY VOLTAGE (V)
Figure 17-2. Standard Operating Voltage Range
Table 17-9. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter Symbol Conditions Min Typ Max Unit
Data retention supply voltage
Data retention supply current
V
DDDR
I
DDDR
Normal operation 1.8 – 5.5 V
V
DDDR
= 1.8 V
– 0.1 1
µA
17-11
Page 35
S3P7324 OTP S3C7324/P7324
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
V
DD
RESET
V
DD
STOP MODE
DATA RETENTION MODE
V
EXECUTION OF
STOP INSTRUCTION
DDDR
t
SREL
Figure 17-3. Stop Mode Release Timing When Initiated by RESETRESET
IDLE MODE
STOP MODE
DATA RETENTION MODE
IDLE MODE
t
WAIT
NORMAL
OPERATING
MODE
OPERATING
MODE
17-12
V
EXECUTION OF
DDDR
STOP INSTRUCTION
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
t
SREL
t
WAIT
Figure 17-4. Stop Mode Release Timing When Initiated by an Interrupt Request
Page 36
S3C7324/P7324 S3P7324 OTP
0.8 V
0.2 V
DD
DD
MEASUREMENT
POINTS
0.8 V
0.2 V
DD
DD
Figure 17-5. A.C. Timing Measurement Points (Except for Xin and XTin)
1 / f
x
t
XL
X
in
t
XH
V
DD
0.1 V
– 0.1 V
XT
Figure 17-6. Clock Timing Measurement at X
1 / f
xt
t
XTL
in
t
Figure 17-7. Clock Timing Measurement at XT
XTH
in
in
V
DD
0.1 V
– 0.1 V
17-13
Page 37
S3P7324 OTP S3C7324/P7324
t
RSL
RESET
0.2 V
DD
Figure 17-8. Input Timing for RESETRESET Signal
INT0, 1, 2, 4
KS0 to KS2
t
INTL
0.8 V
0.2 V
DD
DD
t
INTH
Figure 17-9. Input Timing for External Interrupts and Quasi-Interrupts
17-14
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