Datasheet S3C72N4, S3C72N2, S3P72N4 Datasheet (Samsung)

S3C72N2/C72N4/P72N4 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

With features such as, LCD direct drive capability, 8-bit timer/counter, and watch timer, the S3C72N2/C72N4
offers an excellent design solution for a wide variety of applications that require LCD functions.

Up to 16 pins of the 64-pin QFP package, it can be dedicated to I/O. Four vectored interrupts provide fast
response to internal and external events. In addition, the S3C72N2/C72N4 's advanced CMOS technology
provides for low power consumption and a wide operating voltage range.

OTP

The S3C72N2/C72N4 microcontroller is also available in OTP (One Time Programmable) version, S3P72N4 .
The S3P72N4 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM.
The S3P72N4 is comparable to S3C72N2/C72N4, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW S3C72N2/C72N4/P72N4

FEATURES

Memory

— 288 × 4-bit RAM
— 2048 × 8-bit ROM (S3C72N2)
— 4096 × 8-bit ROM (S3C72N4)

I/O Pins

— Input only: 4 pins
— I/O: 12 pins
— Output: 8 pins sharing with segment driver

outputs

LCD Controller/Driver

— Maximum 16-digit LCD direct drive capability
— 32 segment, 4 common pins
— Display modes: Static, 1/2 duty (1/2 bias)

1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)

8-Bit Basic Timer

— Programmable interval timer

Interrupts

— Two internal vectored interrupts
— Two external vectored interrupts
— Two quasi-interrupts

Memory-Mapped I/O Structure

— Data memory bank 15

Two Power-Down Modes

— Idle mode (only CPU clock stops)
— Stop mode (main or sub system oscillation stops)

Oscillation Sources

— Crystal, ceramic, or RC for main system clock
— Crystal or external oscillator for subsystem clock
— Main system clock frequency: 4.19 MHz (typical)
— Subsystem clock frequency: 32.768 kHz
— CPU clock divider circuit (by 4, 8, or 64)

— Watchdog timer

8-Bit Timer/Counter

— Programmable 8-bit timer
— External event counter
— Arbitrary clock frequency output

Watch Timer

— Real-time and interval time measurement
— Four frequency outputs to BUZ pin
— Clock source generation for LCD

Bit Sequential Carrier

— Support 16-bit serial data transfer in arbitrary

format

Instruction Execution Times

— 0.95, 1.91, 15.3 µs at 4.19 MHz (main)
— 122 µs at 32.768 kHz (subsystem)

Operating Temperature

— – 40 °C to 85 °C

Operating Voltage Range

— 2.0 V to 5.5 V at 4.19 MHz
— 1.8 V to 5.5 V at 3 MHz

Package Type

— 64-pin QFP

1-2

S3C72N2/C72N4/P72N4 PRODUCT OVERVIEW

BLOCK DIAGRAM

P1.3/TCL0

P2.0/TCLO0

P6.0-P6.3/

KS0-KS3

P8.0-P8.7

SEG24-SEG31

INT0, INT1, INT2

8-Bit Timer/

Counter0

I/O Port 6

Output Port 8

Watchdog

Timer

RESET

Interrupt

Control

Xin

XTin

Interrupt

Control

Block

Internal

Interrupts

Instruction Decoder

Arithmetic

and

Logic Unit

288 x 4-Bit

Data Memory

XTout

Block

Xout

Basic

Timer

Instruction

2/4 KByte

Program

Memory

Watch

Timer

Register

Program

Counter

Program

Status

Word

Stack

Pointer

P2.3/BUZ

LCD

Driver/

Controller

Input

Port 1

I/O Port 2

I/O Port 3

BIAS
VLC0-VLC2
LCDCK/P3.0
LCDSY/P3.1
COM0-COM3
SEG0-SEG23

P8.0-P8.7/
SEG24-SEG31

P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/TCL0

P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ

P3.0/LCDCK
P3.1/LCDSY
P3.2
P3.3

Figure 1-1. S3C72N2/C72N4 Simplified Block Diagram

1-3

PRODUCT OVERVIEW S3C72N2/C72N4/P72N4

PIN ASSIGNMENTS

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

64636261605958575655545352

COM0
COM1
COM2
COM3

BIAS
VLC0
VLC1
VLC2

VDD

VSS

Xout

Xin

TEST

XTin

XTout

RESET

P1.0/INT0
P1.1/INT1
P1.2/INT2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

S3C72N2
S3C72N4

(Top View)

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24/P8.0
SEG25/P8.1
SEG26/P8.2
SEG27/P8.3
SEG28/P8.4
SEG29/P8.5
SEG30/P8.6
SEG31/P8.7

20212223242526272829303132

P2.1

P1.3/TCL0

P2.2/CLO

P2.0/TCLO0

P2.3/BUZ

P3.2

P3.3

P6.0/KS0

P3.1/LCDSY

P3.0/LCDCK

P6.1/KS1

P6.2/KS2

P6.3/KS3

Figure 1-2. S3C72N2/C72N4 64-QFP Pin Assignment

1-4

S3C72N2/C72N4/P72N4 PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. S3C72N2/C72N4 Pin Descriptions

Pin Name Pin

P1.0
P1.1
P1.2
P1.3

P2.0
P2.1
P2.2
P2.3

Type

I 4-bit input port.

1-bit or 4-bit read and test is possible.
4-bit pull-up resistors are software
assignable.

I/O 4-bit I/O port.

1-bit and 4-bit read/write and test is
possible.
4-bit pull-up resistors are software

Description Number Share

Pin

17
18
19
20

21
22
23
24

INT0
INT1
INT2

TCL0

TCLO0

–
CLO
BUZ

Reset
Value

Circuit

Type

Input A-4

Input D

assignable.

P3.0
P3.1
P3.2
P3.3

I/O 4-bit I/O port.

1-bit and 4-bit read/write and test is
possible.
Each individual pin can be specified as

25
26
27
28

LCDCK
LCDSY

Input D

input or output. 4-bit pull-up resistors are
software assignable.

P6.0–P6.3 I/O 4-bit I/O ports. Pins are individually

29–32 KS0–KS3 Input D
software configurable as input or output.
1-bit and 4-bit read/write and test is
possible. 4-bit pull-up resistors are
software assignable.

P8.0–P8.7 O Output port for 1-bit data (for use as

CMOS driver only)

40–33 SEG24–

SEG31

Output H-1

SEG0–SEG23 O LCD segment signal output 64–41 – Output H
SEG24–SEG31 O LCD segment signal output 40–33 P8.0–P8.7 Output H-1
COM0–COM3 O LCD common signal output 1–4 – Output H
V

LC0–VLC2

– LCD power supply.

6–8 – – –

Built-in voltage dividing resistors

BIAS – LCD power control 5 – – –
LCDCK I/O LCD clock output for display expansion 25 P3.0 Input D

1-5

PRODUCT OVERVIEW S3C72N2/C72N4/P72N4

Table 1-1. S3C72N2/C72N4 Pin Descriptions (Continued)

Pin Name Pin

Type

LCDSY I/O LCD synchronization clock output for

Description Number Share

Pin

26 P3.1 Input D

Reset
Value

Circuit

Type

LCD display expansion
TCL0 I External clock input for timer/counter 0 20 P1.3 Input A-4
TCLO0 I/O Timer/counter 0 clock output 21 P2.0 Input D
INT0

INT1

I External interrupt. The triggering edge for

INT0 and INT1 is selectable. Only INT0 is

17
18

P1.0
P1.1

Input A-4

synchronized with the system clock.
INT2 I Quasi-interrupt with detection of rising

19 P1.2 Input A-4

edge signals.
KS0–KS3 I/O Quasi-interrupt input with falling edge

29–32 P6.0–P6.3 Input D

detection.
CLO I/O CPU clock output 23 P2.2 Input D
BUZ I/O 2, 4, 8 or 16 kHz frequency output for

24 P2.3 Input D
buzzer sound with 4.19 MHz main system
clock or 32.768 kHz subsystem clock.

X

X

,

IN

OUT

– Crystal, ceramic or RC oscillator pins for

12,11 – – –
main system clock. (For external clock
input, use XIN and input XIN’s reverse

phase to X

XT

XT

,

IN

OUT

– Crystal oscillator pins for subsystem

clock. (For external clock input, use XT
and input XTIN’s reverse phase to XT

V

DD

V

SS

RESET

– Main power supply 9 – – –
– Ground 10 – – –
– Reset signal 16 – Input B

TEST – Test signal input (must be connected to

OUT

)

14,15 – – –

IN

)

OUT

13 – – –

VSS)

NOTE: Pull-up resistors for all I/O ports automatically disabled if they are configured to output mode.

1-6

S3C72N2/C72N4/P72N4 PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

V

DD

P-CHANNEL

IN

N-CHNNEL

Figure 1-3. Pin Circuit Type A

V

DD

PULL-UP
RESISTOR

P-CHANNEL

IN

RESISTOR
ENABLE

DATA

OUTPUT
DISABLE

Figure 1-5. Pin Circuit Type C

RESISTOR

ENABLE

DATA

OUTPUT

DISABLE

CIRCUIT

TYPE C

V

DD

V

DD

PULL-UP
RESISTOR

P-CHANNEL

P-CHANNEL

OUT

N-CHANNEL

I/O

SCHMITT TRIGGER

Figure 1-4. Pin Circuit Type A-4 (P1)

CIRCUIT TYPE A

Figure 1-6. Pin Circuit Type D (P2, P3, and P6)

1-7

PRODUCT OVERVIEW S3C72N2/C72N4/P72N4

V

LC0

V

V

LC1

DD

LCD SEGMENT/
COMMON DATA

V

LC2

OUT

Figure 1-7. Pin Circuit Type H (SEG/COM)

V

DD

V

LC0

IN

SCHMITT TRIGGER

Figure 1-9. Pin Circuit Type B (RESET)

V

LC1

LCD SEGMENT/
& PORT 8 DATA

V

LC2

Figure 1-8. Pin Circuit Type H-1 (P8)

1-8

OUT

S3C72N2/C72N4/P72N4 ELECTRICAL DATA

13 ELECTRICAL DATA

OVERVIEW

In this section, information on S3C72N2/C72N4 electrical characteristics is presented as tables and graphics.
The information is arranged in the following order:

STANDARD ELECTRICAL CHARACTERISTICS

— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range

MISCELLANEOUS TIMING WAVEFORMS

— A.C timing measurement point
— Clock timing measurement at X

— Clock timing measurement at XT
— TCL0 timing

— Input timing for RESET
— Input timing for external interrupts

STOP MODE CHARACTERISTICS AND TIMING WAVEFORMS

— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request

IN

IN

13-1

ELECTRICAL DATA S3C72N2/C72N4/P72N4

Table 13-1. Absolute Maximum Ratings

(TA = 25 °C)

Parameter Symbol Conditions Rating Units

Supply Voltage
Input Voltage
Output Voltage
Output Current High

V

DD

I

V
V

OH

I1
O

All I/O ports

One I/O port active – 15 mA

– – 0.3 to + 6.5 V

– 0.3 to V

DD

+ 0.3

– 0.3 to VDD + 0.3

All I/O ports active – 30

Output Current Low

I

OL

One I/O port active + 30 (Peak value)

(note)

+ 15

Total value for ports 2 and 3 + 60 (Peak value)

(note)

+ 20

Total value for port 6 + 50

(note)

+ 20

Operating Temperature
Storage Temperature

T

A

T

stg

– – 40 to + 85
– – 65 to + 150

°

C

NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value × Duty .

Table 13-2. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Input high
voltage

Input low
voltage

Output high
voltage

V

V

V
V

V
V
V

IH1

IH2
IH3

IL1
IL2
IL3

OH1

All input pins except those
specified below for V

IH2

, V

IH3

Ports 1, 6, and RESET
XIN, X

OUT

, and XT

IN

Ports 2 and 3 – –
Ports 1, 6 and RESET – –
XIN, X

OUT,

and XT

IN

VDD = 4.5 V to 5.5 V
IOH = – 1 mA

0.7 V

0.8 V

V

DD

DD

DD

– 0.1

–

–
–

– – 0.1

V

DD

– 1.0

– – V

V

DD

V

DD

V

DD

0.3 V

0.2 V

DD
DD

Ports 2, 3, 6 and BIAS

V

OH2

VDD = 4.5 V to 5.5 V

V

DD

– 2.0

– –

IOH = –100 µA Port 8 only

V

V

13-2

S3C72N2/C72N4/P72N4 ELECTRICAL DATA

Table 13-2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Output low
voltage

V

OL1

V

= 4.5 V to 5.5 V

DD

IOL = 15 mA, Ports 2, 3, 6

– 0.4 2 V

Input high
leakage
current

Input low
leakage
current

Output high
leakage
current

Output low
leakage
current

Pull-up
resistor

LCD voltage
dividing
resistor

COM output
impedance

V

I

LIH1

I

LIH2

I

LIL1

I

LIL2

I

LOH1

I

LOL

R

R

R

R

COM

OL2

L1

L2

LCD

V

= 4.5 V to 5.5 V

DD

IOL = 100 µA; Port 8 only
VIN = V

DD

All input pins except those
specified below for I

VIN = V
XIN, X

V

= 0 V

IN

DD

OUT

and XT

LIH2

IN

All input pins except XIN, X
and XT

V
XIN, X

V

= 0 V

IN

OUT

OUT

= V

IN

, and XT

DD

IN

All output pins

V

= 0 V

OUT

All output pins

V

= 0 V; V

IN

DD

= 5 V

Ports 1, 2, 3, 6
V

= 3 V

DD

V

= 0 V; V

IN

RESET

V

= 3 V

DD

DD

= 5 V

TA = 25 °C

VDD = 5 V
VDD = 3 V

OUT

– – 1

– – 3

µA

20

– – – 3

,

– 20

– – 3

µA

– 3

25 50 100

KΩ

50 100 200

100 250 400

200 500 800
120 170 220

−

3 6

5 15
SEG output
impedance
COM output

voltage
deviation

R

SEG

VDC

VDD = 5 V
VDD = 3 V
VDD = 5 V (VLC0-COMi)

Io = ± 15uA (i= 0-3)

3 6

5 15

–

± 45 ± 90

mV

13-3

ELECTRICAL DATA S3C72N2/C72N4/P72N4

Table 13-2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

SEG output
voltage
deviation

VDS

VDD = 5 V (VLC0-SEGi)
Io = ± 15uA (i= 0-31)

–

± 45 ± 90

mV

VLC0 Output
voltage
VLC1 Output

voltage
VLC2 Output

voltage

VLC0

VLC1

VLC2

TA = 25 °C

TA = 25 °C

TA = 25 °C

0.6VDD
– 0.2

0.4VDD
– 0.2

0.2VDD
– 0.2

0.6VDD 0.6VDD
+ 0.2

0.4VDD 0.4VDD
+ 0.2

0.2VDD 0.2VDD
+ 0.2

V

13-4

S3C72N2/C72N4/P72N4 ELECTRICAL DATA

Table 13-2. D.C. Electrical Characteristics (Concluded)

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

(2)

Supply
Current

(1)

I

DD1

Main operating:
VDD = 5 V ± 10%

6.0 MHz

4.19 MHz

– 3.5

2.5

8

5.5

mA

CPU = fx/4
SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF

I

DD2

V

= 3 V ± 10%

DD

(2)

Main idle mode;
VDD = 5 V ± 10%

6.0 MHz

4.19 MHz

6.0 MHz

4.19 MHz

– 1

1.6

1.2

0.9

4
3

2.5
2

CPU = fx/4
SCMOD =0000B
Crystal oscillator

C1 = C2 = 22 pF

I

DD3

V

= 3 V ± 10%

DD

Sub operating:
V

= 3 V ± 10%

DD

6.0 MHz

4.19 MHz
– 15 30

0.5

0.4

1.0

0.8
µA

CPU = fxt/4,
SCMOD = 1001B

32 kHz crystal oscillator

I

DD4

Sub idle mode:
V

= 3 V ± 10%

DD

– 6 15

CPU = fxt/4, SCMOD = 1001B
32 kHz crystal oscillator

IDD5

Stop mode:
VDD = 5V ± 10%
CPU=fxt/4, SCMOD = 1101B

(3)

I

DD6

Stop mode:
VDD = 5 V ± 10%

– 0.5 3

CPU = fx/4, SCMOD = 0100B

NOTES:

1. D.C. electrical values for supply current (I
and through LCD voltage dividing resistors.

2. Data includes the power consumption for sub-system clock oscillation.

3. When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The main­ system clock oscillation stops by the STOP instruction.

DD1

to I

) do not include current drawn through internal pull-up resistors

DD6

13-5

ELECTRICAL DATA S3C72N2/C72N4/P72N4

Table 13-3. Main System Clock Oscillator Characteristics

(T

= – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)

A

Oscillator Clock

Configuration

Ceramic

INXOUT

X

Oscillator

C1 C2

Crystal

XINX

Oscillator

C1 C2

External

IN

X

X

Clock

OUT

OUT

Parameter Test Condition Min Typ Max Units

Oscillation frequency

(1)

Stabilization time

(2)

Stabilization occurs

– 0.4 – 6.0 MHz

– – 4 ms

when VDD is equal to
the minimum oscillator

voltage range.

Oscillation frequency

(1)

Stabilization time

(2)

XIN input frequency

VDD = 4.5 V to 5.5 V
V

DD

(1)

– 0.4 – 6.0 MHz

– – 10 ms

= 1.8 V to 4.5 V

– – 30

– 0.4 – 6.0 MHz

XIN input high and low

– 83.3 – – ns

level width (tXH, tXL)

RC
Oscillator

NOTES:

1. Oscillation frequency and X

2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.

13-6

X

X

IN

OUT

R

Frequency

input frequency data are for oscillator characteristics only.

IN

(1)

VDD = 5 V
R = 20 KΩ, VDD = 5 V
R = 39 KΩ, VDD = 3 V

0.4

−

2.0

1.0

2 MHz

S3C72N2/C72N4/P72N4 ELECTRICAL DATA

Oscillation frequency

Table 13-4. Subsystem Clock Oscillator Characteristics

(T

= – 40 °C + 85 °C, V

A

= 1.8 V to 5.5 V)

DD

Oscillator Clock

Parameter Test Condition Min Typ Max Units

Configuration

Crystal
Oscillator

External
Clock

NOTES:

1. Oscillation frequency and XT

2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs.

XTINXT

C1 C2

XTINXT

OUT

OUT

– 32 32.768 35 kHz

(1)

(2)

V

Stabilization time

XTIN input frequency

(1)

XTIN input high and
low level width (t
t

)

XTH

input frequency data are for oscillator characteristics only.

IN

XTL

,

= 4.5 V to 5.5 V

DD

V

= 1.8 V to 4.5 V

DD

– 32 – 100 KHz

– 5 – 15

– 1.0 2 s
– – 10

µs

Table 13-5. Input/Output Capacitance

(TA = 25 °C, V

DD

= 0 V )

Parameter Symbol Condition Min Typ Max Units

C

C

OUT

IN

f = 1 MHz; Unmeasured pins

are returned to V

SS

– – 15 pF

– – 15 pF

Input
capacitance

Output
capacitance

I/O capacitance

C

IO

– – 15 pF

13-7

ELECTRICAL DATA S3C72N2/C72N4/P72N4

Table 13-6. A.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, V

A

= 1.8 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Units

Instruction cycle

(1)

time

t

CY

V

= 2.7 V to 5.5 V

DD

VDD = 1.8 V to 5.5 V

0.67 – 64

0.95 – 64

µs

With subsystem clock (fxt) 114 122 125
TCL0 input
frequency

TCL0 input high,
low width

t

TIH0

f

TI0

, t

VDD = 2.7 V to 5.5 V

VDD = 1.8 V to 5.5 V

TIL0VDD

= 2.7 V to 5.5 V

VDD = 1.8 V to 5.5 V

0 – 1.5 MHz

1 MHz

0.48 – –

1.8

µs

Interrupt input

t

INTH

, t

INTL

INT0

(2)

– –

high, low width INT1, INT2, KS0–KS3 10

RESET Input Low

t

RSL

Input 10 – –
Width

NOTES:

1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source.

2. Minimum value for INT0 is based on a clock of 2t

or 128/fx as assigned by the IMOD0 register setting.

CY

µs

µs

13-8

S3C72N2/C72N4/P72N4 ELECTRICAL DATA

Table 13-7. RAM Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

CPU CLOCK

1.5 MHz

1.0475 MHz
750 kHz

500 kHz

250 kHz

15.6 kHz

1

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)

2 3 4 5 6 7

SUPPLY VOLTAGE (V)

Figure 13-1. Standard Operating Voltage Range

Main OSC. Freq.

6 MHz

4.19 MHz
3 MHz

Parameter Symbol Conditions Min Typ Max Unit

Data retention supply voltage
Data retention supply current
Release signal set time
Oscillator stabilization wait

(1)

time

NOTES:

1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start­up.

2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.

V

DDDR

I

DDDR

t

SREL

t

WAIT

Normal operation 1.5 – 6.5 V
V

Normal operation 0 – –
Released by RESET –
Released by interrupt –

DDDR

= 2.0 V

– 0.1 1

17

2

/ fx

(2)

µA

µs

– ms
–

13-9

ELECTRICAL DATA S3C72N2/C72N4/P72N4

TIMING WAVEFORMS

INTERNAL RESET

OPERATION

V

RESET

V

DD

DD

STOP MODE

DATA RETENTION MODE

V

EXECUTION OF

STOP INSTRUCTION

DDDR

t

SREL

Figure 13-2. Stop Mode Release Timing When Initiated By RESET

IDLE MODE

STOP MODE

DATA RETENTION MODE

IDLE MODE

t

WAIT

NORMAL
OPERATING
MODE

OPERATING
MODE

13-10

V

EXECUTION OF

DDDR

STOP INSTRUCTION

POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)

t

SREL

t

WAIT

Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request

S3C72N2/C72N4/P72N4 ELECTRICAL DATA

0.8 V

0.2 V

DD

DD

MEASUREMENT

POINTS

0.8 V

0.2 V

DD

DD

Figure 13-4. A.C. Timing Measurement Points (Except for Xin and XTin)

1 / f

x

t

XL

X

in

t

XH

V

DD

0.1 V

– 0.1 V

XT

Figure 13-5. Clock Timing Measurement at X

1 / f

xt

t

XTL

in

t

Figure 13-6. Clock Timing Measurement at XT

XTH

in

in

V

DD

0.1 V

– 0.1 V

13-11

ELECTRICAL DATA S3C72N2/C72N4/P72N4

1 / f

TI0

TCL0

RESET

t

TIL0

Figure 13-7. TCL0 Timing

t

RSL

t

TIH0

0.2 V

DD

0.8 V

0.2 V

DD
DD

13-12

Figure 13-8. Input Timing for RESET Signal

INT0, 1, 2, 4
KS0 to KS3

t

INTL

0.8 V

0.2 V

DD
DD

t

INTH

Figure 13-9. Input Timing for External Interrupts and Quasi-Interrupts

S3C72N2/C72N4/P72N4 MECHANICAL DATA

14 MECHANICAL DATA

OVERVIEW

The S3C72N2/C72N4 microcontroller is available in a 64-pin QFP package (Samsung: 64-QFP-1420F).
Package dimensions are shown in Figure 14-1.

23.90 ± 0.3

14.00 ± 0.2

17.90 ± 0.3

#64

1.00

#1

20.00 ± 0.2

64-QFP-1420F

+0.10

0.40

- 0.05

± 0.15MAX

(1.00)

)

(1.00

0-8°

+0.10

0.15

- 0.05

0.10 MAX

0.80 ± 0.20

0.05~0.25

2.65 ± 0.10

3.00 MAX

NOTE: Dimensions are in millimeters.

Figure 14-1. 64-QFP-1420F Package Dimensions

0.80 ± 0.20

S3C72N2/C72N4/P72N4 S3P72N4 OTP

15 S3P72N4 OTP

OVERVIEW

The S3P72N4 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the

S3C72N2/C72N4 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed
by a serial data format.

The S3P72N4 is fully compatible with the S3C72N2/C72N4, both in function and in pin configuration. Because of
its simple programming requirements, the S3P72N4 is ideal for use as an evaluation chip for the S3C72N4.

15-1

S3P72N4 OTP S3C72N2/C72N4/P72N4

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

64636261605958575655545352

COM0
COM1
COM2
COM3

BIAS

VLC0

SDAT/VLC1
SCLK/VLC2

VDD/VDD

VSS/VSS

Xout

Xin

VPP/TEST

XTin

XTout

RESET/RESET

P1.0/INT0
P1.1/INT1
P1.2/INT2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

S3P72N4

(Top View)

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24/P8.0
SEG25/P8.1
SEG26/P8.2
SEG27/P8.3
SEG28/P8.4
SEG29/P8.5
SEG30/P8.6
SEG31/P8.7

20212223242526272829303132

P2.1

P1.3/TCL0

P2.2/CLO

P2.0/TCLO0

P2.3/BUZ

P3.2

P3.3

P6.0/KS0

P3.1/LCDSY

P3.0/LCDCK

P6.1/KS1

P6.2/KS2

P6.3/KS3

Figure 15-1. S3P72N4 Pin Assignments (64-QFP)

15-2

S3C72N2/C72N4/P72N4 S3P72N4 OTP

Table 15-1. Pin Descriptions Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

V

LC1

SDAT 7 I/O Serial data pin. Output port when reading and

input port when writing. Can be assigned as a
Input / push-pull output port.

V

LC2

TEST

SCLK 8 I/O Serial clock pin. Input only pin.

13 I Power supply pin for EPROM cell writing

V

PP

(TEST)

(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)

RESET RESET

V

DD

/ V

SS

VDD / V

SS

16 I Chip initialization

9/10 I

Logic power supply pin. VDD should be tied to
+5 V during programming.

Table 15-2. Comparison of S3P72N4 and S3C72N2/C72N4 Features

Characteristic S3P72N4 S3C72N2/C72N4

Program Memory 4-Kbyte EPROM 2-K / 4-Kbyte mask ROM
Operating Voltage (VDD)

OTP Programming Mode

2.0 V to 5.5 V at 4.19 MHz

1.8 V to 5.5 V at 3 MHz
VDD = 5 V, VPP (TEST) = 12.5 V

2.0 V to 5.5 V at 4.19 MHz

1.8 V to 5.5 V at 3 MHz
–

Pin Configuration 64 QFP 64 QFP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the Vpp (TEST) pin of the S3P72N4, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15-3 below.

Table 15-3. Operating Mode Selection Criteria

V

DD

Vpp

(TEST)

REG/

MEM

Address
(A15-A0)

R/W Mode

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means low level; "1" means high level.

15-3

S3P72N4 OTP S3C72N2/C72N4/P72N4

Table 15-4. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Input high
voltage

Input low
voltage

Output high
voltage

V

V

V
V

V
V
V

IH1

IH2
IH3

IL1
IL2
IL3

OH1

All input pins except those
specified below for V

IH2

, V

IH3

Ports 1, 6, and RESET
XIN, X

OUT

, and XT

IN

Ports 2 and 3 – –
Ports 1, 6 and RESET – –
XIN, X

OUT,

and XT

IN

VDD = 4.5 V to 5.5 V
IOH = – 1 mA

0.7 V

0.8 V

V

DD

DD

DD

– 0.1

–

–
–

– – 0.1

V

DD

– 1.0

– – V

V

DD

V

DD

V

DD

0.3 V

0.2 V

DD
DD

V

V

Ports 2, 3, 6 and BIAS

V

OH2

VDD = 4.5 V to 5.5 V

V

DD

– 2.0

– –

IOH = –100 µA Port 8 only

Output low
voltage

Input high
leakage
current

Input low
leakage
current

Output high
leakage
current

Output low
leakage
current

V

OL1

V

OL2

I

LIH1

I

LIH2

I

LIL1

I

LIL2

I

LOH1

I

LOL

V

= 4.5 V to 5.5 V

DD

IOL = 15 mA, Ports 2, 3, 6
V

= 4.5 V to 5.5 V

DD

IOL = 100 µA; Port 8 only
VIN = V

DD

All input pins except those
specified below for I

VIN = V
XIN, X

V

= 0 V

IN

DD

OUT

and XT

LIH2

IN

All input pins except XIN, X
and XT

V
XIN, X

V

= 0 V

IN

OUT

OUT

= V

IN

, and XT

DD

IN

All output pins

V

= 0 V

OUT

All output pins

OUT

– 0.4 2 V

– – 1

– – 3

µA

– – 20

– – – 3

,

µA

– – – 20

– – 3

µA

– – – 3

15-4

S3C72N2/C72N4/P72N4 S3P72N4 OTP

Table 15-4. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Pull-up
resistor

LCD voltage
dividing

R

L1

R

L2

R

LCD

V

= 0 V; V

IN

DD

Ports 1, 2, 3, 6
V

= 3 V

DD

V

= 0 V; V

IN

RESET

V

= 3 V

DD

DD

TA = 25 °C

= 5 V

= 5 V

25 50 100

50 100 200

100 250 400

200 500 800
120 170 220

KΩ

resistor
COM output

impedance

R

COM

VDD = 5 V
VDD = 3 V

– 3 6

5 15
SEG output
impedance
COM output

voltage
deviation

SEG output
voltage
deviation

VLC0 Output
voltage
VLC1 Output

voltage
VLC2 Output

voltage

R

SEG

VDC

VDS

VLC0

VLC1

VLC2

VDD = 5 V
VDD = 3 V
VDD = 5 V (VLC0-COMi)
Io = ± 15uA (i= 0-3)

VDD = 5 V (VLC0-SEGi)
Io = ± 15uA (i= 0-31)

TA = 25 °C

TA = 25 °C

TA = 25 °C

–

–

0.6VDD

– 0.2

0.4VDD

– 0.2

0.2VDD

– 0.2

3 6

5 15

± 45 ± 90

± 45 ± 90

0.6VDD 0.6VDD
+ 0.2

0.4VDD 0.4VDD
+ 0.2

0.2VDD 0.2VDD
+ 0.2

mV

mV

V

15-5

S3P72N4 OTP S3C72N2/C72N4/P72N4

Table 15-4. D.C. Electrical Characteristics (Concluded)

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

(2)

Supply
Current

(1)

I

DD1

Main operating:
VDD = 5 V ± 10%

6.0 MHz

4.19 MHz

– 3.5

2.5

8

5.5

mA

CPU = fx/4
SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF

I

DD2

V

= 3 V ± 10%

DD

(2)

Main idle mode;
VDD = 5 V ± 10%

6.0 MHz

4.19 MHz

6.0 MHz

4.19 MHz

– 1

1.6

1.2

0.9

4
3

2.5
2

CPU = fx/4
SCMOD =0000B
Crystal oscillator

C1 = C2 = 22 pF

I

DD3

V

= 3 V ± 10%

DD

Sub operating:
V

= 3 V ± 10%

DD

6.0 MHz

4.19 MHz
– 15 30

0.5

0.4

1.0

0.8
µA

CPU = fxt/4,
SCMOD = 1001B

32 kHz crystal oscillator

I

DD4

Sub idle mode:
V

= 3 V ± 10%

DD

– 6 15

CPU = fxt/4, SCMOD = 1001B
32 kHz crystal oscillator

IDD5

Stop mode:
VDD = 5V ± 10%
CPU=fxt/4, SCMOD = 1101B

(3)

I

DD6

Stop mode:
VDD = 5 V ± 10%

– 0.5 3

CPU = fx/4, SCMOD = 0100B

NOTES:

1. D.C. electrical values for supply current (I
and through LCD voltage dividing resistors.

2. Data includes the power consumption for sub-system clock oscillation.

3. When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The main­ system clock oscillation stops by the STOP instruction.

15-6

DD1

to I

) do not include current drawn through internal pull-up resistors

DD6

S3C72N2/C72N4/P72N4 S3P72N4 OTP

CPU CLOCK

1.5 MHz

1.0475 MHz
750 kHz

500 kHz

250 kHz

15.6 kHz

1

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)

2 3 4 5 6 7

SUPPLY VOLTAGE (V)

Figure 15-2. Standard Operating Voltage Range

Main OSC. Freq.

6 MHz

4.19 MHz
3 MHz

15-7

S3P72N4 OTP S3C72N2/C72N4/P72N4

I

OL

(mA)

35.00
V

= 5.5 V

DD

VDD= 4.5 V

3.500/div

V

= 3.3 V

DD

V

= 2.2 V

DD

.0000

.0000 .2000/div

Figure 15-3. Port 2 IOL vs VOL Curve

V

2.000
L (V)

O

15-8