Datasheet S3C72H8, S3P72H8 Datasheet (Samsung)

S3C72H8/P72H8 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

The S3C72H8 single-chip CMOS microcontroller has been designed for very high performance using Samsung's
state-of-the-art 4-bit product development approach, SAM47 (Samsung Arrangeable Microcontrollers). Its main
features are an up-to-13-digit LCD direct drive capability, 2-channel comparator inputs and outputs, and versatile
8-counter/ timers and 16-bit frequency counter. The S3C72H8 gives you an excellent design solution for a variety
of LCD-related applications, specially thermostat control application.

Up to 21 pins of the available 64-pin QFP packages can be dedicated to I/O. And six vectored interrupts provide
fast response to internal and external events.

In addition, the S3C72H8's advanced CMOS technology provides for low power consumption and a wide oper­ating voltage range.

1-1

PRODUCT OVERVIEW S3C72H8/P72H8

FEATURES

Architecture

– SAM47 4-bit CPU core

Memory

– Data Memory: 512 × 4 bits
– Program Memory: 8196 × 8 bits

(Including LCD display RAM)

Memory-Mapped I/O Structure

– Data memory bank 15

Interrupts

– Three internal vectored interrupts
– Three external vectored interrupts
– Two quasi-interrupts

8-Bit Timer/Counter (T0)

– Programmable 8-bit timer
– External event counter
– Arbitrary clock frequency output
– External clock signal divider

16-Bit Frequency Counter (FC)

– a 16-bit binary up-counter
– External event counter
– Gate function control

Watch-Dog TIMER and Basic Timer

LCD Controller/Driver

– 26 segment and 4 common terminals
– Maximum 13-digit LCD direct drive capability
– Display modes: Static, 1/2, 1/3, 1/4 duty
– Voltage regulator and booster (1/3 bias: 1, 2, or

3V, 1/2 bias: 1.5, 3V)

Analog Comparator

– 2 Ch Comparator (Each CnP, CnN, CnOUT pins)

Bit Sequential Carrier

– Support 16-bit serial data transfer in arbitrary

format

I/O Ports

– 21 pins for standard I/O
– 26 pins for LCD segment output
– 4 pins for LCD common output
– Two input pins for external interrupts

Oscillation Sources

– Crystal, ceramic, or RC for main system clock
– Crystal or external oscillator for subsystem clock
– Main system clock frequency: 4.19 MHz (typical)
– Subsystem clock frequency: 32.768 kHz
– CPU clock divider circuit (by 4, 8, or 64 main, and

by 4 for sub clock)

– 8-bit counter + 3-bit counter
– Overflow signal of 8-bit counter makes a basic

timer interrupt. And control the oscillation warm­up time

– Overflow signal of 3-bit counter makes a system

reset

Watch Timer

– Real-time and interval time measurement
– Four frequency outputs to buzzer sound
– Clock source generation for LCD

1-2

Power Down Mode

– Idle mode (only CPU clock stops)
– Stop mode (main or sub-system oscillation stops)

Voltage Level Detector

– VDD level detection circuit (2.2, 2.4, 3, or 4.0V)
– External pin level detect mode

Operating Voltage Range

– 1.8V to 5.5V at 3 MHz
– 2.0V to 5.5V at 4.19 MHz

Package Type

– 64-pin QFP

S3C72H8/P72H8 PRODUCT OVERVIEW

BLOCK DIAGRAM

SCLK

VPP/

XT

Clock

XTIN

OUT

TEST

Block

SDAT

OTP

Voltage

Level

Detector

Instruction

Register

Program

Counter

Program

Status

Word

Stack

Pointer

Two Analog
Comparator

Watch

Timer

Basic
Timer

16-Bit FREQ

Counter

8-Bit

Timer

LCD Driver/

Controller

Voltage
Booster

Watchdog

Timer

FCL
C0OUT
C1OUT

TCL0
TCLO0

COM0-COM3
SEG0-SEG25

CA, CB
VLC0-VLC2

P0.0/ExtRef

P0.1/SDAT
P0.2/SCLK

P2.0/INT0
P2.1/INT1

P2.2/TCL0

P2.3/FCL

P3.0/TCLO0

P3.1/BTCO

P3.2/CLO
P3.3/BUZ

P4.0/C0P

P4.1/C0N
P4.2/C0OUT
P4.3/C1OUT

P5.0/C1P

P5.1/C1N

P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3

I/O Port 0

I/O Port 2

I/O Port 3

I/O Port 4,5

I/O Port 6

INT0, INT1

512 x 4-Bit

Data

Memory

RESET

X

Interrupt

Control

Block

Internal

Interrupts

Instruction Decoder

Arithmetic
Logic Unit

8 K Byte
Program

Memory

XIN

OUT

and

ExtRef CnP

Cn

CnN

OUT

Figure 1-1. S3C72H8 Simplified Block Diagram

1-3

PRODUCT OVERVIEW S3C72H8/P72H8

PIN ASSIGNMENTS

COM0

COM1

COM2

COM3

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

64636261605958575655545352

CA

CB
VLC0
VLC1
VLC2

P0.0/ExtRef

SDAT/P0.1
SCLK/P0.2

VDD/VDD

VSS/VSS

XOUT

XIN

VPP/TEST

XTIN

XTOUT

RESETRESET/RESET

P2.0/INT0
P2.1/INT1

P2.2/TCL0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

S3C72H8

(TOP VIEW)

51
50
43
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
P5.1/C1N
P5.0/C1P

20212223242526272829303132

P2.3/FCL

P3.1/BTCO

P3.0/TCLO0

P6.0/KS0

P3.3/BUZ

P3.2/CLO

P6.1/KS1

P6.2/KS2

P6.3/KS3

P4.0/C0P

P4.1/C0N

P4.2/C0OUT

P4.3PC1OUT

Figure 1-2. S3C72H8 Pin Assignment Diagram

1-4

S3C72H8/P72H8 PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. S3C72H8 Pin Descriptions

Pin Name Pin

Type

P0.0

I/O 3-bit I/O port.
P0.1
P0.2

1-bit and 4-bit read/write and test is possible.
Port 0 is software configurable as input or output. 3-bit

Description Number

(64-QFP)

6
7
8

Share

Pin

ExtRef

–
–

Circuit

Type

D-1

pull-up resistors are software assignable.

P2.0
P2.1
P2.2
P2.3

P3.0
P3.1
P3.2
P3.3

P4.0-P4.3

P5.0-P5.1

I/O 4-bit I/O port.

1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output. 4-bit pull-up resistors are software assignable.

I/O Same as port 2.

Ports 2 and 3 can be addressed by 1, 4, and 8-bit
read/write and test instruction.

I/O 4/2-bit I/O ports. N-channel open-drain or push-pull

output. 1, 4, and 8-bit read/write and test is possible.
Ports 4 and 5 can be paired to support 8-bit data
transfer. Pull-up resistors are assignable to port unit by
software control.

17
18
19
20

21
22
23
24

29-32

33-34

INT0
INT1

TCL0

FCL

TCLO0

BTCO

CLO
BUZ

C0P/
C0N/

C0OUT/

C1OUT

C1P/

D-1

D-1

E-1

C1N

P6.0-P6.3 I/O 4-bit I/O ports. Port 6 pins are individually software

25-28 KS0-KS3 D-1
configurable as input or output. 1-bit and 4-bit read/write
and test is possible. 4-bit pull-up resistors are software
assignable.

BTCO I/O Basic timer clock output 22 P3.1 D-1
CLO I/O CPU clock output 23 P3.2 D-1
BUZ I/O 2, 4, 8 or 16 kHz frequency output for buzzer sound with

24 P3.3 D-1

4.19MHz main-system clock or 32.768 kHz sub-system
clock.

X

OUT

, X

IN

– Crystal, ceramic, or RC oscillator signal for main-

11, 12 – –
system clock. (For external clock input, use XIN and

input XIN’s reverse phase to X

XT
XT

OUT
IN

,

– Crystal oscillator signal for sub-system clock.

(For external clock input, use XTIN and input XTIN’s
reverse phase to XT

OUT

)

INT0, INT1 I/O External interrupts. The triggering edge for INT0 and

OUT

)

14, 15 – –

17, 18 P2.0, P2.1 D-1
Int1 is selectable. Only INT0 is synchronized with the
system clock.

1-5

PRODUCT OVERVIEW S3C72H8/P72H8

Table 1-1. S3C72H8 Pin Descriptions (Continued)

Pin Name Pin

Type

Description Number

(64-QFP)

Share

Pin

Circuit

Type

KS0-KS3 I/O Quasi-interrupt input with falling edge detection 25-28 P6.0-P6.3 D-1
ExtRef I/O External Reference input 6 P0.0 D-1
TCL0 I/O External clock input for timer/counter 0 19 P2.2 D-1
FCL I/O External clock input for frequency counter 20 P2.3 D-1
TCLO0 I/O Timer/counter 0 clock output 21 P3.0 D-1
COM0-COM3 O LCD common signal output 61-64 – H-16
SEG0-SEG25 O LCD segment output 35-60 – H-16
CA, CB – Voltage booster capacitor pins 1, 2 – –
V

LC0-VLC2

Voltage booster output pins (V

–

output, V

is the 2* V

LC1

output, V

LC0

is the regulated

LC0

is the 3* V

LC2

3-5 – –

LC0

output)

C0P, C0N,
C0OUT

I/O Comparator 0 non-inverting input, inverting input and

output. C0Out can be configured as C-MOS push-pull

29-31 P4.0-P4.2 –

or N-Ch open drain output

C1P, C1N,
C1OUT

I/OIComparator 1 non-inverting input, inverting input and

output. C1Out can be configured as C-MOS push-pull

32-34 P4.3-P5.1 –

or N-Ch open drain output

RESET

V

DD

V

SS

TEST –

– Reset signal for chip initialization 16 – B
– Main power supply 9 – –
– Ground 10 – –

Test signal input (must be connected to VSS)

13

V

PP

–

SDAT I/O Serial data for OTP programming 7 P0.1
SCLK I/O Serial clock for OTP programming 8 P0.2
V

PP

– Power supply pin for EPROM cell writing 13 TEST

NOTE: Pull-up resistors for ports 0, 2, 3, and 6 are automatically disabled if they are configured to output mode.

But pull-up resistors for ports 4 and 5 are retained its state even though they are configured to output mode.

1-6

S3C72H8/P72H8 PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

VDD

VDD

P-Channel

In

Data

Output

Disable

N-Channel

Figure 1-3. Pin Circuit Type A

VDD

P-Channel

N-Channel

Out

In

Figure 1-4. Pin Circuit Type B (Reset)

VDD

Pull-up
Resistor

Resistor

Enable

Data

Output

Disable

Input

Disable

Circuit

Type C

P-Cannel

I/O

Figure 1-5. Pin Circuit Type C

Figure 1-6. Pin Circuit Type D-1 (P0, P2, P3, P6)

1-7

PRODUCT OVERVIEW S3C72H8/P72H8

V

DD

Data

Output

Disable

Input

Disable

To Data Bus

To Comparator

VLC2

PNE

V

DD

Figure 1-7. Pin Circuit Type E-1 (P4, P5)

Pull-up

Enable

In/Out

VLC1

SEG/COM

Out

DATA

VLC0

Figure 1-8. Pin Circuit Type H-16 (COM/SEG)

1-8

S3C72H8/P72H8 ELECTRICAL DATA

16 ELECTRICAL DATA

OVERVIEW

In this section, information on S3C72H8 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:

Standard Electrical Characteristics

— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range

Miscellaneous Timing Waveforms

— A.C timing measurement point
— Clock timing measurement at X

— Clock timing measurement at XT
— TCL timing

— Input timing for RESET
— Input timing for external interrupts

Stop Mode Characteristics and Timing Waveforms

— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request

IN

IN

16-1

ELECTRICAL DATA S3C72H8/P72H8

Table 16-1. Absolute Maximum Ratings

(T

= 25 °C)

A

Parameter Symbol Conditions Rating Units

Supply Voltage
Input Voltage
Output Voltage
Output Current High

V

DD

V

IN

V

O

I

OH

All I/O ports
One I/O pin active – 7 mA

– – 0.3 to + 6.5 V
–

– 0.3 to V

DD

+ 0.3

– 0.3 to VDD + 0.3

All I/O ports active – 40

Output Current Low

I

OL

One I/O pin active + 15 mA
Total pin circuit + 60

Operating Temperature
Storage Temperature

T

T

A

STG

– – 40 to + 85
– – 65 to + 150

°

C

Table 16-2. D.C. Electrical Characteristics

(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

Parameter Symbol Conditions Min Typ Max Units

Operation
voltage

V

DD

F

= 6 MHz

OSC

(CPU clock = 1.25 MHz)
F

= 4.19 MHz

OSC

2.7 – 5.5 V

2.0 5.5
(Instruction clock = 1.04 MHz)
F

OSC

= 3 MHz

1.8 5.5
(CPU clock = 0.75 MHz)

Input High
voltage

Input low
voltage

Output high
voltage

V

V
V
V
V
V
V

OH1

IH1
IH2
IH3

IL1
IL2
IL3

P0, P2, P3, P4, P5 and P6

RESET

X

IN

P0, P2, P3, P4, P5 and P6 –

RESET

X

IN

VDD = 5.0V
IOH = – 1 mA

0.8 V

0.85 V

DD

DD

–

VDD-0.1 V

V

DD

– 1.0

– – V

V

DD

V

DD
DD

0.2 V

0.3 V

0.1

DD
DD

All output pins

V

– 0.5

DD

– 0.4 0.5

0.4 1.0

Output low
voltage

V

V

OL1

OL2

IOH = – 100 µA
V

= 5.0 V, IOL = 2 mA

DD

All output pins except V
V

= 5.0 V, IOL = 15 mA

DD

OL2

Ports 2,3, and 4

16-2

S3C72H8/P72H8 ELECTRICAL DATA

Table 16-2. D.C. Electrical Characteristics (Continued)

(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

Parameter Symbol Conditions Min Typ Max Units

Input high
leakage
current

(note)

Input low
leakage
current

(note)

Output high
leakage
current

(note)

Output low
leakage
current

(note)

Pull-up
resistors

I

LIH1

I

LIL1

I

LOH

I

LOL

R

L1

VIN = V

DD

All input pins

V

= V

IN

; All input pins

DD

except RESET
V

= V

OUT

DD

All I/O pins and output pins

V

= 0 V

OUT

All I/O pins and output pins

V

= 0 V, V

IN

DD

= 5 V

TA = 25 °C, Ports 0-6

– – 3 µA

– – – 3

– – 3

– – – 3

25 47 100

KΩ

Oscillator
feed back
resistors

|V

-COMi|

LC1

Voltage Drop
(I = 0-3)

|V

-SEGi|

LC1

Voltage Drop
(I = 0-25)

NOTE: Except XIN, X

R

R

OSC1

R

OSC2

V

V

OUT

L2

DC

DS

V

= 3 V

DD

V

= 0 V; V

IN

TA = 25 °C, RESET
VDD = 5.0 V, TA = 25 °C

XIN = VDD, X

VDD = 5.0 V, TA = 25 °C
XTIN = VDD, XT

-15 uA per common pin

-15 uA per segment pin

, XTIN, XT

OUT

DD

OUT

= 5.0 V

= 0V

= 0V

OUT

50 90 150

150 250 350

400 700 1200

1000 1500 3000

– – 120 mV

– – 120

16-3

ELECTRICAL DATA S3C72H8/P72H8

Table 16-2. D.C. Electrical Characteristics (Continued)

(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

Parameter Symbol Conditions Min Typ Max Units

Supply
Current

(note)

I

DD1

I

DD2

I

DD3

I

DD4

I

DD5

Main operation mode:
V

= 5 V ± 10%, 6-MHz crystal

DD

V

= 5 V ± 10%, 4.19 MHz

DD

V

= 3 V ± 10%, 6-MHz crystal

DD

V

= 3 V ± 10%, 4.19 MHz

DD

Main Idle mode:
V

= 5 V ± 10%, 6-MHz crystal

DD

V

= 5 V ± 10%, 4.19 MHz

DD

V

= 3 V ± 10%, 6-MHz crystal

DD

V

= 3 V ± 10%, 4.19 MHz

DD

Sub operation mode:
V

= 3 V, 32768Hz

DD

Main OSC stop, except IVB, I
Icomp, I

and external load.

LCD

Sub Idle mode;
V

= 3.0, 32768Hz

DD

Main OSC stop, except IVB, I
Icomp, I

and external load.

LCD

Stop mode; Main & Sub
OSC stop, VDD=5 V ± 10%

except I

VD, IVLD,

Icomp and

,

VLD

,

VLD

SCMOD =
0100B
XTIN = 0V-

– 3.5 8 mA

2.5 5.5

1.6 4

1.2 3

– 1.8 3.5

1.4 3.0

0.6 1.2

0.5 1.1

– 15 30 uA

– 6 15

– 0.3 3 uA

external load.
Stop & Sub OSC stop,

VDD = 3 V, except I
I

Lcomp and external

VLD,

VD,

0.1 1

load.

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

I

is LCD controller/driver operating current, IVB is voltage booster current, Icomp is comparator current and I

LCD

is voltage level detector current.

Table 16-3. Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Data retention supply

V

DDDR

1.0 - 5.5 V

voltage
Data retention supply

current

I

DDDR

V

= 1.0 V

DDDR

Stop mode; Main & Sub

- - 1 uA

OSC stop.
except IVB, I

VLD

, I

LCD

and

external load.

16-4

VLD

S3C72H8/P72H8 ELECTRICAL DATA

Table 16-4. Main System Clock Oscillator Characteristics

(T

= – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)

A

Oscillator Clock

Configuration

Ceramic

X

INXOUT

Oscillator

C1 C2

Crystal

XINX

Oscillator

C1 C2

External

X

X

IN

Clock

OUT

OUT

Parameter Test Condition Min Typ Max Units

Oscillation frequency

Stabilization time

(2)

Oscillation frequency

Stabilization time

XIN input frequency

(2)

(1)

(1)

Stabilization occurs
when VDD is equal to

the minimum oscillator
voltage range.

(1)

VDD = 4.5 V to 5.5 V
VDD = 2.0 V to 4.5 V

– 0.4 – 6.0 MHz

– – 4 ms

– 0.4 – 6 MHz

– – 10 ms
– – 30

– 0.4 – 6.0 MHz

XIN input high and low

– 83.3 – – ns

level width (tXH, tXL)

RC

X

X

IN

OUT

Frequency

(1)

Oscillator

R

NOTES:

1. Oscillation frequency and X

2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.

input frequency data are for oscillator characteristics only.

IN

VDD = 5 V
R = 25 K, VDD = 5 V
R = 50 K, VDD = 3 V

0.4 –

2.0

1.0

2.5 MHz

16-5

ELECTRICAL DATA S3C72H8/P72H8

Table 16-5. Subsystem Clock Oscillator Characteristics

(T

= – 40 °C + 85 °C, V

A

= 1.8 V to 5.5 V)

DD

Oscillator Clock

Parameter Test Condition Min Typ Max Units

Configuration

Crystal

XTINXT

OUT

Oscillation frequency

(1)

– 32 32.768 35 kHz

Oscillator

C1 C2

External

XTINXT

OUT

Stabilization time

(2)

XTIN input frequency

VDD = 4.5 V to 5.5 V
VDD = 1.8 V to 4.5 V

(1)

– 1.0 2 s
– – 10

– 32 – 100 kHz

Clock

XTIN input high and low
level width (t

NOTES:

1. Oscillation frequency and XT

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.

input frequency data are for oscillator characteristics only.

IN

XTL

, t

XTH

)

– 5 – 15 us

Table 16-6. A.C. Electrical Characteristics

(TA = – 40 °C to + 85 °C, V

= 1.8 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Units

Instruction cycle

(1)

time
TCL0, FCL input

frequency
TCL0, FCL input
high, low width
Interrupt input

high, low width

RESET Input Low

t

CY

f

TI0, fTI0

t

TIH0, tTIL0

t

FCH, tFCL

t

INTH,

t

INTL

t

RSL

V

= 2.7 V to 5.5 V

DD

V

= 1.8 V to 5.5 V

DD

VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5V
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5 V

0.67 – 64 µs

1.33 – 64
0 – 1.5 MHz

1
150 – – ns
250

INT0 (2) – – µs
INT1, INT2 (KS0-KS3) 10
Input 10 – – µs

Width

NOTES

1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source.

2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.

16-6

S3C72H8/P72H8 ELECTRICAL DATA

CPU Clock

1.5 MHz

1.05 MHz
750 kHz

15.625 kHz

Main OSC Frequency
6 MHz

4.19 MHz
3 MHz

1 2 3 4 5 6 7

1.8 V 2.7 V 5.5 V
Supply Voltage (V)

CPU clock = 1/n x oscillator frequency (n = 4, 8, 64)

Figure 16-1. Standard Operating Voltage Range

0.8 VDD
Measurement

Points

0.2 VDD

0.8 VDD

0.2 VDD

Figure 16-2. A.C Timing Measure Pints (Except for XIN and XTIN)

16-7

ELECTRICAL DATA S3C72H8/P72H8

Internal RESET

Operation

~

~

Stop Mode

Idle Mode

VDD

RESET

VDD

~

~

Execution of

STOP Instrction

Data Retention Mode

VDDDR

tWAIT

tSREL

Figure 16-3. Stop Mode Release Timing When Initiated By RESETRESET

Idle Mode

~

~

~

~

Execution of

STOP Instrction

Stop Mode

Data Retention Mode

VDDDR

tSREL

Normal
Operating
Mode

Operationg Mode

Power-down Mode Terminating Signal
(Interrupt Request)

Figure 16-4.Stop Release Timing When Initiated By Interrupt Request

1/fx

tXHtXL

XIN

Figure 16-5. Clock Timing Measurement at X

IN

tWAIT

VDD - 0.5 V

0.4 V

16-8

S3C72H8/P72H8 ELECTRICAL DATA

1/fxt

tXTHtXTL

XTIN

Figure 16-6. Clock Timing Measurement at XT

tRSL

RESET

Figure 16-7. Input Timing for RESETRESET Signal

tINTHtINTL

VDD - 0.5 V

0.4 V

IN

0.2 VDD

INT0, 1
KS0 to KS3

0.8 VDD

0.2 VDD

Figure 16-8. Input Timing External Interrupt

16-9

S3C72H8/P72H8 MECHANICAL DATA

17 MECHANICAL DATA

OVERVIEW

The S3C72H8/P72H8 microcontroller is available in a 64-pin QFP package (Samsung: 64-QFP-1420F)
Package dimensions are shown in Figure 17-1

23.90

± 0.3

0-8

17.90 ± 0.3

14.00 ± 0.2

#64

1.00

#1

20.00

± 0.2

64-QFP-1420F

0.40+0.10

-0.05

0.15 MAX

(1.00)

(1.00)

+0.10

0.15

-0.05

0.10 MAX

0.80 ± 0.20

0.05-0.25

2.65

± 0.10

3.00 MAX

NOTE

: Dimensions are in millimeters.

Figure 17-1. 64-QFP-1420F Package Dimensions

0.80

± 0.20

17-1

S3C72H8/P72H8 S3P72H8 OTP

18 S3P72H8 OTP

OVERVIEW

The S3P72H8 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72H8

microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data
format.

The S3P72H8 is fully compatible with the S3C72H8, both in function and in pin configuration. Because of its
simple programming requirements, the S3P72H8 is ideal for use as an evaluation chip for the S3C72H8.

18-1

S3P72H8 OTP S3C72H8/P72H8

COM0

COM1

COM2

COM3

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

64636261605958575655545352

CA

CB
VLC0
VLC1
VLC2

P0.0/ExtRef

SDAT/P0.1
SCLK/P0.2

VDD/VDD

VSS/VSS

XOUT

XIN

VPP/TEST

XTIN

XTOUT

RESETRESET/RESET

P2.0/INT0
P2.1/INT1

P2.2/TCL0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

S3P72H8

(TOP VIEW)

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
P5.1/C1N
P5.0/C1P

20212223242526272829303132

FCL/P2.3

BTCO/P3.1

TCLO0/P3.0

KS0/P6.0

BUZ/P3.3

CLO/P3.2

KS1/P6.1

KS2/P6.2

KS3/P6.3

C0P/P4.0

C0N/P4.1

C0OUT/P4.2

C1OUT/P4.3

Figure 18-1. S3P72H8 Pin Assignments

18-2

S3C72H8/P72H8 S3P72H8 OTP

Table 18-1. Pin Descriptions Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P0.1 SDAT 7 I/O Serial data pin. Output port when reading and

input port when writing can be assigned as
Input/push-pull output port respectively.

P0.2 SCLK 8 I/O Serial clock pin. Input only pin.

V

TEST

PP

(TEST)

13 I Power supply pin for EPROM cell writing

(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in

reading mode. (Option)
RESET RESET 16 I Chip initialization
V

DD

/ V

SS

VDD / V

SS

9/10 I

Logic power supply pin. VDD should be tied to

+ 5 V during programming.

Table 18-2. Comparison of S3P72H8 and S3C72H8 Features

Characteristic S3P72H8 S3C72H8

Program Memory 8 K-byte EPROM 8 K-byte mask ROM
Operating Voltage (VDD)

OTP Programming Mode

1.8 V to 5.5 V 1.8 V to 5.5 V
VDD = 5 V, VPP (TEST) = 12.5 V

–

Pin Configuration 64 QFP 64 QFP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP (TEST) pin of the S3P72H8, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 18-3 below.

Table 18-3. Operating Mode Selection Criteria

V

DD

V

PP

(TEST)

REG/

MEMMEM

Address

(A15-A0)

R/WW

Mode

5 V 5 V 0 0000H 1 EPROM read

12.5V 0 0000H 0 EPROM program

12.5V 0 0000H 1 EPROM verify

12.5V 1 0E3FH 0 EPROM read protection

NOTE: "0" means low level; "1" means high level.

18-3

S3P72H8 OTP S3C72H8/P72H8

Table 18-4. D.C. Electrical Characteristics

(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

Parameter Symbol Conditions Min Typ Max Units

Supply
Current

(note)

I

DD1

I

DD2

I

DD3

I

DD4

I

DD5

Main operation mode:
V

= 5 V ± 10%, 6-MHz crystal

DD

V

= 5 V ± 10%, 4.19 MHz

DD

V

= 3 V ± 10%, 6-MHz crystal

DD

V

= 3 V ± 10%, 4.19 MHz

DD

Main Idle mode:
V

= 5 V ± 10%, 6-MHz crystal

DD

V

= 5 V ± 10%, 4.19 MHz

DD

V

= 3 V ± 10%, 6-MHz crystal

DD

V

= 3 V ± 10%, 4.19 MHz

DD

Sub operation mode:
V

= 3 V, 32768Hz

DD

Main OSC stop, except IVB, I
Icomp, I

and external load.

LCD

Sub Idle mode;
V

= 3.0, 32768Hz

DD

Main OSC stop, except IVB, I
Icomp, I

and external load.

LCD

Stop mode; Main & Sub
OSC stop, VDD=5 V ± 10%

except I

VD, IVLD,

Icomp and

,

VLD

,

VLD

SCMOD =
0100B
XTIN = 0V-

– 3.5 8 mA

2.5 5.5

1.6 4

1.2 3

– 1.8 3.5

1.4 3.0

0.6 1.2

0.5 1.1

– 15 30 uA

– 6 15

– 0.3 3 uA

external load.
Stop & Sub OSC stop,

VDD = 3 V, except I
I

Lcomp and external

VLD,

VD,

0.1 1

load.

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

I

is LCD controller/driver operating current, IVB is voltage booster current, Icomp is comparator current, and

LCD

I

is voltage level detector current.

VLD

18-4

S3C72H8/P72H8 S3P72H8 OTP

CPU Clock

1.5 MHz

1.05 MHz
750 kHz

15.625 kHz

Main OSC Frequency
6 MHz

4.19 MHz
3 MHz

1 2 3 4 5 6 7

1.8 V 2.7 V 5.5 V
Supply Voltage (V)

CPU clock = 1/n x oscillator frequency (n = 4, 8, 64)

Figure 18-2. Standard Operating Voltage Range

18-5

S3P72H8 OTP S3C72H8/P72H8

START

Address= First Location

VDD=5V, VPP=12.5V

x = 0

Program One 1ms Pulse

Increment X

FAIL

Device Failed

Verify Byte

YES

x = 10

NO

FAIL

NO

FAIL

Verify 1 Byte

Last Address

V

= VPP= 5 V

DD

Compare All Byte

PASS

Device Passed

Figure 18-3. OTP Programming Algorithm

Increment Address

18-6