Datasheet RFD16N03L Datasheet (Intersil)

RFD16N03L, RFD16N03LSM

Data Sheet April 1999

16A, 30V, 0.025 Ohm, Logic Level,
N-Channel Power MOSFETs

These are N-Channel power MOSFETs manufacturedusing
the MegaFET process. This process, which uses feature
sizes approaching those of LSI circuits, gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switchingregulators,switchingconverters, motor drivers and
relay drivers. This performance is accomplished through a
special gate oxide design which provides full rated
conductance at gate bias in the 3V to 5V range, thereby
facilitating true on-off power control directly from logic level
(5V) integrated circuits.

Formerly developmental type TA49030.

Ordering InformationS

PART NUMBER PACKAGE BRAND

RFD16N03L TO-251AA 16N03L
RFD16N03LSM TO-252AA 16N03L

NOTE: When ordering, use the entire part number. Add the suffix 9A,
toobtain the TO-252AAvariantin tape and reel, e.g. RFD16N03LSM9A.

File Number

Features

• 16A, 30V

DS(ON)

= 0.025Ω

•r

• Temperature Compensating PSPICE™ Model

• Can be Driven Directly from CMOS, NMOS,
and TTL Circuits

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

DRAIN

GATE

4013.2

Packaging

DRAIN

(FLANGE)

SOURCE

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

GATE

GATE

SOURCE

DRAIN
(FLANGE)

6-156

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE™ is a trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFD16N03L, RFD16N03LSM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFD16N03L, RFD16N03LSM UNITS

Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Continuous Drain Current (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

DSS

DGR

GS

DM

AS

D

Refer to Peak Current Curve

D

Derate Above 25oC (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

30 V
30 V

±10 V

16

Figures 6, 16, 17

90

0.606

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

LC-

1. TJ= 25oC to 150oC.

Electrical Specifications T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V
Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance r
Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t
Total Gate Charge Q
Gate Charge at 5V Q
Threshold Gate Charge Q

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance, Junction to Case R
Thermal Resistance, Junction to Ambient R

= 25oC, Unless Otherwise Specified

C

DSS

GS(TH)

DSS

ID = 250µA, VGS = 0V (Figure 13) 30 - - V
VGS = VDS, ID = 250µA (Figure 12) 1 - 2 V
VDS = 30V,

VGS = 0V

GSS

DS(ON)ID

ON

d(ON)

r

d(OFF)

f

OFF

g(TOT)

g(5)

g(TH)

ISS
OSS
RSS

θJC

θJA

VGS = ±10V - - ±100 nA

= 16A, VGS = 5V (Figure 11) - - 0.025 Ω

VDD = 15V, ID≈ 16A,
RL = 0.93Ω, VGS = 5V,
RGS = 5Ω
(Figures 18, 19)

VGS = 0V to 10V VDD = 24V,
VGS = 0V to 5V - 30 36 nC
VGS = 0V to 1V - 1.5 1.8 nC

VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 14)

Figure 3 - - 1.65
TO-251 and TO-252 - - 100

TC = 25oC--1µA
TC = 150oC--50µA

- - 120 ns

-15- ns

-95- ns

-25- ns

-27- ns

- - 80 ns

-5060nC
ID = 16A,
RL = 1.5Ω
I

= 0.6mA

G(REF)

(Figures 15, 20, 21

- 1650 - pF

- 575 - pF

- 200 - pF

o

C/W

o

C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Diode Reverse Recovery Time t

SD

rr

NOTES:

2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%.

3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance curve (Figure 3).

6-157

ISD = 16A - - 1.5 V
ISD = 16A, dISD/dt = 100A/µs--75ns

RFD16N03L, RFD16N03LSM

Typical Performance Curves

Unless Otherwise Specified

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

125

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs

CASE TEMPERATURE

2

1

150

20

15

10

, DRAIN CURRENT (A)

5

D

I

0

25 50 75 100

125

150

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

175

0.5

0.2

0.1

0.1

, NORMALIZED

JC

θ

Z

THERMAL IMPEDANCE

0.05

0.02

0.01
SINGLE PULSE

0.01

-5

10

500

100

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

1

VDS, DRAIN TO SOURCE VOLTAGE (V)

DS(ON)

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-4

10

-3

10

, RECTANGULAR PULSE DURATION (s)

t

1

-2

10

-1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

500

VGS = 10V

100

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

, PEAK CURRENT CAPABILITY (A)

DM

I

10

-5

10

10

VGS = 5V

-4

-3

10

t, PULSE WIDTH (s)

V

DSS

MAX = 30V

10

TC = 25oC

T

= MAX RATED

J

100µs

1ms

10ms
100ms

DC

50

P

DM

t

1

t

2

1/t2

x R

JC

JC

θ

θ

0

10

FOR TEMPERATURES
ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

I = I

175 - T

25

150

TC = 25oC

-2

10

-1

10

+ T

C

1

10

C

0

10

1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

6-158

RFD16N03L, RFD16N03LSM

Typical Performance Curves

200

100

STARTING TJ = 150oC

10

If R = 0

, AVALANCHE CURRENT (A)

tAV = (L)(IAS)/(1.3*RATED BV

AS

I

If R ≠ 0
t

=(L/R)ln[(IAS*R)/(1.3*RATED BV

AV

1

0.001

0.01
tAV, TIME IN AVALANCHE (ms)

DSS

0.1

Unless Otherwise Specified (Continued)

STARTING TJ = 25oC

- VDD)
) +1]

DSS-VDD

1

10

100

100

V

= 10V

GS

75

50

, DRAIN CURRENT (A)

25

D

I

0

0

PULSE DURATION = 250µs, TC = 25oC

1.0
VDS, DRAIN TO SOURCE VOLTAGE (V)

2.0 3.0 5.0

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS

100

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD= 15V

75

50

25

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

I

0

0

VGS, GATE TO SOURCE VOLTAGE (V)

175oC

-55oC

25oC

3.0 4.5 6.0 7.51.5

100

75

50

, DRAIN TO SOURCE

ON RESISTANCE (mΩ)

25

TJ = 25oC

DS(ON)

r

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

0

2.5 3.0 3.5
VGS, GATE TO SOURCE VOLTAGE (V)

4.0

4.0

ID = 32A

ID = 16A

ID = 8A

ID = 2A

4.5

VGS = 5V

VGS = 4.5V

V

= 4V

GS

VGS = 3.5V

VGS = 3V

5.0

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TOSOURCE ON RESISTANCEvs GATE

VOLTAGE AND DRAIN CURRENT

250

VDD = 15V, IDD = 16A, RL = 0.93Ω

200

150

100

SWITCHING TIME (ns)

50

0

010203040

RGS, GATE TO SOURCE RESISTANCE (Ω)

t

r

t

f

t

d(ON)

t

d(OFF)

50

2.0
V

= 5V,

ID = 16A

GS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

6-159

200

RFD16N03L, RFD16N03LSM

Typical Performance Curves

2.0
VGS = VDS,

1.5

1.0

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80 -40 0 40 80 120 160

= 250µA

I

D

TJ, JUNCTION TEMPERATURE (oC)

Unless Otherwise Specified (Continued)

FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

2500

VGS= 0V, f = 1MHz

2000

1500

1000

C, CAPACITANCE (pF)

500

0

0 5 10 15 20

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

C
C
C

ISS
RSS
OSS

= CGS + C

= C

≈ CDS + C

GD

GD

GD

C

C

C

ISS

OSS

RSS

FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

200

2.0
ID = 250µA

1.5

1.0

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
, JUNCTION TEMPERATURE (oC)

T

J

200

FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

30

= BV

V

DD

DSS

24

18

12

6

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

25

I

G(REF)

20

I

G(ACT)

0.75 BV

0.50 BV

0.25 BV

RL = 1.875Ω
I

G(REF)

V

= 5V

GS

t, TIME (s)

DSS

DSS
DSS

= 0.6mA

VDD = BV

I

G(REF)

80

I

G(ACT)

DSS

5

4

3

2

1

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

t

0V

P

AS

R

G

DUT

I

AS

0.01Ω

+

V

DD

-

0

FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

6-160

t

P

I

AS

t

AV

V

DS

V

DD

RFD16N03L, RFD16N03LSM

Test Circuits and Waveforms

V

GS

R

GS

V

GS

(Continued)

V

DS

R

DUT

t

ON

t

d(ON)

t

V

DS

L

+

V

DD

-

V

90%

GS

10%

r

10%

50%

PULSE WIDTH

FIGURE 18. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

V

I

G(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

VGS= 1V

0

Q

g(TOT)

V

DS

Q

g(5)

V

GS

Q

g(TH)

VGS= 5V

t

d(OFF)

90%

t

OFF

50%

t

f

10%

VGS= 10V

90%

I

G(REF)

0

FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS

6-161

PSPICE Electrical Model

.SUBCKT RFD16N03L 2 1 3; rev 12/12/94

CA 12 8 2.55e-9
CB 15 14 2.64e-9
CIN 6 8 1.45e-9

DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 33.3
EDS 14 8 5 8 1

EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1

IT 8 17 1
LDRAIN 2 5 1e-9

LGATE 1 9 3.4e-9
LSOURCE 3 7 3.4e-9

MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 0.14e-3
RGATE 9 20 0.89
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 10.31e-3
RVTO 18 19 RVTOMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

1

RFD16N03L, RFD16N03LSM

10

DPLCAP

-

6

ESG

8

+

RGATEGATE LGATE

EVTO

+

-

18

8

209

RIN CIN

S1A S2A

12 15

13

8

13

CA

+

-

RSCL2

-

14
13

S2BS1B

6
8

VTO

EDSEGS

6

CB

5

51

16
+

+

5
8

-

5

RSCL1

ESCL

RDRAIN

21

MOS1

14

8

DBREAK

EBREAK

MOS2

RSOURCE

11

17
18

RBREAK

+

-

7

IT

LDRAIN

DBODY

LSOURCE

1817

RVTO

19

-

VBAT

+

2

DRAIN

3

SOURCE

VBAT 8 19 DC 1
VTO 21 6 0.583

ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/176,6))}
.MODEL DBDMOD D (IS = 3.61e-13 RS = 5.06e-3 TRS1 = 3.05e-3 TRS2 = 7.57e-6 CJO = 2.16e-9 TT = 2.18e-8)

.MODEL DBKMOD D (RS = 1.66e-1 TRS1 = -2.97e-3 TRS2 = 7.57e-6)
.MODEL DPLCAPMOD D (CJO = 0.96e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 2.313 KP = 53.82 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 8.95e-4 TC2 = -1e-7)
.MODEL RDSMOD RES (TC1 = 3.92e-3 TC2 = 1.29e-5)
.MODEL RSCLMOD RES (TC1 = 2.03e-3 TC2 = 0.45e-5)
.MODEL RVTOMOD RES (TC1 = -2.27e-3 TC2 = -5.75e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.82 VOFF= -2.82)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.82 VOFF= -4.82)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.67 VOFF= 2.33)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.33 VOFF= -2.67)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.

6-162

RFD16N03L, RFD16N03LSM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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6-163

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