Datasheet RFG75N05E Datasheet (Intersil)

RFG75N05E

75A, 50V, 0.008 Ohm, N-Channel Power
MOSFET

These are N-Channel enhancement mode silicon gate
power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a
specified level of energy in the breakdown avalanche mode
of operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching
convertors, motor drivers, relay drivers, and drivers for high
power bipolar switching transistors requiring high speed and
low gate drive power. These types can be operated directly
from integrated circuits.

Formerly developmental type TA09821.

Ordering Information

PART NUMBER PACKAGE BRAND

RFG75N05E TO-247 RFG75N05E

NOTE: When ordering, include the entire part number.

July 1999Data Sheet File Number

Features

• 75A, 50V

DS(ON)

= 0.008Ω

•r

• Electrostatic Discharge Rated

• UIS Rating Curve (Single Pulse)

o

C Operating Temperature

• 175

• Temperature Compensated PSPICE

Symbol

D

G

S

2275.5

®

Model Provided

Packaging

DRAIN

(BOTTOM

SIDE METAL)

JEDEC STYLE TO-247

SOURCE

DRAIN

GATE

4-481

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFG75N05E

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFG75N05E UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

Continuous Drain Current (Current Limited by Package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

D

DM

GS

D

50 V
50 V

75 A
200 A
±20 V
240 W

Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 W/oC

Electrostatic Discharge Rating, MIL-STD-883, Category B(2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

SD

2kV

Single Pulse Avalanche Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to UIS SOA

Curves

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

-55 to 175

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage I
Drain to Source on Resistance (Note 2) r

DS(ON)VGS

Turn On Time t
Turn On Delay Time t

d(ON)

Rise Time t
Turn Off Delay Time t

d(OFF)

Fall Time t
Turn Off Time t
Total Gate Charge

(OFF)

Q

g(TOT)VGS

(Gate to Source + Gate to Drain)
Gate Charge at 10V Q
Threshold Gate Charge Q
Junction to Case R
Junction to Ambient R

DSSVGS

DSS

GSS

(ON)

r

f

g(10)

g(TH)VGS

θJC
θJA

= 0V, ID = 250µA (Figure 9) 50 - - V

= VDS, ID = 250µA (Figure 8) 2.0 - 4.0 V
VDS = Rated BV
VDS = 0.8 x Rated BV

, VGS = 0V - - 1 µA

DSS

, VGS = 0V, TC = 150oC- -25µA

DSS

VGS = ±20V - - ±100 nA

= 10V, ID = 75A (Figure 7) - - 0.008 Ω
VDD= 25V, I

RL = 0.67Ω, RG= 1.67Ω, VGS = 10V,
(Figure 11)

≈ 37.5A,

D

- - 125 ns

-17- ns

-75- ns

-70- ns

-17- ns

- - 125 ns

= 0, 20V VDD = 40V, ID = 75A,

- - 400 nC
RL = 0.53Ω
I

= 3.44mA

VGS = 0, 10V - - 220 nC

G(REF)

(Figure 11)

= 0, 2V - - 15 nC

- - 0.625oC/W

--80oC/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Diode Reverse Recovery Time t

NOTES:

2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.

3. Repetitive pulse: pulse width is limited by maximum junction temperature.

4. Refer to Intersil Application Notes AN9321 and AN9322. See Figure 4.

4-482

ISD= 75A - - 1.5 V

SD

ISD = 75A, dISD/dt = 100A/µs - - 125 ns

rr

RFG75N05E

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

125

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

100

ID MAX CONTINUOUS

150

80

70

60

50

40

30

, DRAIN CURRENT (A)

20

D

I

10

0

25 50 75 100 125 150

T

, CASE TEMPERATURE (oC)

C

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

1000

175

OPERATION IN THIS AREA
MAY BE LIMITED BY r

10

, DRAIN CURRENT (A)

D

I

TC = 25oC
T

= MAX RATED

J

SINGLE PULSE

1

1

VDS, DRAIN TO SOURCE VOLTAGE (V)

DS(ON)

10

FIGURE 3. FORWARD BIAS SAFE OPERATING AREA

200

VGS = 10V

160

120

80

, DRAIN CURRENT (A)

D

I

40

0

VGS = 7.0V

VGS = 6.0V

TC = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS = 5.0V

VGS = 4.0V

1.5 3.0 4.5 6.00 7.5
V

DRAIN TO SOURCE VOLTAGE (V)

DS,

DC

Idm

100

STARTING TJ = 150oC

If R = 0

, AVALANCHE CURRENT (A)

tAV = (L)(IAS)/(1.3 RATED BV

AS

I

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3 RATED BV

AV

2

10

10

tAV, TIME IN AVALANCHE (ms)

STARTING TJ = 25oC

- VDD)

DSS

- VDD) +1]

DSS

1100.01 0.10

FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA

(SINGLE PULSE UIS SOA)

200

VDD > ID x r
PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

160

120

80

40

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

I

0

046102

DS(ON)

VGS, GATE TO SOURCE VOLTAGE (V)

-55oC
25oC

175oC

8

FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS

4-483

RFG75N05E

Typical Performance Curves

3.0
ID = 75A, VGS = 10V

PULSE DURATION = 80µs

2.5

DUTY CYCLE = 0.5% MAX

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-50

FIGURE 7. NORMALIZED DRAIN TOSOURCE ON

2.0

1.5

1.0

0 50 150 200

, JUNCTION TEMPERATURE (oC)

T

J

100

RESISTANCE vs JUNCTION TEMPERATURE

ID = 250µA

Unless Otherwise Specified (Continued)

2.0

1.6

1.2

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.4

0

-50

FIGURE 8. NORMALIZED GATETHRESHOLD VOLTAGE vs

6000

4000

ID = 250µA

V

= V

GS

DS

0 200

T

J

50 100 150

, JUNCTION TEMPERATURE (oC)

JUNCTION TEMPERATURE

C

ISS

C

OSS

VGS = 0V, f = 1MHz
C

= CGS + C
C
C

ISS
RSS
OSS

= C

≈ C

GD
DS

+ C

GD

GD

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

0 150

T

J

50-50

, JUNCTION TEMPERATURE (oC)

100 200

FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

50

40

30

20

10

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

VDD = BV

DSS

I

GREF()

20

------------------------ ­I

G ACT()

DRAIN SOURCE VOLTAGE

GATE SOURCE

VOLTAGE

RL = 0.667Ω
I

= 3.44mA

G(REF)

= 10V

V

GS

VDD = 0.75 BV
VDD = 0.50 BV
VDD = 0.25 BV

t, TIME (µs)

2000

C, CAPACITANCE (pF)

C

RSS

0

0101520

5

V

DRAIN TO SOURCE VOLTAGE (V)

DS,

FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

10

VDD = BV

DSS
DSS
DSS

80

DSS

I

G REF()

------------------------ ­I

GACT()

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

25

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 11. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT

4-484

RFG75N05E

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS

t

P

I

AS

t

AV

V

DS

V

DD

t

ON

t

DS

10%

d(ON)

90%

50%

t

10%

r

PULSE WIDTH

V

DS

V

R

DUT

L

+

V

DD

-

0

V

GS

0

V

GS

R

GS

V

GS

FIGURE 14. SWITCHING TIME TEST CIRCUIT FIGURE 15. RESISTIVE SWITCHING WAVEFORMS

V

I

g(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

VGS= 2V

0

Q

g(TOT)

V

DS

Q

g(10)

V

GS

Q

g(TH)

VGS = 10V

t

d(OFF)

90%

t

OFF

50%

t

f

10%

VGS= 20V

90%

I

g(REF)

0

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM

4-485

RFG75N05E

PSpice Electrical Model

.SUBCKT RFG75N05 2 1 3 ; rev 10/30/90

DPLCAP

10

*Nominal Temperature = 25oC
CA 12 8 8.98e-9
CB 15 14 8.81e-9
Cin 6 8 4.48e-9
DPLCAP 10 5 DPLCAPMOD
Dbody 7 5 DBODYMOD
Dbreak 5 11 DBREAKMOD
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Ebreak 11 7 17 18 58.4
EVTEMP 20 6 18 8 1
IT 8 17 1
Ldrain 2 5 e-10

GATE

1

LGATE

RGATE

9

20

ESG

EVTO

+

18

22

RIN

6
8

+

CIN

Lgate 1 9 5e-9
Lsource 3 7 3e-9
Mos 16 6 8 8 MODMOD
Rbreak 17 18 RBREAKMOD 1
Rdrain 5 16 RSOURCEMOD 3.07e-3
Rgate 9 20 1.2
Rin 6 8 1e9
Rsource 8 7 RSOURCEMOD 2.e-3
RVTEMP 18 19 RVTONEGMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD

S1A

12

S1B

CA

EGS

S2A

15

14

13

8

13

S2B

13

+

6
8

CB

EDS

S2b 13 15 14 13 S2AMOD
Vbat 8 19 DC 1
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.48 VOFF=-0.48)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.48 VOFF=-2.48)
.MODEL S2AMOD VSWITCH (RON=1e=5 ROFF=0.1 VON=-2.25 VOFF=2.75)
.MODEL S2ABMOD VSWITCH (RON=1e-5 ROFF=0.1 VON =2.75 VOFF=-2.25)
.MODEL DBODYMOD D (IS=2.23e-12 RS=249e-3 TRS1=2.5e-3 CJO=7.55e-9 TT=4e-8)
.MODEL DBREAKMOD D (RS=8e-2 TRS1=2.5e-3)
.MODEL DPLCAPMOD D (IS=1e-30 N=10 CJO=2.14e-9)
.MODEL RBREAKMOD RES (TC1=9.5e-4 TC2=-1.17e-6)
.MODEL RSOURCEMOD RES (TC1=5.2e-3 TC2=1.37e-5)
.MODEL RVTONEGMOD RES (TC1=-3.78e-3 TC2=-7.51e-7)
.MODEL MODMOD NMOS (VTO=3.48 N=10 IS=1e-30 KP=78.5 TOX=1 L=1u W1u)
.ENDS

7

LDRAIN

DBODY

LSOURCE

18

RVTEMP

19

VBAT

+

5

DBREAK

EBREAK

RBREAK

17

11

+

17
18

IT

RDRAIN

16

6

MOS

RSOURCE

8

14

+

5
8

8

DRAIN

2

3

SOURCE

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Intersil semiconductor products are sold by description only. Intersil Corporationreserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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4-486

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