Datasheet NDT410EL Datasheet (Fairchild Semiconductor)

NDT410EL N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description Features

August 1996

Power SOT N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior

2.1A 100V. R High density cell design for extremely low R

= 0.25Ω @ VGS = 5V.

DS(ON)

.

High power and current handling capability in a widely used surface mount package.

switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as automotive, DC/DC converters, PWM motor controls, and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.

___________________________________________________________________________________________

D

G

D S

D

G

S

ABSOLUTE MAXIMUM RATINGS T

= 25°C unless otherwise noted

A

Symbol Parameter NDT410EL Units

V

DSS

V

GSS

I

D

Drain-Source Voltage 100 V Gate-Source Voltage 20 V Drain Current - Continuous (Note 1a) 2.1 A

- Pulsed 10

P

D

TJ,T

Maximum Power Dissipation (Note 1a) 3 W

(Note 1b) 1.3 (Note 1c)

Operating and Storage Temperature Range -65 to 150 °C

STG

1.1

THERMAL CHARACTERISTICS

R

θ

R

θ

* Order option J23Z for cropped center drain lead.

Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W

JA

Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W

JC

NDT410EL Rev. B1

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE AVALANCHE RATINGS (Note 2)

W

DSS

I

AR

Single Pulse Drain-Source Avalanche Energy VDD = 50 V, ID = 10A 15 mJ Maximum Drain-Source Avalanche Current 10 A

OFF CHARACTERISTICS

BV I

DSS

I

GSSF

I

GSSR

DSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = 250 µA VDS = 80 V, V

GS

= 0 V

TJ= 55°C Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA Gate - Body Leakage, Reverse

VGS = -20 V, VDS= 0 V

100 V

1 µA

10 µA

-100 nA

ON CHARACTERISTICS (Note 2)

V

R

I g

GS(th)

DS(ON)

D(on)

FS

Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.5 2 V

TJ= 125°C

0.65 1.1 1.5

Static Drain-Source On-Resistance VGS = 5 V, ID = 2.1 A 0.2 0.25

TJ= 125°C

0.37 0.5 On-State Drain Current VGS = 5 V, VDS = 5 V 10 A Forward Transconductance

VDS = 10 V, ID = 2.1 A

6 S

Ω

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance VDS = 25 V, V Output Capacitance 85 pF

f = 1.0 MHz

GS

= 0 V,

528 pF

Reverse Transfer Capacitance 20 pF

SWITCHING CHARACTERISTICS (Note 2)

t t t t Q

Q Q

D(on)

r

D(off)

f

Turn - On Delay Time Turn - On Rise Time 72 120 ns

VDD = 50 V, ID = 2.1 A, V

= 5 V, R

GEN

= 25 Ω

Turn - Off Delay Time 49 80 ns Turn - Off Fall Time 47 80 ns

g

gs

gd

Total Gate Charge Gate-Source Charge 1.5 nC

Gate-Drain Charge 5.6 nC

VDS = 80 V, ID = 2.1 A, VGS = 5 V

9 20 ns

16 nC

10

NDT410EL Rev. B1

ELECTRICAL CHARACTERISTICS (T

TJ−

T

θJA

TJ−

T

θJC+RθCA

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

t

rr

Notes:

1. R design while R

P

D

Typical R

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

Maximum Continuous Drain-Source Diode Forward Current 2.3 A Drain-Source Diode Forward Voltage Reverse Recovery Time

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

(t)

is determined by the user's board design.

CA

θ

A

=

(t)

R

using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

JA

θ

a. 42oC/W when mounted on a 1 in2 pad of 2oz copper. b. 95oC/W when mounted on a 0.04 in2 pad of 2oz copper.

c. 110oC/W when mounted on a 0.006 in2 pad of 2oz copper.

A

2

=

R

(t)

= I

× R

DS(ON)@T

D

(t)

J

1a

VGS = 0 V, IS = 2.3 A

(Note 2)

VGS = 0 V, IS = 2.3 A, dIF/dt = 100A/µs

1b

1c

1.3 V

150 ns

is guaranteed by

JC

θ

NDT410EL Rev. B1

Typical Electrical Characteristics

10

V = 10V

GS

6.0

8

5.0

6

4

2

D

I , DRAIN-SOURCE CURRENT (A)

0

0 1 2 3 4 5 6

4.0

3.5

3.0

V , DRAIN-SOURCE VOLTAGE (V)

DS

2.5

2

V = 3.0V

1.5

1

DS(on)

R , NORMALIZED

DRAIN-SOURCE ON-RESISTANCE

0.5 0 2 4 6 8 10

GS

I , DRAIN CURRENT (A)

D

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with

Gate Voltage and Drain Current.

2.5

I = 2.1A

D

V = 5V

GS

2

1.5

DS(ON)

R , NORMALIZED

1

DRAIN-SOURCE ON-RESISTANCE

0.5

-50 -25 0 25 50 75 100 125 150 175 T , JUNCTION TEMPERATURE (°C)

J

3

V = 5V

GS

T = 125°C

J

2

1

DS(on)

R , NORMALIZED

DRAIN-SOURCE ON-RESISTANCE

0

0 2 4 6 8 10

I , DRAIN CURRENT (A)

D

3.5

25°C

-55°C

4.0

5.0

6.0 10

Figure 3. On-Resistance Variation

with Temperature.

10

V = 10V

DS

8

6

4

D

I , DRAIN CURRENT (A)

2

0

1 2 3 4 5

V , GATE TO SOURCE VOLTAGE (V)

T = -55°C

J

GS

25

125

Figure 4. On-Resistance Variation with Drain

Current and Temperature.

1.2

1.1

1

0.9

0.8

th

0.7

V , NORMALIZED

0.6

GATE-SOURCE THRESHOLD VOLTAGE (V)

0.5

-50 -25 0 25 50 75 100 125 150 175 T , JUNCTION TEMPERATURE (°C)

J

Figure 5. Transfer Characteristics. Figure 6. Gate Threshold Variation with

Temperature.

V = V

DS GS

I = 250µA

D

NDT410EL Rev. B1

Typical Electrical Characteristics (continued)

1.15

I = 250µA

D

1.1

1.05

1

DSS

BV , NORMALIZED

0.95

0.9

DRAIN-SOURCE BREAKDOWN VOLTAGE (V)

-50 -25 0 25 50 75 100 125 150 175 T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Breakdown Voltage Variation with

Temperature.

1300 1000

500 300

200

100

50

CAPACITANCE (pF)

10

f = 1 MHz V = 0V

GS

0.1 0.2 0.5 1 2 5 10 20 50 V , DRAIN TO SOURCE VOLTAGE (V)

DS

C

10

V = 0V

GS

5

T = 125°C

1

J

0.5

0.1

0.05

S

I , REVERSE DRAIN CURRENT (A)

0.01

0.4 0.6 0.8 1 1.2 V , BODY DIODE FORWARD VOLTAGE (V)

SD

25°C

-55°C

Figure 8. Body Diode Forward Voltage

Variation with Current and Temperature.

10

I = 2.1A

iss

C

oss

C

rss

D

8

6

4

2

GS

V , GATE-SOURCE VOLTAGE (V)

0

0 5 10 15 20

Q , GATE CHARGE (nC)

g

V = 20V

DS

50V

80V

Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics.

V

DD

t

V

d(on)

OUT

V

IN

V

IN

V

GS

R

GEN

G

R

L

D

V

OUT

DUT

S

10%

t t

on off

t

r

d(off)

90%

10%

50%

PULSE WIDTH

Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms.

50%

90%

10%

90%

NDT410EL Rev. B1

tt

f

INVERTED

V , DRAIN-SOURCE VOLTAGE (V)

I , DRAIN CURRENT (A)

DS

Typical Electrical and Thermal Characteristics

12

V = 10V

10

FS

g , TRANSCONDUCTANCE (SIEMENS)

DS

8

6

4

2

0

0 2 4 6 8 10

T = -55°C

J

25°C

I , DRAIN CURRENT (A)

D

125°C

Figure 13. Transconductance Variation with Drain

Current and Temperature.

3

2.5

2

1.5

1b

1c

1

4.5"x5" FR-4 Board

o

T = 25 C

0.5

D

I , STEADY-STATE DRAIN CURRENT (A)

0

0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

A

Still Air V = 5V

GS

2

3.5

3

2.5

2

1.5

1b

1c

1

STEADY-STATE POWER DISSIPATION (W)

0.5 0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air

2

1a

Figure 14. SOT-223 Maximum Steady- State Power

Dissipation versus Copper Mounting Pad Area.

20

10

1a

5

2

RDS(ON) Limit

1

0.5

D

0.2

0.1

0.1 0.2 0.5 1 2 5 10 20 50 100 200

V = 5V

GS

SINGLE PULSE

T = 25°C

C

DC

10s

10ms

1s

10µs

100µs

1ms

Figure 15. Maximum Steady-State Drain Current

versus Copper Mounting Pad Area.

1

0.5

D = 0.5

0.2

0.1

0.05

0.02

0.01

0.005

r(t), NORMALIZED EFFECTIVE

0.002

TRANSIENT THERMAL RESISTANCE

0.001

0.05

0.02

0.01

Single Pulse

0.0001 0.001 0.01 0.1 1 10 100 300

Figure 17. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change

depending on the circuit board design.

t , TIME (sec)

1

Figure 16. Maximum Safe

Operating Area.

R (t) = r(t) * R

R = See Note 1 c

P(pk)

T - T = P * R (t)

J

Duty Cycle, D = t / t

JA

θ

JA

θ

t

1

t

2

A

JA

θ

JA

θ

2

1

NDT410EL Rev. B1

SOT-223 Tape and Reel Data and Package Dimensions

SOT-223 Packaging Configuration: Figure 1.0

Customized Label

F63TNR Label

Antistatic Cover Tape

Static Dissipativ e

Embossed Car rier Tape

Packaging Description:

SOT-223 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 2,500 uni t s pe r 13" o r 33 0c m d ia met er reel . Th e reel s ar e dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or 177cm di ameter reel. This and some o ther options are further described in the Packaging Information table.

These full reels are individually barcode labeled and placed inside a standard intermediate box (illustrated in figure 1.0) made of recyclable corrugated brown paper. One box contains two reels maximum. And these boxes are placed inside a barcode labeled shipping box which comes in di ff ere nt siz es depe nd in g on th e num be r of pa rts shippe d.

SOT-223 Packaging Information

Packaging Option Packaging type

Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg)

Note/Comments

Standard

(no flow code)

13" Dia

343x64x343 184x187x47

0.1246 0.1246

0.7250 0.1532

D84Z

TNR

2,500 500

5,000 1,000

TNR

7" Dia

F63TNR Label

184mm x 184mm x 47mm

Pizza Box for D84Z Option

SOT-223 Tape Leader and Trailer Configuration: Figure 2.0

F

014

852

F

014

852

SOT-223 Unit Orientation

343mm x 342mm x 64mm

Intermediate box for Standard

F

014

852

F

014

852

F63TNR Label sample

LOT: CBVK741B019

FSID: PN2222A

D/C1: D9842 QTY1: SPEC REV: D/C2: QTY2: CPN:

F63TNR Label

QTY: 3000

SPEC:

N/F: F (F63TNR)3

Carrier Tape

Cover Tape

Trailer Tape 300mm minimum or 38 empty pockets

Components

Leader Tape 500mm minimum or 62 empty pockets

September 1999, Rev. B

SOT-223 Tape and Reel Data and Package Dimensions, continued

SOT-223 Embossed Carrier Tape Configuration: Figure 3.0

T

K0

Wc

B0

P0

D0

E1

F

W

E2

Tc

A0

D1

P1

User Direction of Feed

Dimensions are in millimeter

Pkg type

SOT-223

(12mm)

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481

SOT-223 Reel Configuration: Figure 4.0

A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc

6.83

7.42

12.0

1.55

1.50

1.75

10.25

+/-0.10

+/-0.3

+/-0.05

+/-0.10

rotational and lateral movement requirements (see sketches A, B, and C).

B0

20 deg maximum component rotation

Sketch A (Side or Front Sectional View)

Component Rotation

5.50

min

+/-0.05

20 deg maximum

A0

Sketch B (Top View)

Component Rotation

W1 Measured at Hub

8.0 +/-0.1

Typical component cavity center line

Typical component center line

Dim A

Max

4.0 +/-0.1

0.292

1.88 +/-0.10

0.5mm maximum

Sketch C (Top View)

Component lateral movement

+/-

0.0130

9.5 +/-0.025

0.5mm maximum

0.06 +/-0.02

Dim A

max

Tape Size

12mm 7" Dia

12mm 13" Dia

Reel

Option

Dim N

Diameter Option

7"

See detail AA

B Min

Dim C

13" Diameter Option

See detail AA

W2 max Measured at Hub

Dim D

W3

min

DETAIL AA

Dimensions are in inches and millimeters

Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)

7.00

0.059

177.8

13.00 330

1.5

0.059

1.5

512 +0.020/- 0.008 13 +0.5/-0.2

0.795

20.2

0.795

20.2

5.906 150

7.00 178

0.488 +0.078/-0.000

12.4 +2/0

0.488 +0.078/-0.000

12.4 +2/0

0.724

18.4

0.724

18.4

0.469 – 0.606

11.9 – 15.4

0.469 – 0.606

11.9 – 15.4

July 1999, Rev. B

SOT-223 Tape and Reel Data and Package Dimensions, continued

SOT-223 (FS PKG Code 47)

1 : 1

Scale 1:1 on letter size paper

Part Weight per unit (gram): 0.1246

September 1999, Rev. C

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ CoolFET™ CROSSVOLT™

2

E

CMOS

TM

FACT™ FACT Quiet Series™

®

FAST FASTr™ GTO™ HiSeC™

ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QFET™ QS™

Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8

TinyLogic™ UHC™ VCX™

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2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or

effectiveness.

PRODUCT STA TUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

Formative or In Design

First Production

Full Production

Not In Production

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.