Datasheet NDS8961 Datasheet (Fairchild Semiconductor)

NDS8961
Dual N-Channel Enhancement Mode Field Effect Transistor

General Description Features

June 1997

SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance.These devices are particularly
suited for low voltage applications such as DC motor control
and DC/DC conversion where fast switching, low in-line power

3.1 A, 30 V. R
R

High density cell design for extremely low R

= 0.1 Ω @ V

DS(ON)

= 0.15 Ω @ V

DS(ON)

= 10 V

GS

= 4.5 V.

GS

.

DS(ON)

High power and current handling capability in a widely used
surface mount package.

Dual MOSFET in surface mount package.

loss, and resistance to transients are needed.

____________________________________________________________________________________________

5

6

7

8

4

3

2

1

Absolute Maximum Ratings T

Symbol Parameter

V

DSS

V

GSS

I

D

Drain-Source Voltage 30 V

Gate-Source Voltage ±20 V

Drain Current - Continuous (Note 1a) 3.1 A

- Pulsed 10

P

D

Power Dissipation for Dual Operation 2 W

Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9

TJ,T

Operating and Storage Temperature Range -55 to 150 °C

STG

THERMAL CHARACTERISTICS

R

JA

θ

R

JC

θ

© 1997 Fairchild Semiconductor Corporation

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W

= 25°C unless otherwise noted

A

NDS8961

NDS8961 Rev.D

Units

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units

OFF CHARACTERISTICS

BV

I

DSS

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current

VDS = 24 V, V

GS

= 0 V

1 µA

TJ = 55oC 10 µA

I

GSSF

I

GSSR

Gate - Body Leakage, Forward

VGS = 20 V, VDS = 0 V

Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA

100 nA

ON CHARACTERISTICS (Note 2)

V

GS(th)

Gate Threshold Voltage

VDS = VGS, ID = 250 µA

1 1.6 3 V

TJ = 125oC 0.7 1.2 2

R

DS(ON)

Static Drain-Source On-Resistance

VGS = 10 V, ID = 3.1 A

0.072 0.1

Ω

TJ = 125oC 0.107 0.18

0.116 0.15

4

I

g

D(on)

VGS = 4.5 V, ID = 2.6 A

On-State Drain Current VGS = 10 V, VDS = 5 V 10 A

VGS = 4.5 V, VDS = 5 V

FS

Forward Transconductance VDS = 10 V, ID = 3.1 A 4.3 S

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 120 pF

VDS= 15 V, VGS = 0 V,
f = 1.0 MHz

Reverse Transfer Capacitance 40 pF

190 pF

SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time VDD = 10 V, ID = 1 A,
Turn - On Rise Time 15 30 ns

VGS = 10 V, R

GEN

= 6 Ω

7 15 ns

Turn - Off Delay Time 14 28 ns
Turn - Off Fall Time 3 6 ns
Total Gate Charge VDS = 10 V,
Gate-Source Charge 1.2 nC

ID = 3.1 A, VGS = 10 V

7.1 10 nC

Gate-Drain Charge 1.9 nC

NDS8961 Rev.D

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

Notes:

1. R

design while R

P

D

Typical R

Scale 1 : 1 on letter size paper.

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

Maximum Continuous Drain-Source Diode Forward Current 1.3 A
Drain-Source Diode Forward Voltage

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

(t)

is determined by the user's board design.

CA

θ

−

T

J

=

R

θJA

for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

JA

θ

a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper.

b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper.

c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper.

−

T

T

T

A

J

A

=

(t)

R

θJC+RθCA

2

= I

(t) ×R

DS(ON ) T

D

(t)

J

1a

VGS = 0 V, IS = 1.3 A (Note 2)

1b

1c

0.79 1.2 V

is guaranteed by

JC

θ

NDS8961 Rev.D

Typical Electrical Characteristics

10

V =10V

GS

8

6

4

2

D

I , DRAIN-SOURCE CURRENT (A)

0

0 0.5 1 1.5 2 2.5 3

6.0

5.0

4.5

4.0

3.5

V , DRAIN-SOURCE VOLTAGE (V)

DS

Figure 1. On-Region Characteristics.

1.8

I = 3.1A

D

1.6

V = 10V

GS

1.4

1.2

1

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

3.0

2.5

V = 3.5V

GS

2

4.0

4.5

1.5

1

DS(on)

DRAIN-SOURCE ON-RESISTANCE

R , NORMALIZED

0.5
0 2 4 6 8 10

5.0

5.5

6.0

I , DRAIN CURRENT (A)

D

7.0

Figure 2. On-Resistance Variation with Gate

Voltage and Drain Current.

2.5

V = 10V

GS

2

T = 125°C

1.5

1

DS(on)

R , NORMALIZED

0.5

DRAIN-SOURCE ON-RESISTANCE

0

0 2 4 6 8 10

J

25°C

-55°C

I , DRAIN CURRENT (A)

D

8.0
10

Figure 3. On-Resistance Variation with

Temperature.

10

V = 10V

DS

8

6

4

D

I , DRAIN CURRENT (A)

2

0

1 2 3 4 5 6

V , GATE TO SOURCE VOLTAGE (V)

GS

T = -55°C

J

25°C

125°C

Figure 5. Transfer Characteristics.

Figure 4. On-Resistance Variation with Drain

Current and Temperature.

1.2

V = V

DS

1.1

1

0.9

0.8

th

V , NORMALIZED

0.7

GATE-SOURCE THRESHOLD VOLTAGE

0.6

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

I = 250µA

D

Figure 6. Gate Threshold Variation with

GS

Temperature.

NDS8961 Rev.D

Typical Electrical Characteristics

1.12

I = 250µA

D

1.08

1.04

1

DSS

BV , NORMALIZED

0.96

DRAIN-SOURCE BREAKDOWN VOLTAGE

0.92

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Breakdown Voltage Variation with

Temperature.

600

400

200

100

70

CAPACITANCE (pF)

50

f = 1 MHz
V = 0V

30

GS

20

0.1 0.2 0.5 1 2 5 10 20 30
V , DRAIN TO SOURCE VOLTAGE (V)

DS

C

C

C

iss

oss

rss

10

5

V =0V

GS

1

0.1

0.01

0.001

S

I , REVERSE DRAIN CURRENT (A)

0.0001
0 0.2 0.4 0.6 0.8 1 1.2

V , BODY DIODE FORWARD VOLTAGE (V)

SD

T = 125°C

J

25°C

-55°C

Figure 8. Body Diode Forward Voltage Variation

with Current and Temperature.

10

I = 3.1A

D

8

6

4

2

GS

V , GATE-SOURCE VOLTAGE (V)

0

0 2 4 6 8

Q , GATE CHARGE (nC)

g

V = 5V

DS

10V

15V

Figure 9. Capacitance Characteristics.

V

DD

V

IN

D

V

GS

R

GEN

G

S

R

L

V

OUT

DUT

Figure 10. Gate Charge Characteristics.

t t

on off

t

V

V

d(on)

OUT

IN

r

90%

10%

50%

t

d(off)

50%

90%

90%

10%

tt

f

INVERTED

10%

PULSE WIDTH

Figure 11. Switching Test Circuit.

NDS8961 Rev.D

Figure 12. Switching Waveforms.

Typical Electrical and Thermal Characteristics

8

V = 10V

DS

6

T = -55°C

J

25°C

4

2

FS

g , TRANSCONDUCTANCE (SIEMENS)

0

0 2 4 6 8 10

I , DRAIN CURRENT (A)

D

125°C

Figure 13. Transconductance Variation with Drain

Current and Temperature.

3.5

3

1b

2.5

1c

2

1.5

D

I , STEADY-STATE DRAIN CURRENT (A)

1

0 0.1 0.2 0.3 0.4 0.5

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air
V = 10V

GS

2

2.5

2

1.5

1b

1

1c

0.5

STEADY-STATE POWER DISSIPATION (W)

0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

Total Power for Dual Operation

1a

Power for Single Operation

4.5"x5" FR-4 Board
T = 25 C

A

Still Air

o

2

Figure 14. SO-8 Dual Package Maximum

Steady-State Power Dissipation versus
Copper Mounting Pad Area.

30

1a

10

5

RDS(ON) LIMIT

1

0.5

V = 10V

0.1

D

I , DRAIN CURRENT (A)

0.05

0.01

GS

SINGLE PULSE

R = See Note 1c

JA

θ

T = 25°C

A

0.1 0.2 0.5 1 2 5 10 20 30 50
V , DRAIN-SOURCE VOLTAGE (V)

DS

10s

DC

100us

1ms

10ms

100ms

1s

Figure 15. Maximum Steady-State Drain

Figure 16. Maximum Safe Operating Area.

Current versus Copper Mounting
Pad Area.

1

0.5

0.2

0.1

0.05

0.02

0.01

0.005

r(t), NORMALIZED EFFECTIVE

0.002

TRANSIENT THERMAL RESISTANCE

0.001

0.0001 0.001 0.01 0.1 1 10 100 300

NDS8961 Rev.D

D = 0.5

0.2

0.1

0.05

0.02

0.01

Single Pulse

t , TIME (sec)

1

Figure 17. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change

depending on the circuit board design.

R (t) = r(t) * R

R = See Note 1c

P(pk)

T - T = P * R (t)

J

Duty Cycle, D = t / t

JA

θ

JA

θ

t

1

t

2

A

JA

θ

JA

θ

2

1

SO-8 Tape and Reel Data and Package Dimensions

SOIC(8lds) Packaging
Configuration: Figure 1.0

ELECTROSTATIC

SENSITIVE DEVICES

DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC
ELECTROMAGNETIC, MAGNETIC OR RADIOACTIVE FIELDS

TNR DATE
PT NUMBER
PEEL STRENGTH MIN ______________gms

Customized
Label

Packaging Option
Packaging type

Qty per Reel/Tube/Bag
Reel Size
Box Dimension (mm)
Max qty per Box
Weight per unit (gm)
Weight per Reel (kg)

Note/Comments

MAX _____________ gms

ESD Label

SOIC (8lds) Packaging Information

Standard

(no flow code)

2,500 95 4,000

13" Dia

343x64x343 530x130x83 343x64x343

5,000 30,000 8,000

0.0774 0.0774 0.0774 0.0774

0.6060 - 0.9696 0.1182

TNR

L86Z F011

Rail/Tube-TNR

13" Dia

Embossed Car rier Tape

Antistatic Cover Tape

Static Dissipative

F63TNR
Label

D84Z

TNR

500

7" Dia

184x18 7x47

1,000

F

NDS

9959

9959

852

SOIC-8 Unit Orientation

343mm x 342mm x 64mm

Stand a r d In t e rm ed iate box

Packaging Description:

SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 uni t s pe r 13" o r 33 0c m d ia met er reel . Th e reel s ar e
dark blue in color and is made of polystyrene plastic (anti­static coated). Other option comes in 500 units per 7" or
177cm di ameter reel. This and some o ther options are
further described in the Packaging Information table.

These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in di ff ere nt siz es depe nd in g on th e num be r of pa rts
shippe d.

F

NDS

9959

F

NDS

9959

F

NDS

852

852

852

F

NDS
9959

852

Pin 1

F63TNR Label sample

LOT: CBVK741B019

FSID: FDS9953A

D/C1: D9842 QTY1: SPEC REV:
D/C2: QTY2: CPN:

QTY: 2500

SPEC:

N/F: F (F63TNR)3

SOIC(8lds) Tape Leader and Trailer
Configuration: Figure 2.0

Carrier Tape

Cover Tape

Trailer Tape
640mm minimum or
80 empty pockets

F63TNLab el

ESD Label

Components

ESD Label

F63TNLabel

Leader Tape
1680mm minimum or
210 empty pockets

July 1999, Rev. B

SO-8 Tape and Reel Data and Package Dimensions, continued

SOIC(8lds) Embossed Carrier Tape
Configuration: Figure 3.0

T

K0

Wc

B0

P0

D0

E1

F

W

E2

Tc

A0

D1

P1

User Direction of Feed

Dimensions are in millimeter

Pkg type

(8lds)

SOIC

(12mm)

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481

rotational and lateral movement requirements (see sketches A, B, and C).

SOIC(8lds) Reel Configuration: Figure 4.0

A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc

6.50

5.30

12.0

1.55

1.60

1.75

10.25

+/-0.10

+/-0.10

20 deg maximum component rotation

Sketch A (Side or Front Sectional View)

Component Rotation

+/-0.3

+/-0.05

+/-0.10

+/-0.10

B0

5.50

min

+/-0.05

20 deg maximum

A0

Sketch B (Top View)

Component Rotation

W1 Measured at Hub

8.0
+/-0.1

Typical
component
cavity
center line

Typical
component
center line

Dim A

Max

4.0
+/-0.1

0.450

2.1
+/-0.10

0.5mm
maximum

Sketch C (Top View)

Component lateral movement

+/-

0.150

9.2
+/-0.3

0.5mm
maximum

0.06
+/-0.02

Dim A

max

Tape Size

12mm 7" Dia

12mm 13" Dia

 1998 Fairchild Semiconductor Corporation

Reel

Option

Dim N

Diameter Option

7"

See detail AA

B Min

Dim C

13" Diameter Option

See detail AA

W2 max Measured at Hub

Dim D

W3

min

DETAIL AA

Dimensions are in inches and millimeters

Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)

7.00

0.059

177.8

13.00
330

1.5

0.059

1.5

512 +0.020/-0.008
13 +0.5/-0.2

512 +0.020/-0.008
13 +0.5/-0.2

0.795

2.165550.488 +0.078/-0.000

20.2

0.795

7.00

20.2

178

12.4 +2/0

0.488 +0.078/-0.000

12.4 +2/0

0.724

18.4

0.724

18.4

0.469 – 0.606

11.9 – 15.4

0.469 – 0.606

11.9 – 15.4

July 1999, Rev. B

SO-8 Tape and Reel Data and Package Dimensions, continued

SOIC-8 (FS PKG Code S1)

1 : 1

Scale 1:1 on letter size paper

Dimensions s how n below are in:

inches [millimeters]

Part Weight per unit (gram): 0.0774

9

September 1998, Rev. A

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PRODUCT STA TUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

Formative or
In Design

First Production

Full Production

Not In Production

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. D