Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description Features
July 1996
These dual N- and P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
notebook computer power management and other battery
powered circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
N-Channel 5.3A, 30V, R
P-Channel -4.0A, -30V, R
High density cell design or extremely low R
=0.035Ω @ V
DS(ON)
=0.065Ω @ V
DS(ON)
GS
GS
DS(ON)
=10V.
=-10V.
.
High power and current handling capability in a widely used
surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward CurrentN-Ch1.3A
P-Ch-1.3
V
SD
t
rr
Notes:
1. R
P
design while R
D
Typical R
Drain-Source Diode Forward
Voltage
VGS = 0 V, IS = 1.3 A
VGS = 0 V, IS = -1.3 A
(Note 2)N-Ch0.91.2V
(Note 2)
P-Ch-0.85-1.2
Reverse Recovery TimeVGS = 0 V, IF = 1.3 A, dIF/dt = 100 A/µsN-Ch100ns
VGS = 0 V, IF = -1.3 A, dIF/dt = 100 A/µs
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
is determined by the user's board design.
CA
θ
T
=
R
θ
T
J−TA
θJA
JA
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper.
1a
J−TA
=
(t)
R
θ
JC
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
Figure 22. P-Channel Transconductance Variation with
Drain Current and Temperature.
NDS8958 Rev. C
Page 8
Typical Thermal Characteristics: N & P-Channel
- V , DRAIN-SOURCE CURRENT (V)
-I , DRAIN CURRENT (A)
2.5
2
1.5
1b
1
1c
0.5
STEADY-STATE POWER DISSIPATION (W)
00.20.40.60.81
2oz COPPER MOUNTING PAD AREA (in )
Total Power for Dual Operation
1a
Power for Single Operation
4.5"x5" FR-4 Board
T = 25 C
A
Still Air
o
2
Figure 23. SO-8 Dual Package Maximum
Steady-State Power Dissipation versus
Copper Mounting Pad Area.
4.5
4
3.5
1b
1c
3
2.5
D
-I , STEADY-STATE DRAIN CURRENT (A)
2
00.10.20.30.40.5
2oz COPPER MOUNTING PAD AREA (in )
4.5"x5" FR-4 Board
o
T = 25 C
A
Still Air
V = -10V
GS
2
6
1a
5
1b
4
1c
3
D
I , STEADY-STATE DRAIN CURRENT (A)
2
00.10.20.30.40.5
2oz COPPER MOUNTING PAD AREA (in )
4.5"x5" FR-4 Board
o
T = 25 C
A
Still Air
V = 10V
GS
2
Figure 24. N-Ch Maximum Steady-State Drain
Current versus Copper Mounting Pad
Area.
50
1a
20
10
RDS(ON) LIMIT
5
1
0.5
V = 10V
GS
0.1
D
I , DRAIN CURRENT (A)
0.05
0.01
SINGLE PULSE
R = See Note 1c
JA
θ
T = 25°C
A
0.10.20.51251030 50
V , DRAIN-SOURCE VOLTAGE (V)
DS
DC
10s
100us
1ms
10ms
100ms
1s
Figure 25. P-Ch Maximum Steady- State
Drain Current versus Copper Mounting
Pad Area.
50
20
10
5
RDS(ON) LIMIT
1
0.5
V = -10V
GS
D
0.1
0.05
0.01
SINGLE PULSE
R = See Note 1c
JA
θ
T = 25°C
A
0.10.20.51251030 50
DS
DC
10s
1ms
10ms
100ms
1s
Figure 27. P-Channel Maximum Safe Operating
Area.
Figure 26. N-Channel Maximum Safe Operating
Area.
100us
NDS8958 Rev. C
Page 9
Typical Thermal Characteristics: N & P-Channel
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
r(t), NORMALIZED EFFECTIVE
0.002
TRANSIENT THERMAL RESISTANCE
0.001
0.00010.0010.010.1110100300
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
t , TIME (sec)
1
Figure 28. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
R (t) = r(t) * R
JA
θ
R = See Note 1c
JA
θ
P(pk)
t
1
t
2
T - T = P * R (t)
J
A
Duty Cycle, D = t / t
JA
θ
JA
θ
2
1
V
DD
t
d(on)
V
IN
V
GS
R
GEN
G
R
L
D
V
OUT
V
OUT
DUT
V
S
IN
10%
tt
onoff
t
r
d(off)
90%
10%
90%
50%
50%
90%
10%
PULSE WIDTH
Figure 29. N or P-Channel Switching Test Circuit.Figure 30. N or P-Channel Switching Waveforms.
tt
f
NDS8958 Rev. C
Page 10
SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging
Configuration: Figure 1.0
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC
ELECTROMAGNETIC, MAGNETIC OR RADIOACTIVE FIELDS
TNR DATE
PT NUMBER
PEEL STRENGTH MIN ______________gms
Customized
Label
Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Reel Size
Box Dimension (mm)
Max qty per Box
Weight per unit (gm)
Weight per Reel (kg)
Note/Comments
MAX _____________ gms
ESD Label
SOIC (8lds) Packaging Information
Standard
(no flow code)
2,500954,000
13" Dia
343x64x343 530x130x83 343x64x343
5,00030,0008,000
0.07740.07740.07740.0774
0.6060-0.96960.1182
TNR
L86ZF011
Rail/Tube-TNR
13" Dia
Embossed Car rier Tape
Antistatic Cover Tape
Static Dissipative
F63TNR
Label
D84Z
TNR
500
7" Dia
184x18 7x47
1,000
F
NDS
9959
9959
852
SOIC-8 Unit Orientation
343mm x 342mm x 64mm
Stand a r d In t e rm ed iate box
Packaging Description:
SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 uni t s pe r 13" o r 33 0c m d ia met er reel . Th e reel s ar e
dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or
177cm di ameter reel. This and some o ther options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in di ff ere nt siz es depe nd in g on th e num be r of pa rts
shippe d.
F
NDS
9959
F
NDS
9959
F
NDS
852
852
852
F
NDS
9959
852
Pin 1
F63TNR Label sample
LOT: CBVK741B019
FSID: FDS9953A
D/C1: D9842 QTY1: SPEC REV:
D/C2: QTY2: CPN:
QTY: 2500
SPEC:
N/F: F (F63TNR)3
SOIC(8lds) Tape Leader and Trailer
Configuration: Figure 2.0
Carrier Tape
Cover Tape
Trailer Tape
640mm minimum or
80 empty pockets
F63TNLab el
ESD Label
Components
ESD Label
F63TNLabel
Leader Tape
1680mm minimum or
210 empty pockets
July 1999, Rev. B
Page 11
SO-8 Tape and Reel Data and Package Dimensions, continued
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
SOIC(8lds) Reel Configuration: Figure 4.0
A0B0WD0D1E1E2FP1P0K0TWcTc
(8lds)
6.50
5.30
12.0
1.55
1.60
1.75
+/-0.10
+/-0.10
+/-0.3
+/-0.05
+/-0.10
+/-0.10
10.25
min
rotational and lateral movement requirements (see sketches A, B, and C).
B0
20 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
Sketch B (Top View)
Component Rotation
W1 Measured at Hub
5.50
+/-0.05
20 deg maximum
A0
8.0
+/-0.1
Typical
component
cavity
center line
Typical
component
center line
Dim A
Max
4.0
+/-0.1
0.450
2.1
+/-0.10
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
+/-
0.150
9.2
+/-0.3
0.5mm
maximum
0.06
+/-0.02
Dim A
max
Tape Size
12mm7" Dia
12mm13" Dia
1998 Fairchild Semiconductor Corporation
Reel
Option
Dim N
Diameter Option
7"
See detail AA
B Min
Dim C
13" Diameter Option
See detail AA
W2 max Measured at Hub
Dim D
W3
min
DETAIL AA
Dimensions are in inches and millimeters
Dim ADim BDim CDim DDim NDim W1Dim W2Dim W3 (LSL-USL)
7.00
0.059
177.8
13.00
330
1.5
0.059
1.5
512 +0.020/- 0.008
13 +0.5/-0.2
512 +0.020/- 0.008
13 +0.5/-0.2
0.795
2.165550.488 +0.078/-0.000
20.2
0.795
7.00
20.2
178
12.4 +2/0
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.724
18.4
0.469 – 0.606
11.9 – 15.4
0.469 – 0.606
11.9 – 15.4
July 1999, Rev. B
Page 12
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1 : 1
Scale 1:1 on letter size paper
Dimen sions show n below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A
Page 13
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
CoolFET™
CROSSVOLT™
2
E
CMOS
TM
FACT™
FACT Quiet Series™
®
FAST
FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STA TUS DEFINITIONS
Definition of Terms
Datasheet IdentificationProduct StatusDefinition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or
In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. D
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.