Datasheet NDS8958 Datasheet (Fairchild Semiconductor)

Page 1
NDS8958
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description Features
July 1996
These dual N- and P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
N-Channel 5.3A, 30V, R P-Channel -4.0A, -30V, R
High density cell design or extremely low R
=0.035 @ V
DS(ON)
=0.065@ V
DS(ON)
GS
GS
DS(ON)
=10V.
=-10V.
.
High power and current handling capability in a widely used surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
________________________________________________________________________________
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter N-Channel P-Channel Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 -30 V
Gate-Source Voltage 20 -20 V
Drain Current - Continuous (Note 1a) 5.3 -4 A
- Pulsed 20 -15
P
D
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6 (Note 1b) 1 (Note 1c) 0.9
TJ,T
Operating and Storage Temperature Range -55 to 150 °C
STG
THERMAL CHARACTERISTICS
R
θ
R
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
JC
NDS8958 Rev. C
Page 2
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Type Min Typ Max Units OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA N-Ch 30 V
VGS = 0 V, ID = -250 µA
Zero Gate Voltage Drain Current VDS = 24 V, V
VDS = -24 V, V
= 0 V N-Ch 1 µA
GS
TJ = 55°C
= 0 V P-Ch -1 µA
GS
TJ = 55°C
P-Ch -30 V
10 µA
-10 µA Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V All 100 nA Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
All -100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage
Static Drain-Source On-Resistance
VDS = VGS, ID = 250 µA
TJ = 125°C
VDS = VGS, ID = -250 µA
TJ = 125°C
VGS = 10 V, ID = 5.3 A
N-Ch 1 1.6 2.8 V
0.7 1.2 2.2
P-Ch -1 -1.6 -2.8
-0.7 -1.2 -2.2
N-Ch 0.033 0.035
TJ = 125°C 0.046 0.063
VGS = 4.5 V, ID = 4.4 A
0.046 0.05
VGS = -10 V, ID = -4.0 A P-Ch 0.052 0.065
TJ = 125°C
0.075 0.13
VGS = -4.5 V, ID = -3.3 A 0.085 0.1
I
D(on)
On-State Drain Current
VGS = 10 V, VDS = 5 V
N-Ch 20 A
VGS = -10 V, VDS = -5 V P-Ch -15
g
FS
Forward Transconductance
VDS = 10 V, ID = 5.3 A
N-Ch 10.5 S
VDS = -10 V, ID = -4.0 A P-Ch 7
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance N-Channel
VDS = 15 V, VGS = 0 V, f = 1.0 MHz
C
oss
C
rss
Output Capacitance N-Ch 370 pF
P-Channel
Reverse Transfer Capacitance N-Ch 250 pF
VDS = -15 V, VGS = 0 V, f = 1.0 MHz
N-Ch 720 pF P-Ch 690
P-Ch 430
P-Ch 160
NDS8958 Rev. C
Page 3
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Type Min Typ Max Units SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
D(on)
r
D(off)
f
Turn - On Delay Time N-Channel
VDD = 10 V, ID = 1 A, V
= 10 V, R
Turn - On Rise Time N-Ch 13 30 ns
GEN
GEN
= 6
P-Channel
Turn - Off Delay Time N-Ch 29 50 ns
VDD = -10 V, ID = -1 A, V
= -10 V, R
GEN
GEN
= 6
N-Ch 12 20 ns P-Ch 9 20
P-Ch 20 25
P-Ch 40 50
Turn - Off Fall Time N-Ch 10 20 ns
P-Ch 19 40
Q
g
Q
gs
Q
gd
Total Gate Charge N-Channel
VDS = 10 V, ID = 5.3 A, VGS = 10 V
N-Ch 19 30 nC P-Ch 21 30
Gate-Source Charge N-Ch 2.2
P-Channel
Gate-Drain Charge N-Ch 5.5
VDS = -10 V, ID = -4.0 A, VGS = -10 V
P-Ch 3.1
P-Ch 5.1
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current N-Ch 1.3 A
P-Ch -1.3
V
SD
t
rr
Notes:
1. R
P
design while R
D
Typical R
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 1.3 A VGS = 0 V, IS = -1.3 A
(Note 2) N-Ch 0.9 1.2 V
(Note 2)
P-Ch -0.85 -1.2
Reverse Recovery Time VGS = 0 V, IF = 1.3 A, dIF/dt = 100 A/µs N-Ch 100 ns
VGS = 0 V, IF = -1.3 A, dIF/dt = 100 A/µs
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
is determined by the user's board design.
CA
θ
T
=
R
θ
T
J−TA
θJA
JA
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper.
1a
J−TA
=
(t)
R
θ
JC
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
2
= I
(t) ×R
DS (ON ) T
D
+R
(t)
θ
CA
J
1b 1c
P-Ch 100
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS8958 Rev. C
Page 4
Typical Electrical Characteristics: N-Channel
25
V =10V
GS
20
15
6.0
5.0
4.5
4.0
2.5
3
2
V = 3.0V
GS
3.5
4.0
3.5
10
5
D
I , DRAIN-SOURCE CURRENT (A)
0
0 0.5 1 1.5 2 2.5 3
V , DRAIN-SOURCE VOLTAGE (V)
DS
3.0
1.5
DS(ON)
R , NORMALIZED
1
DRAIN-SOURCE ON-RESISTANCE
0.5 0 5 10 15 20 25
I , DRAIN CURRENT (A)
D
Figure 1. N-Channel On-Region Characteristic. Figure 2. N-Channel On-Resistance Variation with
Gate Voltage and Drain Current.
1.6
I = 5.3A
D
1.4
V =10V
GS
1.2
1
DS(ON)
R , NORMALIZED
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)
J
2
V = 10V
GS
1.75
1.5
1.25
1
DS(ON)
R , NORMALIZED
0.75
DRAIN-SOURCE ON-RESISTANCE
0.5 0 5 10 15 20 25
I , DRAIN CURRENT (A)
D
T = 125°C
J
4.5
5.0
6.0 10
25°C
-55°C
Figure 3. N-Channel On-Resistance Variation with
Temperature.
25
V = 10V
DS
20
15
10
D
I , DRAIN CURRENT (A)
5
0
1 2 3 4 5 6
V , GATE TO SOURCE VOLTAGE (V)
GS
T = -55°C
J 25°C
125°C
Figure 5. N-Channel Transfer Characteristic.
Figure 4. N-Channel On-Resistance Variation with
Drain Current and Temperature.
1.2
V = V
1.1
1
0.9
th
V , NORMALIZED
0.8
0.7
GATE-SOURCE THRESHOLD VOLTAGE
0.6
-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)
J
DS GS
I = 250µA
D
Figure 6. N-Channel Gate Threshold Variation
with Temperature.
NDS8958 Rev. C
Page 5
Typical Electrical Characteristics: N-Channel (continued)
1.1
I = 250µA
D
1.05
1
DSS
BV , NORMALIZED
0.95
DRAIN-SOURCE BREAKDOWN VOLTAGE
0.9
-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)
J
Figure 7. N-Channel Breakdown Voltage Variation
with Temperature.
2000
1500
1000
500
CAPACITANCE (pF)
200
100
f = 1 MHz V = 0V
GS
0.1 0.2 0.5 1 2 5 10 20 30 V , DRAIN TO SOURCE VOLTAGE (V)
DS
C
C
iss
oss
C
Figure 9. N-Channel Capacitance Characteristics.
rss
25
V =0V
10
GS
1
T = 125°C
J
0.1
0.01
S
I , REVERSE DRAIN CURRENT (A)
0.001
0.2 0.4 0.6 0.8 1 1.2 1.4 V , BODY DIODE FORWARD VOLTAGE (V)
SD
25°C
-55°C
Figure 8. N-Channel Body Diode Forward Voltage
Variation with Current and Temperature.
10
I = 5.3A
D
8
6
4
2
GS
V , GATE-SOURCE VOLTAGE (V)
0
0 5 10 15 20 25
V = 5V
DS
Q , GATE CHARGE (nC)
g
10V
20V
Figure 10. N-Channel Gate Charge Characteristics.
20
V = 10V
DS
16
T = -55°C
J
25°C
12
8
4
FS
g , TRANSCONDUCTANCE (SIEMENS)
0
0 5 10 15 20 25
I , DRAIN CURRENT (A)
D
125°C
Figure 11. N-Channel Transconductance Variation
with Drain Current and Temperature.
NDS8958 Rev. C
Page 6
Typical Electrical Characteristics: P-Channel (continued)
-20
V = -10V
GS
-15
-10
-5
D
I , DRAIN-SOURCE CURRENT (A)
0
-6.0
V , DRAIN-SOURCE VOLTAGE (V)
DS
-5.0
-4.5
-4.0
-3.5
-3.0
-4-3-2-10
3
V = -3.5V
2.5
2
1.5
DS(on)
R , NORMALIZED
1
DRAIN-SOURCE ON-RESISTANCE
0.5
GS
- 4.0
-4.5
I , DRAIN CURRENT (A)
D
Figure 12. P-Channel On-Region Characteristics. Figure 13. P-Channel On-Resistance Variation
with Gate Voltage and Drain Current.
1.6
I = -4.0A
D
1.4
V = -10V
GS
1.2
1
DS(ON)
R , NORMALIZED
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)
J
2
V = -10V
GS
1.5
1
DS(on)
R , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
0.5
T = 125°C
J
I , DRAIN CURRENT (A)
D
-5.0
-6.0
-10
-20-16-12-8-40
25°C
-55°C
-20-16-12-8-40
Figure 14. P-Channel On-Resistance Variation with
Temperature.
-20
V = -10V
DS
-15
-10
-5
D
I , DRAIN CURRENT (A)
0
V , GATE TO SOURCE VOLTAGE (V)
GS
T = -55°C
J
125°C
25°C
-6-5-4-3-2-1
Figure 15. P-Channel On-Resistance Variation with
Drain Current and Temperature.
1.2
1.1
1
0.9
th
0.8
V , NORMALIZED
0.7
GATE-SOURCE THRESHOLD VOLTAGE
0.6
-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)
J
Figure 16. P-Channel Transfer Characteristics. Figure 17. P-Channel Gate Threshold Variation
with Temperature.
V = V
GS
DS
I = -250µA
D
NDS8958 Rev. C
Page 7
Typical Electrical Characteristics: P-Channel (continued)
1.1
I = -250µA
1.08
1.06
1.04
1.02
DSS
BV , NORMALIZED
0.98
0.96
DRAIN-SOURCE BREAKDOWN VOLTAGE
0.94
D
1
-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)
J
Figure 18. P-Channel Breakdown Voltage
Variation with Temperature.
2000
1000
500
300
CAPACITANCE (pF)
200
100
f = 1 MHz V = 0V
GS
0.1 0.2 0.5 1 2 5 10 30
-V , DRAIN TO SOURCE VOLTAGE (V)
DS
C
C
iss
oss
C
rss
20
V = 0V
10
GS
5
T = 125°C
J
1
0.1
0.01
S
-I , REVERSE DRAIN CURRENT (A)
0.001 0 0.4 0.8 1.2 1.6 2
25°C
-55°C
-V , BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 19. P-Channel Body Diode Forward Voltage
Variation with Current and Temperature.
10
I = -4.0A
D V = -5V
8
6
4
2
GS
-V , GATE-SOURCE VOLTAGE (V)
0
0 5 10 15 20 25
Q , GATE CHARGE (nC)
DS
-20V
-10V
g
Figure 20. P-Channel Capacitance Characteristics. Figure 21. P-Channel Gate Charge Characteristic.
12
V = -10V
DS
9
6
3
FS
g , TRANSCONDUCTANCE (SIEMENS)
0
I , DRAIN CURRENT (A)
D
T = -55°C
J
25°C
125°C
-20-16-12-8-40
Figure 22. P-Channel Transconductance Variation with
Drain Current and Temperature.
NDS8958 Rev. C
Page 8
Typical Thermal Characteristics: N & P-Channel
- V , DRAIN-SOURCE CURRENT (V)
-I , DRAIN CURRENT (A)
2.5
2
1.5
1b
1
1c
0.5
STEADY-STATE POWER DISSIPATION (W)
0 0.2 0.4 0.6 0.8 1
2oz COPPER MOUNTING PAD AREA (in )
Total Power for Dual Operation
1a
Power for Single Operation
4.5"x5" FR-4 Board T = 25 C
A
Still Air
o
2
Figure 23. SO-8 Dual Package Maximum
Steady-State Power Dissipation versus Copper Mounting Pad Area.
4.5
4
3.5
1b
1c
3
2.5
D
-I , STEADY-STATE DRAIN CURRENT (A) 2
0 0.1 0.2 0.3 0.4 0.5
2oz COPPER MOUNTING PAD AREA (in )
4.5"x5" FR-4 Board
o
T = 25 C
A
Still Air V = -10V
GS
2
6
1a
5
1b
4
1c
3
D
I , STEADY-STATE DRAIN CURRENT (A)
2
0 0.1 0.2 0.3 0.4 0.5
2oz COPPER MOUNTING PAD AREA (in )
4.5"x5" FR-4 Board
o
T = 25 C
A
Still Air V = 10V
GS
2
Figure 24. N-Ch Maximum Steady-State Drain
Current versus Copper Mounting Pad Area.
50
1a
20
10
RDS(ON) LIMIT
5
1
0.5
V = 10V
GS
0.1
D
I , DRAIN CURRENT (A)
0.05
0.01
SINGLE PULSE
R = See Note 1c
JA
θ
T = 25°C
A
0.1 0.2 0.5 1 2 5 10 30 50 V , DRAIN-SOURCE VOLTAGE (V)
DS
DC
10s
100us
1ms
10ms
100ms
1s
Figure 25. P-Ch Maximum Steady- State
Drain Current versus Copper Mounting Pad Area.
50
20
10
5
RDS(ON) LIMIT
1
0.5
V = -10V
GS
D
0.1
0.05
0.01
SINGLE PULSE
R = See Note 1c
JA
θ
T = 25°C
A
0.1 0.2 0.5 1 2 5 10 30 50
DS
DC
10s
1ms
10ms
100ms
1s
Figure 27. P-Channel Maximum Safe Operating
Area.
Figure 26. N-Channel Maximum Safe Operating
Area.
100us
NDS8958 Rev. C
Page 9
Typical Thermal Characteristics: N & P-Channel
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
r(t), NORMALIZED EFFECTIVE
0.002
TRANSIENT THERMAL RESISTANCE
0.001
0.0001 0.001 0.01 0.1 1 10 100 300
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
t , TIME (sec)
1
Figure 28. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
R (t) = r(t) * R
JA
θ
R = See Note 1c
JA
θ
P(pk)
t
1
t
2
T - T = P * R (t)
J
A
Duty Cycle, D = t / t
JA
θ
JA
θ
2
1
V
DD
d(on)
V
IN
V
GS
R
GEN
G
R
L
D
V
OUT
V
OUT
DUT
V
S
IN
10%
t t
on off
r
d(off)
90%
10%
90%
50%
50%
90%
10%
PULSE WIDTH
Figure 29. N or P-Channel Switching Test Circuit. Figure 30. N or P-Channel Switching Waveforms.
tt
f
NDS8958 Rev. C
Page 10
SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging Configuration: Figure 1.0
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC, MAGNETIC OR RADIOACTIVE FIELDS
TNR DATE PT NUMBER PEEL STRENGTH MIN ______________gms
Customized Label
Packaging Option Packaging type
Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg)
Note/Comments
MAX _____________ gms
ESD Label
SOIC (8lds) Packaging Information
Standard
(no flow code)
2,500 95 4,000
13" Dia
343x64x343 530x130x83 343x64x343
5,000 30,000 8,000
0.0774 0.0774 0.0774 0.0774
0.6060 - 0.9696 0.1182
TNR
L86Z F011
Rail/Tube-TNR
13" Dia
Embossed Car rier Tape
Antistatic Cover Tape
Static Dissipative
F63TNR Label
D84Z
TNR
500
7" Dia
184x18 7x47
1,000
F
NDS
9959
9959
852
SOIC-8 Unit Orientation
343mm x 342mm x 64mm
Stand a r d In t e rm ed iate box
Packaging Description:
SOIC-8 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 2,500 uni t s pe r 13" o r 33 0c m d ia met er reel . Th e reel s ar e dark blue in color and is made of polystyrene plastic (anti­static coated). Other option comes in 500 units per 7" or 177cm di ameter reel. This and some o ther options are further described in the Packaging Information table.
These full reels are individually barcode labeled and placed inside a standard intermediate box (illustrated in figure 1.0) made of recyclable corrugated brown paper. One box contains two reels maximum. And these boxes are placed inside a barcode labeled shipping box which comes in di ff ere nt siz es depe nd in g on th e num be r of pa rts shippe d.
F
NDS
9959
F
NDS
9959
F
NDS
852
852
852
F
NDS 9959
852
Pin 1
F63TNR Label sample
LOT: CBVK741B019
FSID: FDS9953A
D/C1: D9842 QTY1: SPEC REV: D/C2: QTY2: CPN:
QTY: 2500
SPEC:
N/F: F (F63TNR)3
SOIC(8lds) Tape Leader and Trailer Configuration: Figure 2.0
Carrier Tape
Cover Tape
Trailer Tape 640mm minimum or 80 empty pockets
F63TNLab el
ESD Label
Components
ESD Label
F63TNLabel
Leader Tape 1680mm minimum or 210 empty pockets
July 1999, Rev. B
Page 11
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape Configuration: Figure 3.0
T
K0
Wc
B0
P0
D0
E1
F
W
E2
Tc
A0
D1
P1
User Direction of Feed
Dimensions are in millimeter
Pkg type
SOIC
(12mm)
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
SOIC(8lds) Reel Configuration: Figure 4.0
A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc
(8lds)
6.50
5.30
12.0
1.55
1.60
1.75
+/-0.10
+/-0.10
+/-0.3
+/-0.05
+/-0.10
+/-0.10
10.25 min
rotational and lateral movement requirements (see sketches A, B, and C).
B0
20 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
Sketch B (Top View)
Component Rotation
W1 Measured at Hub
5.50 +/-0.05
20 deg maximum
A0
8.0 +/-0.1
Typical component cavity center line
Typical component center line
Dim A
Max
4.0 +/-0.1
0.450
2.1 +/-0.10
0.5mm maximum
Sketch C (Top View)
Component lateral movement
+/-
0.150
9.2 +/-0.3
0.5mm maximum
0.06 +/-0.02
Dim A
max
Tape Size
12mm 7" Dia
12mm 13" Dia
1998 Fairchild Semiconductor Corporation
Reel
Option
Dim N
Diameter Option
7"
See detail AA
B Min
Dim C
13" Diameter Option
See detail AA
W2 max Measured at Hub
Dim D
W3
min
DETAIL AA
Dimensions are in inches and millimeters
Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
7.00
0.059
177.8
13.00 330
1.5
0.059
1.5
512 +0.020/- 0.008 13 +0.5/-0.2
512 +0.020/- 0.008 13 +0.5/-0.2
0.795
2.165550.488 +0.078/-0.000
20.2
0.795
7.00
20.2
178
12.4 +2/0
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.724
18.4
0.469 – 0.606
11.9 – 15.4
0.469 – 0.606
11.9 – 15.4
July 1999, Rev. B
Page 12
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1 : 1
Scale 1:1 on letter size paper
Dimen sions show n below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A
Page 13
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ CoolFET™ CROSSVOLT™
2
E
CMOS
TM
FACT™ FACT Quiet Series™
®
FAST FASTr™ GTO™ HiSeC™
ISOPLANAR™ MICROWIRE™ POP™ PowerTrench
QFET™ QS™
Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8
SyncFET™ TinyLogic™ UHC™ VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
PRODUCT STA TUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. D
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