Datasheet NDS8934 Datasheet (Fairchild Semiconductor)

NDS8934

Dual P-Channel Enhancement Mode Field Effect Transistor

General Description Features

March 1996

These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance, provide superior switching performance, and
withstand high energy pulses in the avalanche and
commutation modes. These devices are particularly
suited for low voltage applications such as notebook

-3.8A, -20V. R
R

High density cell design for extremely low R

= 0.07Ω @ VGS = -4.5V

DS(ON)

= 0.1Ω @ VGS = -2.7V.

DS(ON)

DS(ON)

.

High power and current handling capability in a widely used
surface mount package.

Dual MOSFET in surface mount package.
computer power management and other battery powered
circuits where fast switching, low in-line power loss, and
resistance to transients are needed.

_________________________________________________________________________________

5

6

7

8

4

3

2

1

Absolute Maximum Ratings T

= 25°C unless otherwise noted

A

Symbol Parameter NDS8934 Units

V

DSS

V

GSS

I

D

Drain-Source Voltage -20 V
Gate-Source Voltage -8 V
Drain Current - Continuous (Note 1a) -3.8 A

- Pulsed -15

P

D

Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9

TJ,T

Operating and Storage Temperature Range -55 to 150 °C

STG

THERMAL CHARACTERISTICS

R

θ

R

θ

© 1997 Fairchild Semiconductor Corporation

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W

JA

Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W

JC

NDS8934.SAM

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BV
I

DSS

I

GSSF

I

GSSR

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -20 V
Zero Gate Voltage Drain Current

Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse

VDS = -16 V, V
VDS = -10 V, V

= 0 V

GS

= 0 V, TJ = 70°C -5 µA

GS

VGS = 8 V, VDS = 0 V
VGS = -8 V, VDS= 0 V

-1 µA

100 nA

-100 nA

ON CHARACTERISTICS (Note 2)

V

R

GS(th)

DS(ON)

Gate Threshold Voltage

VDS = VGS, ID = -250 µA

TJ = 125°C

Static Drain-Source On-Resistance VGS = -4.5 V, ID = -3.8 A 0.06 0.07

TJ = 125°C

-0.5 -0.7 -1 V

-0.3 -0.5 -0.8

Ω

0.085 0.14

VGS = -2.7 V, ID = -3.2 A 0.082 0.1

I

D(on)

On-State Drain Current

VGS = -4.5 V, VDS = -5 V

-15 A

VGS = -2.7 V, VDS = -5 V -5

g

FS

Forward Transconductance

VDS = 10 V, ID = -3.8 A

9 S

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance VDS = -10 V, VGS = 0 V,
Output Capacitance 470 pF

f = 1.0 MHz

1120 pF

Reverse Transfer Capacitance 145 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q

D(on)

r

D(off)

f

Turn - On Delay Time

Turn - On Rise Time 53 70 ns

VDD = -5 V, ID = -1 A,
V

= -4.5 V, R

GEN

GEN

= 6 Ω

Turn - Off Delay Time 60 80 ns

Turn - Off Fall Time 33 40 ns

g

gs

gd

Total Gate Charge

Gate-Source Charge 2.4 nC

Gate-Drain Charge 5.5 nC

VDS = -10 V,
ID = -3.8 A, VGS = -4.5 V

13 20 ns

19 30 nC

NDS8934.SAM

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

Notes:

1. R
design while R

P

D

Typical R

Scale 1 : 1 on letter size paper

Maximum Continuous Drain-Source Diode Forward Current -1.3 A
Drain-Source Diode Forward Voltage

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

(t)

is determined by the user's board design.

CA

θ

T

=

R

JA

θ

a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper.

T

J−TA

=

(t)

R

θJ A

θ

J C

for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

J−TA

+R

2

= I

(t) × R

DS (ON ) T

D

(t)

θ

CA

J

1a

VGS = 0 V, IS = -1.3 A

1b

(Note 2)

1c

-0.75 -1.2 V

is guaranteed by

JC

θ

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%..

NDS8934.SAM

Typical Electrical Characteristics

-20

V = -4.5V

GS

-16

-12

-8

-4

D

I , DRAIN-SOURCE CURRENT (A)

0

V , DRAIN-SOURCE VOLTAGE (V)

DS

-3.5

-3.0

-2.7

-2.5

-2.0

-1.5

-4-3-2-10

2

1.8

V = -2.5V

1.6

1.4

1.2

DS(on)

R , NORMALIZED

1

DRAIN-SOURCE ON-RESISTANCE

0.8

GS

-2.7

-3.0

-3.5

I , DRAIN CURRENT (A)

D

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Gate

Voltage and Drain Current.

1.6

I = -3.8A

1.4

1.2

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

D

V = -4.5V

GS

1

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

2

V = -4.5V

GS

1.5

1

DS(on)

R , NORMALIZED

DRAIN-SOURCE ON-RESISTANCE

0.5

T = 125°C

J

I , DRAIN CURRENT (A)

D

-4.0

25°C

-55°C

-4.5

-5.0

-20-16-12-8-40

-20-16-12-8-40

Figure 3. On-Resistance Variation with

Temperature.

-20

V = -10V

DS

-16

-12

-8

D

I , DRAIN CURRENT (A)

-4

0

V , GATE TO SOURCE VOLTAGE (V)

GS

T = -55°C

J

Figure 5. Transfer Characteristics.

25°C

125°C

-4-3.5-3-2.5-2-1.5-1-0.50

Figure 4. On-Resistance Variation with Drain

Current and Temperature.

1.2

V = V

1.1

1

0.9

th

0.8

V , NORMALIZED

0.7

GATE-SOURCE THRESHOLD VOLTAGE

0.6

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

DS

I = -250µA

D

Figure 6. Gate Threshold Variation with

Temperature.

GS

NDS8934.SAM

Typical Electrical Characteristics

1.1

I = -250µA

D

1.08

1.06

1.04

1.02

1

DSS

BV , NORMALIZED

0.98

0.96

DRAIN-SOURCE BREAKDOWN VOLTAGE

0.94

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Breakdown Voltage Variation with

Temperature.

2000
1500

1000

800
600

400

CAPACITANCE (pF)

f = 1 MHz

200

V = 0V

GS

100

0.1 0.2 0.5 1 2 3 5 10 20

-V , DRAIN TO SOURCE VOLTAGE (V)

DS

C

iss

C

oss

Figure 9. Capacitance Characteristics.

C

rss

20
10

V = 0V

GS

2
1

T = 125°C

J

0.1

0.01

0.001

S

-I , REVERSE DRAIN CURRENT (A)

0.0001
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

-V , BODY DIODE FORWARD VOLTAGE (V)

25°C

-55°C

SD

Figure 8. Body Diode Forward Voltage Variation

with Current and Temperature.

5

I = -3.8A

D

4

3

2

1

GS

-V , GATE-SOURCE VOLTAGE (V)
0

0 5 10 15 20 25

V = -5.0V

DS

Q , GATE CHARGE (nC)

g

-10V

-15V

Figure 10. Gate Charge Characteristics.

20

V = -10V

DS

15

T = -55°C

J

25°C

125°C

10

5

FS

g , TRANSCONDUCTANCE (SIEMENS)

0

I , DRAIN CURRENT (A)

D

Figure 11. Transconductance Variation with Drain

Current and Temperature.

-20-16-12-8-40

NDS8934.SAM

Typical Thermal Characteristics

2.5

2

1.5

1b

1

1c

0.5

STEADY-STATE POWER DISSIPATION (W)

0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

Total Power for Dual Operation

1a

Power for Single Operation

4.5"x5" FR-4 Board
T = 25 C

A

Still Air

2

Figure 12. SO-8 Dual Package Maximum

Steady-State Power Dissipation versus
Copper Mounting Pad Area.

30

10

RDS(ON) LIMIT

3

1

0.3

0.1

D

-I , DRAIN CURRENT (A)

0.03

0.01

0.1 0.2 0.5 1 2 5 10 20 30

V = -4.5V

GS

SINGLE PULSE

R = See Note 1c

JA

θ

T = 25°C

A

- V , DRAIN-SOURCE VOLTAGE (V)

DS

100ms

10ms

1s

10s

DC

o

100us

1ms

4.5

4

3.5

1b

3

1c

2.5

D

-I , STEADY-STATE DRAIN CURRENT (A)
2

0 0.1 0.2 0.3 0.4 0.5

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air
V = -4.5V

GS

2

Figure 13. Maximum Steady-State Drain

Current versus Copper Mounting Pad
Area.

1a

Figure 14. Maximum Safe Operating Area.

1

0.5

0.2

0.1

0.05

0.02

0.01

0.005

r(t), NORMALIZED EFFECTIVE

0.002

TRANSIENT THERMAL RESISTANCE

0.001

0.0001 0.001 0.01 0.1 1 10 100 300

D = 0.5

0.2

R (t) = r(t) * R

JA

θ

0.1

0.05

0.02

0.01
Single Pulse

t , TIME (sec)

1

Figure 15. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change

depending on the circuit board design.

R = See Note 1c

JA

θ

P(pk)

t

1

t

2

T - T = P * R (t)

J

A

Duty Cycle, D = t / t

JA

θ

JA

θ

2

1

NDS8934.SAM