Datasheet NDS8410A Datasheet (Fairchild Semiconductor)

March 1997

NDS8410A
Single N-Channel Enhancement Mode Field Effect Transistor

General Description Features

SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer

10.8 A, 30 V. R
R

High density cell design for extremely low R
High power and current handling capability in a widely used

surface mount package.

power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.

____________________________________________________________________________________________

= 0.012 Ω @ VGS = 10 V

DS(ON)

= 0.017 Ω @ VGS = 4.5 V.

DS(ON)

DS(ON)

.

ABSOLUTE MAXIMUM RATINGS T

= 25°C unless otherwise noted

A

5

6

7

8

4

3
2

1

Symbol Parameter NDS8410A Units

V

DSS

V

GSS

I

D

Drain-Source Voltage 30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) 10.8 A

- Pulsed 50

P

D

TJ,T

Maximum Power Dissipation (Note 1a) 2.5 W

(Note 1b)

(Note 1c)

Operating and Storage Temperature Range -55 to 150 °C

STG

1.2
1

THERMAL CHARACTERISTICS

R

JA

θ

R

JC

θ

Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W

© 1997 Fairchild Semiconductor Corporation

NDS8410A Rev.C1

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units

OFF CHARACTERISTICS

BV
I

DSS

I

GSSF

I

GSSR

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current

VDS = 24 V, V

GS

= 0 V

TJ= 55°C

1 µA

10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse

VGS = -20 V, VDS= 0 V

-100 nA

ON CHARACTERISTICS (Note 2)

V

R

GS(th)

DS(ON)

Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.45 3 V

TJ= 125°C

0.8 1 2.1

Static Drain-Source On-Resistance VGS = 10 V, ID = 10.8 A 0.0105 0.012

TJ= 125°C

0.015 0.022

Ω

VGS = 4.5 V, ID = 9 A 0.015 0.017
I
g

D(on)

On-State Drain Current

FS

Forward Transconductance VDS = 10 V, ID = 10.8 A 25 S

VGS = 10 V, VDS = 5 V

50 A

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 790 pF

VDS = 15 V, V

f = 1.0 MHz

GS

= 0 V,

Reverse Transfer Capacitance 210 pF

1430 pF

SWITCHING CHARACTERISTICS (Note 2)

t
t
t
t
Q
Q
Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time VDD = 10 V, ID = 1 A,

V

= 10 V, R

Turn - On Rise Time 18 30 ns

GEN

GEN

= 6 Ω

12 20 ns

Turn - Off Delay Time 65 100 ns
Turn - Off Fall Time 37 80 ns
Total Gate Charge VDS = 15 V,
Gate-Source Charge 5.5 nC

ID = 10.8 A, VGS = 10 V

45 60 nC

Gate-Drain Charge 10.5 nC

NDS8410A Rev.C1

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

t

rr

Notes:

1. R
design while R

P

Typical R

Maximum Continuous Drain-Source Diode Forward Current 2.1 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

(t)

D

is determined by the user's board design.

CA

θ

T

=

R

JA

θ

a. 50oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 105oC/W when mounted on a 0.04 in2 pad of 2oz copper.
c. 125oC/W when mounted on a 0.006 in2 pad of 2oz copper.

T

J−TA

θJA

for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

J−TA

=

(t)

R

θJC+RθCA

2

= I

(t)×R

D

DS(O N ) T

(t)

J

1a

VGS = 0 V, IS = 10.8 A
VGS = 0V, IF = 2.1 A, dIF/dt = 100 A/µs

1b

(Note 2)

1c

1.2 V
80 ns

is guaranteed by

JC

θ

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%

NDS8410A Rev.C1

Typical Electrical Characteristics

50

V = 10V

GS

6.0

40

30

4.5

4.0

3.5

20

3.0

10

D

I , DRAIN-SOURCE CURRENT (A)

0

0 0.5 1 1.5 2 2.5 3

V , DRAIN-SOURCE VOLTAGE (V)

DS

2.5

Figure 1. On-Region Characteristics.

1.6

I = 10.8A

D

V = 10V

GS

1.4

1.2

1

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

2.5

2

V = 3.5 V

GS

1.5

DS(on)

1

R , NORMALIZED

DRAIN-SOURCE ON-RESISTANCE

0.5
0 10 20 30 40 50

4.0

4.5

5.0

I , DRAIN CURRENT (A)

D

6.0

7.0

Figure 2. On-Resistance Variation

with Drain Current and Gate Voltage.

1.8

V = 10V

GS

1.6

1.4

1.2

1

DS(on)

0.8

R , NORMALIZED

0.6

DRAIN-SOURCE ON-RESISTANCE

0.4
0 10 20 30 40 50

T = 125°C

J

25°C

-55°C

I , DRAIN CURRENT (A)

D

10

Figure 3. On-Resistance Variation

with Temperature.

60

V = 10V

DS

50

40

30

20

D

I , DRAIN CURRENT (A)

10

0

1 1.5 2 2.5 3 3.5 4 4.5 5

V , GATE TO SOURCE VOLTAGE (V)

GS

T = -55°C

J

25

125

Figure 5. Transfer Charateristics.

Figure 4. On-Resistance Variation

with Drain Current and Temperature.

1.3

1.2

1.1

1

0.9

0.8

GS(th)

0.7

V , NORMALIZED

0.6

GATE-SOURCE THRESHOLD VOLTAGE

0.5

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

V = V

DS

GS

I = 250µA

D

Figure 6. Gate Threshold Variation

with Temperature.

NDS8410A Rev.C1

Typical Electrical Characteristics (continued)

1.12

I = 250µA

D

1.08

1.04

1

DSS

BV , NORMALIZED

0.96

DRAIN-SOURCE BREAKDOWN VOLTAGE

0.92

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Breakdown Voltage

Variation with Temperature.

4000
3000

2000

1000

500

300

CAPACITANCE (pF)

f = 1 MHz
V = 0 V

GS

100

0.1 0.2 0.5 1 2 5 10 20 30
V , DRAIN TO SOURCE VOLTAGE (V)

DS

C

C

C

iss

oss

rss

40
20

V = 0V

GS

10

1

0.1

0.01

0.001

S

I , REVERSE DRAIN CURRENT (A)

0.0001
0 0.3 0.6 0.9 1.2

V , BODY DIODE FORWARD VOLTAGE (V)

SD

T = 125°C

J

25°C

-55°C

Figure 8. Body Diode Forward Voltage Variation with

Source Current and Temperature.

10

I = 10.8A

D

8

6

4

2

GS

V , GATE-SOURCE VOLTAGE (V)

0

0 10 20 30 40 50

Q , GATE CHARGE (nC)

g

V = 5V

DS

15V

10V

Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics.

V

V

IN

D

V

GS

R

GEN

G

S

Figure 11. Switching Test Circuit.

DD

t

d(on)

R

L

V

OUT

V

OUT

DUT

V

IN

10%

t t

on off

t

r

d(off)

90%

10%

50%

50%

PULSE WIDTH

Figure 12. Switching Waveforms.

NDS8410A Rev.C1

90%

90%

10%

tt

f

INVERTED

Typical Electrical and ThermalCharacteristics (continued)

50

V = 10V

DS

40

T = -55°C

J

25°C

30

125°C

20

10

FS

g , TRANSCONDUCTANCE (SIEMENS)

0

0 6 12 18 24 30

I , DRAIN CURRENT (A)

D

Figure 13. Transconductance Variation with Drain

Current and Temperature.

12

11

10

9

1b

8

1c

D

I , STEADY-STATE DRAIN CURRENT (A)

7

0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air
V = 10V

GS

2

2.5

1a

2

1.5

1b

1c

1

STEADY-STATE POWER DISSIPATION (W)

0.5
0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air

2

Figure 14. SO-8 Maximum Steady-State Power

Dissipation versus Copper Mounting Pad
Area.

80
50
30

1a

RDS(ON) LIMIT

10

5

1

0.5

V = 10V

GS

SINGLE PULSE

0.1

D

R = See Note 1c

I , DRAIN CURRENT (A)

JA

θ

T = 25°C

A

A

0.01

0.1 0.2 0.5 1 5 10 20 30 50

V , DRAIN-SOURCE VOLTAGE (V)

DS

10s

DC

100µs

1ms

10ms

100ms

1s

Figure 15. Maximum Steady- State Drain

Figure 16. Maximum Safe Operating Area.

Current versus Copper Mounting Pad
Area.

1

0.5

0.2

0.1

0.05

0.02

0.01

0.005

r(t), NORMALIZED EFFECTIVE

0.002

TRANSIENT THERMAL RESISTANCE

0.001

0.0001 0.001 0.01 0.1 1 10 100 300

D = 0.5

0.2

0.1

0.05

0.02

0.01

Single Pulse

t , TIME (sec)

1

Figure 17. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change

depending on the circuit board design.

P(pk)

R (t) = r(t) * R

JA

θ

R = See note 1c

JA

θ

t

1

t

2

T - T = P * R (t)

J

A

Duty Cycle, D = t /t

JA

θ

1

NDS8410A Rev.C1

JA

θ

2

SO-8 Tape and Reel Data and Package Dimensions

SOIC(8lds) Packaging
Configuration: Figure 1.0

ELECTROSTATIC

SENSITIVE DEVICES

DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC
ELECTROMAGNETIC, MAGNETIC OR RADIOACTIVE FIELDS

TNR DATE
PT NUMBER
PEEL STRENGTH MIN ______________gms

Customized
Label

Packaging Option
Packaging type

Qty per Reel/Tube/Bag
Reel Size
Box Dimension (mm)
Max qty per Box
Weight per unit (gm)
Weight per Reel (kg)

Note/Comments

MAX _____________ gms

ESD Label

SOIC (8lds) Packaging Information

Standard

(no flow code)

2,500 95 4,000

13" Dia

343x64x343 530x130x83 343x64x343

5,000 30,000 8,000

0.0774 0.0774 0.0774 0.0774

0.6060 - 0.9696 0.1182

TNR

L86Z F011

Rail/Tube-TNR

13" Dia

Embossed Car rier Tape

Antistatic Cover Tape

Static Dissipative

F63TNR
Label

D84Z

TNR
500

7" Dia

184x18 7x47

1,000

F

NDS

9959

9959

852

SOIC-8 Unit Orientation

343mm x 342mm x 64mm

Stand a r d In t e rm ed iate box

Packaging Description:

SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 uni t s pe r 13" o r 33 0c m d ia met er reel . Th e reel s ar e
dark blue in color and is made of polystyrene plastic (anti­static coated). Other option comes in 500 units per 7" or
177cm di ameter reel. This and some o ther options are
further described in the Packaging Information table.

These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in di ff ere nt siz es depe nd in g on th e num be r of pa rts
shippe d.

F

NDS

9959

F

NDS

9959

F

NDS

852

852

852

F

NDS
9959

852

Pin 1

F63TNR Label sample

LOT: CBVK741B019

FSID: FDS9953A

D/C1: D9842 QTY1: SPEC REV:
D/C2: QTY2: CPN:

QTY: 2500

SPEC:

N/F: F (F63TNR)3

SOIC(8lds) Tape Leader and Trailer
Configuration: Figure 2.0

Carrier Tape

Cover Tape

Trailer Tape
640mm minimum or
80 empty pockets

F63TNLab el

ESD Label

Components

ESD Label

F63TNLabel

Leader Tape
1680mm minimum or
210 empty pockets

July 1999, Rev. B

SO-8 Tape and Reel Data and Package Dimensions, continued

SOIC(8lds) Embossed Carrier Tape
Configuration: Figure 3.0

T

K0

Wc

B0

P0

D0

E1

F

W

E2

Tc

A0

D1

P1

User Direction of Feed

Dimensions are in millimeter

Pkg type

(8lds)

SOIC

(12mm)

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481

SOIC(8lds) Reel Configuration: Figure 4.0

A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc

6.50

5.30

12.0

1.55

1.60

1.75

10.25

+/-0.10

+/-0.10

+/-0.3

+/-0.05

+/-0.10

+/-0.10

rotational and lateral movement requirements (see sketches A, B, and C).

B0

20 deg maximum component rotation

Sketch A (Side or Front Sectional View)

Component Rotation

5.50

min

+/-0.05

20 deg maximum

A0

Sketch B (Top View)

Component Rotation

W1 Measured at Hub

8.0
+/-0.1

Typical
component
cavity
center line

Typical
component
center line

Dim A

Max

4.0
+/-0.1

0.450

2.1
+/-0.10

0.5mm
maximum

Sketch C (Top View)

Component lateral movement

+/-

0.150

9.2
+/-0.3

0.5mm
maximum

0.06
+/-0.02

Dim A

max

Tape Size

12mm 7" Dia

12mm 13" Dia

 1998 Fairchild Semiconductor Corporation

Reel

Option

Dim N

Diameter Option

7"

See detail AA

B Min

Dim C

13" Diameter Option

See detail AA

W2 max Measured at Hub

Dim D

W3

min

DETAIL AA

Dimensions are in inches and millimeters

Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)

7.00

0.059

177.8

13.00
330

1.5

0.059

1.5

512 +0.020/-0.008
13 +0.5/-0.2

512 +0.020/-0.008
13 +0.5/-0.2

0.795

2.165550.488 +0.078/-0.000

20.2

0.795

7.00

20.2

178

12.4 +2/0

0.488 +0.078/-0.000

12.4 +2/0

0.724

18.4

0.724

18.4

0.469 – 0.606

11.9 – 15.4

0.469 – 0.606

11.9 – 15.4

July 1999, Rev. B

SO-8 Tape and Reel Data and Package Dimensions, continued

SOIC-8 (FS PKG Code S1)

1 : 1

Scale 1:1 on letter size paper

Dimensions shown below are in:

inches [millimeters]

Part Weight per unit (gram): 0.0774

9

September 1998, Rev. A

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx™
CoolFET™
CROSSVOLT™

2

CMOS

E

TM

FACT™
FACT Quiet Series™

®

FAST
FASTr™
GTO™
HiSeC™

ISOPLANAR™
MICROWIRE™
POP™
PowerTrench™
QFET™
QS™

Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8

TinyLogic™
UHC™
VCX™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:

1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.

2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or

effectiveness.

PRODUCT STA TUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

Formative or
In Design

First Production

Full Production

Not In Production

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.