Datasheet NDS355N Datasheet (Fairchild Semiconductor)

NDS355N
N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description Features

March 1996

These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMICA
cards, and other battery powered circuits where fast switching,
and low in-line power loss are needed in a very small outline
surface mount package.

1.6A, 30V. R

= 0.125Ω @ VGS = 4.5V.

DS(ON)

Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.

High density cell design for extremely low R

DS(ON)

.

Exceptional on-resistance and maximum DC current
capability.

Compact industry standard SOT-23 surface mount
package.

_______________________________________________________________________________

D

G

S

Absolute Maximum Ratings T

= 25°C unless otherwise noted

A

Symbol Parameter NDS355N Units

V

DSS

V

GSS

I

D

Drain-Source Voltage 30 V
Gate-Source Voltage - Continuous 20 V
Drain Current - Continuous (Note 1a) ± 1.6 A

- Pulsed ± 10

P

D

TJ,T

Maximum Power Dissipation (Note 1a) 0.5 W

(Note 1b)

Operating and Storage Temperature Range -55 to 150 °C

STG

0.46

THERMAL CHARACTERISTICS

R

JA

θ

R

JC

θ

© 1997 Fairchild Semiconductor Corporation

Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
Thermal Resistance, Junction-to -Case (Note 1) 75 °C/W

NDS355N Rev. D1

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BV
I

DSS

I

GSSF

I

GSSR

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current

VDS = 24 V, V

GS

= 0 V

TJ=125°C

1 µA

10 µA
Gate - Body Leakage, Forward VGS = 12 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse

VGS = -12 V, VDS= 0 V

-100 nA

ON CHARACTERISTICS (Note 2)

V

R

GS(th)

DS(ON)

Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.6 2 V

0.5 1.3 1.5

0.125

Static Drain-Source On-Resistance

TJ=125°C

VGS = 4.5 V, ID = 1.6 A

Ω

TJ=125°C 0.25

0.085

3.5 S

I
g

D(ON)

FS

VGS = 10 V, ID = 1.9 A
On-State Drain Current VGS = 4.5 V, VDS = 5 V 6 A
Forward Transconductance

VDS = 5 V, ID = 1.6 A

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 130 pF

VDS = 10 V, VGS = 0 V,

f = 1.0 MHz
Reverse Transfer Capacitance 20 pF

245 pF

SWITCHING CHARACTERISTICS (Note 2)

t
t
t
t
Q
Q
Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time VDD = 10 V, ID = 1 A,
Turn - On Rise Time 14 30 ns

VGS = 10 V, R

GEN

= 6 Ω

15 30 ns

Turn - Off Delay Time 12 25 ns
Turn - Off Fall Time 4 10 ns
Total Gate Charge VDS = 10 V, ID = 1.6 A,
Gate-Source Charge 1 nC

VGS = 5 V

3.5 5 nC

Gate-Drain Charge 2 nC

NDS355N Rev. D1

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

I

SM

V

SD

Notes:

1. R
design while R

P

D

Typical R

a. 250

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

Maximum Continuous Source Current 0.6 A
Maximum Pulse Source Current (Note 2) 6 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.6 A 0.8 1.2 V

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

(t)

is determined by the user's board design.

CA

θ

T

=

R

JA

θ

o

C/W when mounted on a 0.02 in2 pad of 2oz cpper.

b. 270oC/W when mounted on a 0.001 in2 pad of 2oz cpper.

T

J−TA

θJ A

1a

J−TA

=

(t)

R

θ

J C

using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

2

= I

(t) × R

DS(ON ) T

D

+R

(t)

θ

CA

J

1b

is guaranteed by

JC

θ

NDS355N Rev. D1

Typical Electrical Characteristics

12

V =10V

GS

9

6

6.0

5.0

4.5

4.0

3.5

3

D

I , DRAIN-SOURCE CURRENT (A)

0

0 1 2 3 4

V , DRAIN-SOURCE VOLTAGE (V)

DS

3.0

2

V =3.5V

GS

1.5

4.0

4.5

1

DS(on)

R , NORMALIZED

DRAIN-SOURCE ON-RESISTANCE

0.5
0 3 6 9 12

I , DRAIN CURRENT (A)

D

Figure 1. On-Region Characteristics Figure 2. On-Resistance Variation with Gate Voltage

and Drain Current

1.6

I = 1.6A

D

1.4

1.2

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

V =4.5V

GS

1

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

Figure 3. On-Resistance Variation

with Temperature

3

V = 4.5V

GS

2.5

T = 125°C

2

1.5

DS(on)

R , NORMALIZED

1

DRAIN-SOURCE ON-RESISTANCE

0.5
0 2 4 6 8 10 12

J

25°C

I , DRAIN CURRENT (A)

D

-55°C

Figure 4. On-Resistance Variation with Drain

Current and Temperature

5.0

6.0

10

10

V = 10V

8

6

4

D

I , DRAIN CURRENT (A)

2

0

DS

1 2 3 4 5 6

V , GATE TO SOURCE VOLTAGE (V)

GS

T = -55°C

J

25°C

125°C

Figure 5. Transfer Characteristics Figure 6. Gate Threshold Variation with

1.2

V = V

1.1

1

0.9

th

0.8

V , NORMALIZED

0.7

GATE-SOURCE THRESHOLD VOLTAGE (V)

0.6

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

DS GS

I = 250µA

D

Temperature

NDS355N Rev. D1

Pulse Width

Typical Electrical Characteristics (continued)

1.15

I = 250µA

D

1.1

1.05

1

DSS

BV , NORMALIZED

0.95

0.9

DRAIN-SOURCE BREAKDOWN VOLTAGE (V)

-50 -25 0 25 50 75 100 125 150 175
T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Breakdown Voltage Variation

with Temperature

500

300
200

100

50

CAPACITANCE (pF)

30

f = 1 MHz
V = 0V

GS

0.1 0.2 0.5 1 2 5 10 30
V , DRAIN TO SOURCE VOLTAGE (V)

DS

C

C

20
10

V = 0V

GS

1

T = 125°C

J

0.1

0.01

S

I , REVERSE DRAIN CURRENT (A)

0.001

0.2 0.4 0.6 0.8 1 1.2 1.4
V , BODY DIODE FORWARD VOLTAGE (V)

SD

25°C

-55°C

Figure 8. Body Diode Forward Voltage Variation

with Current and Temperature

10

V = 5V

iss

oss

C

rss

I = 1.6A

D

8

6

4

2

GS

V , GATE-SOURCE VOLTAGE (V)

0

0 1 2 3 4 5 6 7

Q , GATE CHARGE (nC)

g

DS

10

15

Figure 9. Capacitance Characteristics Figure 10. Gate Charge Characteristics

out

10%

t

50%

on

10%

r

t

90%

t

d(off)

V

DD

t

d(on)

V

IN

V

GS

R

GEN

G

R

L

D

V

OUT

DUT

Input, V

in

S

Figure 11. Switching Test Circuit Figure 12. Switching Waveforms

50%

90%

t

off

90%

10%

t

f

Inverted

NDS355N Rev. D1

Typical Electrical Characteristics (continued)

r(t), NORMALIZED EFFECTIVE

8

-55°C

6

4

2

FS

g , TRANSCONDUCTANCE (SIEMENS)

0

0 2 4 6 8 10 12

I , DRAIN CURRENT (A)

D

D

25°C

T = 125°C

J

V = 5V

DS

Figure 13. Transconductance Variation with Drain

20
10

100us

1ms

2

RDS(ON) Limit

1

0.5

0.1

D

I , DRAIN CURRENT (A)

0.01

V = 10V

GS

SINGLE PULSE

T = 25°C

A

0.1 1 2 5 10 20 30 50
V , DRAIN-SOURCE VOLTAGE (V)

DS

DC

10s

10ms

100ms

1s

Figure 14. Maximum Safe Operating Area

Current and Temperature

1

D = 0.5

0.5

0.2

0.2

0.1

0.1

0.05

0.05

0.02

0.02

0.01

0.01

0.005

0.002

TRANSIENT THERMAL RESISTANCE

0.001

0.0001 0.001 0.01 0.1 1 10 100 300

Single Pulse

t , TIME (sec)

1

R (t) = r(t) * R

JA

θ

R = 250 °C/W

JA

θ

P(pk)

t

1

t

2

T - T = P * R (t)

J

Duty Cycle, D = t /t

θ

A

JA

θ

1 2

JA

Figure 15. Transient Thermal Response Curve

Note : Characterization performed using the conditions described in note 1c. Transient thermal response will

change depending on the circuit board design.

NDS355N Rev. D1