Datasheet NDS352P Datasheet (Fairchild Semiconductor)

NDS352P

P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description Features

March 1996

These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.

-0.85A, -20V. R

= 0.5Ω @ VGS = -4.5V.

DS(ON)

Proprietary package design using copper lead frame for superior thermal and electrical capabilities.

High density cell design for extremely low R

DS(ON)

.

Exceptional on-resistance and maximum DC current capability.

Compact industry standard SOT-23 surface mount package.

____________________________________________________________________________________________

D

G

S

Absolute Maximum Ratings T

= 25°C unless otherwise noted

A

Symbol Parameter NDS352P Units

V

DSS

V

GSS

I

D

Drain-Source Voltage -20 V Gate-Source Voltage - Continuous ±12 V Maximum Drain Current - Continuous (Note 1a) ±0.85 A

- Pulsed ±10

P

D

TJ,T

Maximum Power Dissipation (Note 1a) 0.5 W

(Note 1b)

Operating and Storage Temperature Range -55 to 150 °C

STG

0.46

THERMAL CHARACTERISTICS

R

JA

θ

R

JC

θ

Thermal Resistance, Junction-to-Ambient (Note 1a)

Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W

250 °C/W

NDS352P Rev. F1

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS

BV I

DSS

I

GSSF

I

GSSR

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -20 V Zero Gate Voltage Drain Current

VDS = -16 V, V

GS

= 0 V

TJ =125°C

-5 µA

-20 µA Gate - Body Leakage, Forward VGS = 12 V, VDS = 0 V 100 nA Gate - Body Leakage, Reverse

VGS = -12 V, VDS = 0 V

-100 nA

ON CHARACTERISTICS (Note 2)

V

R

I

D(ON)

g

GS(th)

DS(ON)

FS

Gate Threshold Voltage VDS = VGS, ID = -250 µA -0.8 -1.6 -2.5 V

-0.5 -1.3 -2.2

0.46 0.5

0.59 0.7

0.35

-2 A

1.5 S

Static Drain-Source On-Resistance

On-State Drain Current Forward Transconductance

TJ =125°C

VGS = -4.5 V, ID = -0.85 A

TJ =125°C VGS = -10 V, ID = -1 A VGS = -4.5 V, VDS = -5 V VDS = -5 V, ID = -0.85 A

Ω

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance Output Capacitance 140 pF

VDS = -10 V, VGS = 0 V, f = 1.0 MHz

Reverse Transfer Capacitance 45 pF

125 pF

SWITCHING CHARACTERISTICS (Note 2)

t t t t Q Q Q

d(on)

r

d(off)

f

g

gs

gd

Turn - On Delay Time VDD = -10 V, ID = -1 A, Turn - On Rise Time 19 30 ns

VGS = -10 V, R

GEN

= 50 Ω

8 15 ns

Turn - Off Delay Time 64 90 ns Turn - Off Fall Time 61 90 ns Total Gate Charge VDS = -10 V, ID = -0.85 A, Gate-Source Charge 1 nC

VGS = -5 V

2.2 4 nC

Gate-Drain Charge 2 nC

NDS352P Rev. F1

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

I

SM

V

SD

Notes:

1. R design while R

P

D

Typical R

a. 250

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

Maximum Continuous Drain-Source Diode Forward Current -0.6 A Maximum Pulsed Drain-Source Diode Forward Current -5 A Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.85 A (Note 2) -0.92 -1.2 V

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

(t)

is determined by the user's board design.

CA

θ

T

=

R

θ

o

C/W when mounted on a 0.02 in2 pad of 2oz cpper.

b. 270oC/W when mounted on a 0.001 in2 pad of 2oz cpper.

1a

T

J−TA

=

(t)

R

θJ A

θ

J C

using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

JA

J−TA

+R

2

= I

(t) × R

DS(ON ) T

D

(t)

θ

CA

J

1b

is guaranteed by

JC

θ

NDS352P Rev. F1

Typical Electrical Characteristics

I , DRAIN CURRENT (A)

DRAIN-SOURCE ON-RESISTANCE

R , NORMALIZED

DS(on)

-5

V = -10V

GS

-4

-7.0

-5.5

-5.0

-4.5

1.8

1.6

1.4

V = -3.5 V

GS

-4.0

-3

1.2

1

DS(on)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6 I , DRAIN CURRENT (A)

D

-2

-1

D

I , DRAIN-SOURCE CURRENT (A)

0

V , DRAIN-SOURCE VOLTAGE (V)

DS

-4.0

-3.5

-3.0

-4-3-2-10

Figure 1. On-Region Characteristics Figure 2. On-Resistance Variation

with Drain Current and Gate Voltage

1.4

I = -0.85A

D

1.3

V = -4.5V

1.2

1.1

0.9

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE (OHMS)

0.7

GS

1

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

2

V = -4.5V

1.8

1.6

GS

T = 125°C

J

1.4

1.2

1

0.8

0.6

D

-4.5

-5.0

-5.5

-7.0

-10

-5-4-3-2-10

25°C

-55°C

-4-3-2-10

Figure 3. On-Resistance Variation

with Temperature

-5

V = -10V

DS

-4

-3

-2

D

I , DRAIN CURRENT (A)

-1

0

V , GATE TO SOURCE VOLTAGE (V)

GS

Figure 5. Transfer Characteristics

T = -55°C

J

25

125

th

V , NORMALIZED

-6-5-4-3-2-1

Figure 4. On-Resistance Variation

with Drain Current and Temperature

1.15

V = V

1.1

1.05

1

0.95

0.9

0.85

GATE-SOURCE THRESHOLD VOLTAGE (V)

0.8

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

DS

I = -250µA

D

Figure 6. Gate Threshold Variation

GS

with Temperature

NDS352P Rev. F1

Typical Electrical Characteristics (continued)

1.15

I = -250µA

D

1.1

1.05

1

DSS

BV , NORMALIZED

0.95

0.9

DRAIN-SOURCE BREAKDOWN VOLTAGE (V)

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Breakdown Voltage Variation with

Temperature

500

300

200

100

CAPACITANCE (pF)

50

f = 1 MHz V = 0 V

30

20

GS

0.1 0.2 0.5 1 2 5 10 20

-V , DRAIN TO SOURCE VOLTAGE (V)

DS

C

iss

oss

rss

5

V = 0V

GS

1

0.5

T = 125°C

J

0.1

0.01

S

-I , REVERSE DRAIN CURRENT (A)

0 0.4 0.8 1.2 1.6 2 2.4

25°C

-55°C

-V , BODY DIODE FORWARD VOLTAGE (V)

SD

Figure 8. Body Diode Forward Voltage Variation with

Source Current and Temperature

-10

I = -850mA

-8

-6

-4

-2

GS

V , GATE-SOURCE VOLTAGE (V)

0

D

V = -5V

DS

0 1 2 3 4

Q , GATE CHARGE (nC)

g

-10

Figure 9. Capacitance Characteristics

V

DD

V

IN

D

V

GS

R

GEN

G

S

Figure 11. Switching Test Circuit

Figure 10. Gate Charge Characteristics

t t

on off

t

R

d(on)

L

V

OUT

V

OUT

r

90%

10%

t

d(off)

90%

10%

tt

f

DUT

90%

V

IN

50%

10%

PULSE WIDTH

INVERTED

Figure 12. Switching Waveforms

NDS352P Rev. F1

I , DRAIN CURRENT (A)

g , TRANSCONDUCTANCE (SIEMENS)

Typical Electrical Characteristics (continued)

r(t), NORMALIZED EFFECTIVE

3

V = -5V

2.5

1.5

DS

2

T = -55°C

J

25°C

125°C

1

0.5

FS

0

D

Figure 13. Transconductance Variation with

-5-4-3-2-10

20 10

5

2 1

0.5

0.1

D

-I , DRAIN CURRENT (A)

0.05

0.01

0.1 0.2 0.5 1 2 5 10 20 30

RDS(ON) LIMIT

V = -10V

GS

SINGLE PULSE

T = 25°C

A

- V , DRAIN-SOURCE VOLTAGE (V)

DS

DC

10s

1ms

10ms

100ms

1s

Figure 14. Maximum Safe Operating Area

100us

Drain Current and Temperature

1

D = 0.5

0.5

0.2

0.1

0.05

0.02

0.01

0.005

0.002

TRANSIENT THERMAL RESISTANCE

0.001

0.0001 0.001 0.01 0.1 1 10 100 300

Single Pulse

t , TIME (sec)

1

R (t) = r(t) * R

JA

θ

R = 250 °C/W

JA

θ

P(pk)

t

1

t

2

T - T = P * R (t)

J

Duty Cycle, D = t /t

θ

A

JA

θ

1 2

JA

Figure 15. Transient Thermal Response Curve

Note : Characterization performed using the conditions described in note 1c. Transient thermal response will

change depending on the circuit board design.

NDS352P Rev. F1

Datasheet NDS352P Datasheet (Fairchild Semiconductor)

Specifications and Main Features

Frequently Asked Questions

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