Datasheet NDS352AP Datasheet (Fairchild Semiconductor)

NDS352AP
P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description Features

February 1997

These P -Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage applications
such as notebook computer power management, portable
electronics, and other battery powered circuits where fast
high-side switching, and low in-line power loss are needed in a
very small outline surface mount package.

-0.9 A, -30 V. R
R

= 0.5 Ω @ VGS = -4.5 V

DS(ON)

= 0.3 Ω @ VGS = -10 V.

DS(ON)

Industry standard outline SOT-23 surface mount package
using proprietary SuperSOTTM-3 design for superior thermal
and electrical capabilities.

High density cell design for extremely low R

DS(ON)

.

Exceptional on-resistance and maximum DC current
capability.

________________________________________________________________________________

D

G

S

Absolute Maximum Ratings T

= 25°C unless otherwise noted

A

Symbol Parameter NDS352AP Units

V

DSS

V

GSS

I

D

Drain-Source Voltage -30 V
Gate-Source Voltage - Continuous ±20 V
Maximum Drain Current - Continuous (Note 1a)

±0.9 A

- Pulsed ±10

P

D

TJ,T

Maximum Power Dissipation (Note 1a) 0.5 W

(Note 1b)

Operating and Storage Temperature Range -55 to 150 °C

STG

0.46

THERMAL CHARACTERISTICS

R

θ

R

θ

© 1997 Fairchild Semiconductor Corporation

Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W

JA

Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W

JC

NDS352AP Rev.D

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BV
I

DSS

I

GSSF

I

GSSR

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current

VDS = -24 V, V

GS

= 0 V

TJ =125°C

-1 µA

-10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse

VGS = -20 V, VDS = 0 V

-100 nA

ON CHARACTERISTICS (Note 2)

V

GS(th)

Gate Threshold Voltage

VDS = VGS, ID = -250 µA

-0.8 -1.7 -2.5 V

TJ =125°C -0.5 -1.4 -2.2

R

DS(ON)

Static Drain-Source On-Resistance

VGS = -4.5 V, ID = -0.9 A

0.45 0.5

Ω

TJ =125°C 0.65 0.7

0.25 0.3

1.9 S

I
g

D(ON)

FS

VGS = -10 V, ID = -1 A

On-State Drain Current VGS = -4.5 V, VDS = -5 V -2 A

Forward Transconductance

VDS = -5 V, I

= -0.9 A

D

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 88 pF

VDS = -15 V, VGS = 0 V,
f = 1.0 MHz

Reverse Transfer Capacitance 40 pF

135 pF

SWITCHING CHARACTERISTICS (Note 2)

t

d(on)

t

r

t

d(off)

t

f

t

d(on)

t

r

t

d(off)

t

f

Q

g

Q

gs

Q

gd

Turn - On Delay Time VDD = -6 V, ID = -1 A,
Turn - On Rise Time 17 30 ns

VGS = -4.5 V, R

GEN

= 6 Ω

5 10 ns

Turn - Off Delay Time 35 70 ns
Turn - Off Fall Time 30 60 ns
Turn - On Delay Time VDD = -10 V, ID = -1 A,
Turn - On Rise Time

VGS = -10 V, R

GEN

= 50 Ω

Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge 0.5 nC

VDS = -10 V, ID = -0.9 A,
VGS = -4.5 V

8 15
16 30
35 90
30 90

2 3 nC

ns
ns
ns
ns

Gate-Drain Charge 1 nC

NDS352AP Rev.D

Electrical Characteristics (T

TJ−

T

TJ−

T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

I

SM

V

SD

Maximum Continuous Source Current -0.42 A
Maximum Pulsed Drain-Source Diode Forward Current -10 A

Drain-Source Diode Forward Voltage

VGS = 0 V, IS = -0.42 (Note 2)

-0.8 -1.2 V

Notes:

1. R

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

design while R

is determined by the user's board design.

CA

θ

is guaranteed by

JC

θ

D

Typical R

(t)

R

θJA

using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

JA

θ

a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper.
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.

A

(t)

P

=

1a

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

=

R

θJC+RθCA

A

2

(t)

= I

× R

D

(t)

1b

DS(ON)@T

J

NDS352AP Rev.D

Typical Electrical Characteristics

-5

V = -10V

GS

-4

-3

-2

-7.0

-6.0

-5.5

-5.0

-4.5

-4.0

-3.5

-1

D

I , DRAIN-SOURCE CURRENT (A)

0

V , DRAIN-SOURCE VOLTAGE (V)

DS

Figure 1. On-Region Characteristics.

1.6

I = -0.9A

D

1.4

V = -4.5V

GS

1.2

1

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

Figure 3. On-Resistance Variation

with Temperature.

-3.0

1.6

V = -3.5 V

GS

1.4

1.2

1

0.8

DS(on)

R , NORMALIZED

0.6

DRAIN-SOURCE ON-RESISTANCE

-5-4-3-2-10

0.4

-4.0

-4.5

-5.0

I , DRAIN CURRENT (A)

D

-5.5

-6.0

-7.0

-10

-5-4-3-2-10

Figure 2. On-Resistance Variation

with Drain Current and Gate Voltage.

1.6

T = 125°C

1.4

1.2

0.8

DS(on)

0.6

R , NORMALIZED

0.4

DRAIN-SOURCE ON-RESISTANCE

0.2

J

25°C

1

-55°C

V = -4.5V

GS

I , DRAIN CURRENT (A)

D

-4-3-2-10

Figure 4. On-Resistance Variation

with Drain Current and Temperature.

-4

V = -10V

DS

-3.2

-2.4

-1.6

D

I , DRAIN CURRENT (A)

-0.8

V , GATE TO SOURCE VOLTAGE (V)

GS

Figure 5. Transfer Characteristics.

T = -55°C

J

1.2

25

125

-6-5-4-3-2-1

1.1

1

0.9

0.8

GATE-SOURCE THRESHOLD VOLTAGE

0.7

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

Figure 6. Gate Threshold Variation

with Temperature.

NDS352AP Rev.C

Typical Electrical Characteristics (continued)

1.1

1.08

I = -250µA

D

1.06

1.04

1.02

1

DSS

0.98

BV , NORMALIZED

0.96

DRAIN-SOURCE BREAKDOWN VOLTAGE

0.94

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Breakdown Voltage Variation with

Temperature.

400
300

200

100

50

CAPACITANCE (pF)

f = 1 MHz
V = 0 V

30

20

GS

0.1 0.2 0.5 1 2 5 10 20 30

-V , DRAIN TO SOURCE VOLTAGE (V)
DS

C

C

C

iss

rss

oss

4

V = 0V

GS

1

0.1

0.01

0.001

S

-I , REVERSE DRAIN CURRENT (A)

0.0001
0 0.2 0.4 0.6 0.8 1 1.2 1.4

T = 125°C

J

25°C

-55°C

-V , BODY DIODE FORWARD VOLTAGE (V)

SD

Figure 8. Body Diode Forward Voltage Variation with

Source Current and Temperature.

10

I = -0.9A

D

8

6

4

2

GS

-V , GATE-SOURCE VOLTAGE (V)
0

0 1 2 3 4 5

Q , GATE CHARGE (nC)

g

V = -5V

DS

-10

-15

Figure 9. Capacitance Characteristics.

V

DD

V

IN

D

V

GS

R

GEN

G

S

Figure 11. Switching Test Circuit.

Figure 10. Gate Charge Characteristics.

t t

on off

t

d(on)

R

L

V

OUT

V

OUT

r

90%

10%

t

d(off)

90%

10%

tt

f

DUT

90%

V

IN

50%

50%

10%

PULSE WIDTH

INVERTED

Figure 12. Switching Waveforms.

NDS352Ap Rev.C

Typical Electrical Characteristics (continued)

3

V = - 5V

DS

2.5

2

1.5

1

0.5

FS

g , TRANSCONDUCTANCE (SIEMENS)

0

I , DRAIN CURRENT (A)

D

T = -55°C

J

25°C

125°C

Figure 13. Transconductance Variation with Drain

Current and Temperature.

1

0.8

0.6

1a

1b

1b

0.4

0.2

0

STEADY-STATE POWER DISSIPATION (W)

0 0.1 0.2 0.3 0.4

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air

2

2

20
10

5
2

1

0.5

0.1

D

0.05

-I , DRAIN CURRENT (A)

0.01

-5-4-3-2-10

0.1 0.2 0.5 1 2 5 10 20 30 50

RDS(ON) LIMIT

V = -4.5V

GS

SINGLE PULSE

R = See Note 1b

JA

θ

A

T = 25°C

A

- V , DRAIN-SOURCE VOLTAGE (V)

DS

DC

1ms

10ms

100ms

1s

10s

Figure 14. Maximum Safe Operating Area.

1.2

1.1

1

0.9

1a

0.8

1b

0.7

D

-I , STEADY-STATE DRAIN CURRENT (A)

0.6
0 0.1 0.2 0.3 0.4

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air
V = -4.5V

GS

2

Figue 15. SuperSOT

TM _

3 Maximum

Steady-State Power Dissipation versus

Figure 16. Maximum Steady-State Drain

Current versus Copper Mounting Pad Area.

Copper Mounting Pad Area.

1

D = 0.5

0.5

R (t) = r(t) * R

JA

0.2

0.2

0.1

0.1

0.05

0.05

0.02

0.02

0.01

0.01

0.005

r(t), NORMALIZED EFFECTIVE

0.002

TRANSIENT THERMAL RESISTANCE

0.001

0.0001 0.001 0.01 0.1 1 10 100 300

Single Pulse

t , TIME (sec)

1

θ

R = See Note 1b

θJA

P(pk)

t

1

t

2

T - T = P * R (t)

J

A

Duty Cycle, D = t /t

Figure 17. Transient Thermal Response Curve.

Note : Characterization performed using the conditions described in note 1b. Transient thermal response will

change depending on the circuit board design.

JA

θ

θ

JA

1

2

NDS352Ap Rev.C