Datasheet NDS332P Datasheet (Fairchild)

June 1997

NDS332P
P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description Features

These P-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. These
devices are particularly suited for low voltage applications such as
notebook computer power management, portable electronics,
and other battery powered circuits where fast high-side
switching, and low in-line power loss are needed in a very small
outline surface mount package.

-1 A, -20 V, R
R

Very low level gate drive requirements allowing direct
operation in 3V circuits. V

Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.

High density cell design for extremely low R
Exceptional on-resistance and maximum DC current

capability.
Compact industry standard SOT-23 surface Mount

package.

________________________________________________________________________________

= 0.41 Ω @ VGS= -2.7 V

DS(ON)

= 0.3 Ω @ V

DS(ON)

GS(th)

GS

< 1.0V.

= -4.5 V.

DS(ON)

.

D

G

S

Asolute Maximum Ratings T

Symbol Parameter NDS332P Units

V

DSS

V

GSS

I

D

P

D

TJ,T

THERMAL CHARACTERISTICS

R

JA

θ

R

JC

θ

Drain-Source Voltage -20 V
Gate-Source Voltage - Continuous ±8 V
Drain Current - Continuous (Note 1a) -1 A

- Pulsed -10
Maximum Power Dissipation (Note 1a) 0.5 W

(Note 1b)

Operating and Storage Temperature Range -55 to 150 °C

STG

Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W

= 25°C unless otherwise noted

A

0.46

© 1997 Fairchild Semiconductor Corporation

NDS332P Rev. E

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BV
I

DSS

I

GSS

I

GSS

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -20 V
Zero Gate Voltage Drain Current

Gate - Body Leakage Current
Gate - Body Leakage Current

VDS = -16 V, V

GS

= 0 V

TJ = 55°C
VGS = 8 V, VDS= 0 V 100 nA
VGS = -8 V, VDS= 0 V -100 nA

-1 µA

-10 µA

ON CHARACTERISTICS (Note 2)

V

R

GS(th)

DS(ON)

Gate Threshold Voltage VDS = VGS, ID = -250 µA -0.4 -0.6 -1 V

-0.3 -0.45 -0.8

0.35 0.41

0.5 0.74

Static Drain-Source On-Resistance

TJ =125°C
VGS = -2.7 V, ID = -1 A

TJ =125°C

Ω

VGS = -4.5 V, ID = -1.1 A 0.26 0.3

I

D(ON)

On-State Drain Current VGS = -2.7 V, VDS = -5 V -1.5 A

VGS = -4.5 V, VDS = -5 V -2.5

g

F

S

Forward Transconductance

VDS = -5 V, ID= -1 A

2.2

S

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 105 pF

VDS = -10 V, VGS = 0 V,
f = 1.0 MHz

Reverse Transfer Capacitance 40 pF

195 pF

SWITCHING CHARACTERISTICS (Note 2)

t
t
t
t
Q
Q
Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time VDD = -6 V, ID = -1 A,
Turn - On Rise Time 30 45 ns

VGS = -4.5 V, R

GEN

= 6 Ω

8 15 ns

Turn - Off Delay Time 25 45 ns
Turn - Off Fall Time 27 45 ns
Total Gate Charge VDS = -5 V, ID = -1 A,

Gate-Source Charge 0.5 nC

VGS = -4.5 V

3.7 5 nC

Gate-Drain Charge 0.9 nC

NDS332P Rev. E

Electrical Characteristics (T

TJ−

T

θJA

TJ−

T

θJC

θCA

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

Notes:

1. R
design while R

P

Typical R

Maximum Continuous Source Current -0.42 A
Drain-Source Diode Forward Voltage

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

D

is determined by the user's board design.

CA

θ

A

(t)

=

(t)

R

using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

JA

θ

a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper.
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.

A

2

=

+

R

R

(t)

= I

× R

DS(ON)@T

D

(t)

J

VGS = 0 V, IS = -0.42 A (Note 2)

-0.75 -1.2 V

is guaranteed by

JC

θ

1a 1b

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

NDS332P Rev. E

Typical Electrical Characteristics

D

J

D

-2.5

V = -4.5V

-1.5

GS

-3.5

-2

-1

-2.5

-2.7 -3.0

-2.0

-1.5

-0.5

D

I , DRAIN-SOURCE CURRENT (A)

0

V , DRAIN-SOURCE VOLTAGE (V)

DS

Figure 1. On-Region Characteristics.

1.8

I = -1A

D

1.6

V = -2.7

GS

1.4

1.2

1

DS(ON)

0.8

R , NORMALIZED

0.6

DRAIN-SOURCE ON-RESISTANCE

0.4

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

1.8

1.6

V =-2.0V

1.4

GS

1.2

1

0.8

DS(ON)

R , NORMALIZED

0.6

DRAIN-SOURCE ON-RESISTANCE

-3-2.5-2-1.5-1-0.50

0.4

-2.5

-2.7

-3.0

I , DRAIN CURRENT (A)

-3.5

-4.5

-3-2.5-2-1.5-1-0.50

Figure 2. On-Resistance Variation

with Drain Current and Gate Voltage.

1.8

V = -2.7 V

GS

1.6

1.4

1.2

1

DS(on)

0.8

R , NORMALIZED

0.6

DRAIN-SOURCE ON-RESISTANCE

0.4

T = 125°C

J

25°C

-55°C

I , DRAIN CURRENT (A)

-3-2.5-2-1.5-1-0.50

Figure 3. On-Resistance Variation

with Temperature.

-1.5

V = - 3V

DS

-1.2

-0.9

-0.6

D

I , DRAIN CURRENT (A)

-0.3

0

V , GATE TO SOURCE VOLTAGE (V)

GS

Figure 5. Transfer Characteristics.

T = -55°C

J

25°C

125°C

Figure 4. On-Resistance Variation

with Drain Current and Temperature.

1.15

V = V

GS

1.1

1.05

1

0.95

th

V , NORMALIZED

0.9

0.85

GATE-SOURCE THRESHOLD VOLTAGE (V)

-2-1.75-1.5-1.25-1-0.75-0.5

0.8

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

DS

I = -250µA

D

Figure 6. Gate Threshold Variation

with Temperature.

NDS332P Rev.E

Typical Electrical Characteristics (continued)

DS

1.12

I = -250µA

D

1.08

1.04

1

DSS

BV , NORMALIZED

0.96

DRAIN-SOURCE BREAKDOWN VOLTAGE

0.92

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Breakdown Voltage Variation with

Temperature.

500

300
200

100

CAPACITANCE (pF)

50

f = 1 MHz

30

V = 0V

GS

20

0.1 0.2 0.5 1 2 5 10 20

-V , DRAIN TO SOURCE VOLTAGE (V)

C

C

C

iss

oss

rss

1

V =0V

GS

0.1

0.05

0.01

0.001

S

-I , REVERSE DRAIN CURRENT (A)

0.0001
0 0.2 0.4 0.6 0.8 1

T = 125°C

J

25°C

-55°C

-V , BODY DIODE FORWARD VOLTAGE (V)

SD

Figure 8. Body Diode ForwardVoltageVariation with

Source Current and Temperature.

5

I = -1A

D

4

3

2

1

GS

-V , GATE-SOURCE VOLTAGE (V)
0

0 1 2 3 4 5

Q , GATE CHARGE (nC)

g

V = -5V

DS

-10V

-15V

Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics.

t t

on off

t

r

d(off)

90%

10%

50%

50%

PULSE WIDTH

Figure 12. Switching Waveforms.

V

IN

D

V

GS

R

GEN

G

Figure 11. Switching Test Circuit.

V

DD

R

L

V

OUT

t

V

d(on)

OUT

DUT

V

S

IN

10%

90%

90%

10%

tt

f

INVERTED

NDS332PRev. E

Typical Electrical Characteristics (continued)

4

V =- 5V

DS

3

2

1

FS

g , TRANSCONDUCTANCE (SIEMENS)

0

I , DRAIN CURRENT (A)

D

T = -55°C

J

25°C

125°C

Figure 13. Transconductance Variation with

Drain Current and Temperature.

1

0.8

0.6

1a

1b

0.4

0.2

STEADY-STATE POWER DISSIPATION (W)

0

0 0.1 0.2 0.3 0.4

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board
T = 25 C

A

Still Air

2

20
10

5
2

1

0.5

0.1

D

-I , DRAIN CURRENT (A)

0.03

0.01

-3-2.5-2-1.5-1-0.50

0.1 0.2 0.5 1 2 5 10 20 50

RDS(ON) LIMIT

V = -2.7V

GS

SINGLE PULSE

R = See Note 1b

JA

θ

T = 25°C

A

-V , DRAIN-SOURCE VOLTAGE (V)

DS

D

1s

10s

C

1ms

10ms

100ms

Figure 14. Maximum Safe Operating Area.

1.4

1.2

1

1b

1a

0.8

o

D

-I , STEADY-STATE DRAIN CURRENT (A)

0.6
0 0.1 0.2 0.3 0.4

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air
V = -2.7V

GS

2

Figue 15. SuperSOT

TM _

3 Maximum

Steady-State Power Dissipation versus

Figure 16. Maximum Steady-State Drain

Current versus Copper Mounting Pad Area.

Copper Mounting Pad Area.

1

D = 0.5

0.5

R (t) = r(t) * R

JA

0.2

0.2

0.1

0.1

0.05

0.05

0.02

0.02

0.01

0.01

0.005

r(t), NORMALIZED EFFECTIVE

0.002

TRANSIENT THERMAL RESISTANCE

0.001

0.0001 0.001 0.01 0.1 1 10 100 300

Single Pulse

t , TIME (sec)

1

θ

R = See Note 1b

θJA

P(pk)

t

1

t

2

T - T = P * R (t)

J

A

Duty Cycle, D = t /t

Figure 17. Transient Thermal Response Curve.

Note : Characterization performed using the conditions described in note 1b. Transient thermal response will

change depending on the circuit board design.

JA

θ

θ

JA

1

2

NDS332PRev. E

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOS
EnSigna

TM

TM

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FACT Quiet Series™

STAR*POWER is used under license

FAST
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GlobalOptoisolator™
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ISOPLANAR™
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MicroFET™
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MICROWIRE™



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PowerTrench



QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER

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NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:

1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.

PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Formative or
In Design

First Production

Full Production

2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or

effectiveness.

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H4