Datasheet N74F524N, N74F524D Datasheet (Philips)

INTEGRATED CIRCUITS

74F524

8-bit register comparator (open-collector
+ 3-State)

Product specification
IC15 Data Handbook




1990 Aug 07

Philips Semiconductors Product specification

74F5248-bit register comparator (open collector + 3-State)

FEA TURES

•8-Bit bidirectional register with bus-oriented input-output

•Independent serial input-output to register

•Register bus comparator with ‘equal to’, ‘greater than’ and

‘less than’ outputs

•Cascadable in groups of 8-bits

•Open collector comparator outputs for AND-wired expansion

•Two’ s complement or magnitude compare

DESCRIPTION

The 74F524 is an 8-bit bidirectional register with parallel input and
output, plus serial input and output progressing from MSB to LSB.
All data inputs, serial and parallel, are loaded by the rising edge of
the clock. The device functions are controlled by two control lines
(S0, S1) to execute shift, load, hold and read out. An 8-bit
comparator examines the data stored in the registers and on the
data bus. Three true-High, open collector outputs representing
‘register equal to bus’, ‘register greater than bus’ and ‘register less
than bus’ are provided. These outputs can be disabled to the OFF
state by the use of Status Enable (SE
been provided to allow Two’s Complement as well as magnitude
compare. Linking inputs are provided for expansion to longer words.

). A mode control has also

PIN CONFIGURATION

S0

1

I/O0

2
3

I/O1
I/O2

4

I/O3

5

I/O4

6

I/O5

7

I/O6

8

I/O7

9

GND CP

TYPE TYPICAL f

TYPICAL SUPPL Y CURRENT

MAX

74F524 65MHz 110mA

20
19
18
17
16
15
14
13
12
1110

SF00970

V

CC

S1
SE

C/SI
C/SO

EQ
GT
LT
M

(TOTAL)

ORDERING INFORMATION

COMMERCIAL

DESCRIPTION

20-pin plastic DIP N74F524N SOT146-1

20-pin plastic SOL N74F524D SOT163-1

RANGE

V

= 5V ±10%,

CC

T

= 0°C to +70°C

amb

PKG DWG #

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

74F(U.L.)

HIGH/LOW

I/On Parallel data inputs 3.5/1.0 70µA/0.6mA
S0, S1 Mode select inputs 1.0/1.0 20µA/0.6mA
C/SI Status priority or serial data input 1.0/1.0 20µA/0.6mA
CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
SE Status enable input (active Low) 1.0/1.0 20µA/0.6mA
M Compare mode select input 1.0/1.0 20µA/0.6mA
I/On 3-state parallel data outputs 150/40 3.0mA/24mA
C/SO Status priority or serial data output 50/33 1.0mA/20mA
LT Register less than bus output OC/33 OC/20mA
EQ Register equal to bus output OC/33 OC/20mA
GT Register greater than bus output OC/33 OC/20mA

NOTE:

One (1.0) FAST Unit Load (U.L.) is defined as 20µA in the High state and 0.6mA in the Low state.
OC=Open Collector

LOAD VALUE

HIGH/LOW

1990 Aug 07 853–0373 00135

2

Philips Semiconductors Product specification

74F5248-bit register comparator (open collector + 3-State)

LOGIC SYMBOL for 74F456

12 18

MSE

C/SO 16

LT
GT
EQ

13
14
15

SF00971

1
19
11

VCC= Pin 20
GND = Pin 10

C/SI17
S0
S1
CP

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

23456789

LOGIC SYMBOL (IEEE/IEC) for 74F456

COMP

1

19

12

17
18

0
1

11

2
3

4
5
6

7
8
9

C4/2/4
M5 MAGNITUDE
M6 TWO’s COMPLEMENT

&

M

3, 4D

G7

0
3

0=HOLD
1=READ
2=SHIFT
3=LOAD

1,5,6,7>I/O
1,5,6,7<I/O

1,5,6,7=I/O

2D

16

13
14
15

SF00972

FUNCTIONAL DESCRIPTION

The 74F524 contains eight D-type flip-flops connected as a shift
register with provision for either parallel or serial loading. Parallel
data may be read from or loaded into the registers via the data bus
I/O0–I/O7. Serial data is loaded into the register from the C/SI input
and may be shifted through the register and out through the C/SO
output. Both parallel and serial data entry occurs on the rising edge
of the clock (CP). The operation of the shift register is controlled by
two signals, S0 and S1, according to the Select Function Table. The
3-State parallel output buffers are enabled only in the READ mode.

SELECT FUNCTION TABLE

S0 S1 OPERATION

L L HOLD–Retains data in shift register
L H READ–Read contents in register onto data bus

H L SHIFT–Allows serial shifting on next rising clock

edge

H H LOAD–Load data on bus into register

H = High voltage level
L = Low voltage level

One port of an 8-bit comparator is attached to the data bus while the
other port is tied to the outputs of the internal register. Three
active-OFF Open Collector outputs indicate whether the contents
held in the shift register are ‘greater than’ (GT). ‘less than’ (LT), or
‘equal to’ (EQ) the data on the input bus. A High signal on the Status
Enable (SE

) input disables these outputs to the OFF state. A mode
control (M) input allows selection between a straightforward
magnitude compare or a comparison between Two’s complement
numbers.

NUMBER REPRESENTA TION SELECT TABLE

M OPERATION

L Magnitude compare

H Two’s Complement compare

H = High voltage level
L = Low voltage level

For ‘greater than’ or ‘less than’ detection, the C/SI input must be
held High, as indicated in the Function Table. The internal logic is
arranged such that a Low signal on the C/SI input places the
‘greater than’ and ‘less than’ outputs in their off state. (Note that this
off state serves also as the active state when C/SI is High. It is
intended for use in expansion to word lengths greater than 8 bits
using multiple 74S524s as explained in the next 3 paragraphs.) The
C/SO output will be forced High if the ‘equal to’ status condition
exists; otherwise, C/SO will be held Low.

Word length expansion (in groups of 8 bits) can be achieved by
connecting the C/SO output of the more significant byte to the C/SI
input of the next less significant byte and also to its own SE
(see Application Figure 1). The CS/I input of the most significant
device is held High while the SE

input of the least significant device
is held Low. The corresponding status outputs are AND-wired
together. In the case of two’s complement number compare, only the
Mode input to the most significant device should be High. the Mode
inputs to all other cascaded devices are held Low.

Suppose that an inequality condition is detected in the most
significant device. Assuming that the byte stored in the register is
greater than the byte on the data bus, then the EQ and LT outputs
will be pulled Low, whereas the GT output will float High. Also, the

input

1990 Aug 07

3

Philips Semiconductors Product specification

OPERATING MODE

Hold

Read

Load

(GT=CT=off)

(GT=CT=on)

74F5248-bit register comparator (open collector + 3-State)

CS/O output of the most significant device will be forced Low,
disabling the subsequent devices but enabling its own status
outputs. The corrected status condition is thus indicated. The same
applies if the register byte is less than the data byte, only in this
case the EQ and GT outputs go Low, whereas the LT output floats
High.

If an equality condition is detected in the most significant device, its
C/SO output is forced High. This enables the next less significant

APPLICATION

GREATER THAN

EQUAL TO

LESS THAN
H = TWO’s COMPLEMENT
L = MAGNITUDE

H

RD

WR

MGTEQLT

C/SI

S0 S1 I/O

C/SO

SE

C/SI

device and disables its own status outputs. In this way, the status
output proximity is handed down to the next less significant device
which now effectively becomes the most significant byte. The worst
case propagation delay for a compare operation involving ‘n’
cascaded 74F524s will be when an equality condition is detected in
all but the least significant byte. In this case, the status priority has
to ripple all the way down the chain before the correct status output
is established. Typically, this will take 35+6(n–2) ns.

LL

MGTEQLT

SE

C/SO

S0 S1 I/O

MGTEQLT

C/SI

S0 S1 I/O

SE

C/SO

V

CC

L

MSB

8

8 8LSB

Figure 1. Cascading 74F524s for Comparing Longer Words

FUNCTION TABLE

INPUTS OUTPUTS

SE C/SI S0 S1 Data comparison EQ GT LT C/SO

H H L L X H H H (1)
H L L L X H H H L
H X H L X H H H Q0 Shift
H H L H X H H H (1)
H L L H X H H H L
H H H H X H H H (1)
H L H H X H H H L

L L H or L
L L H or L
L L H or L
L H H or L
L H H or L
L H H or L

2
2
2
2
2
2

(1) = High if I/On=Dn, otherwise Low
2 = Must meet setup and hold time requirements
H = High voltage level
L = Low voltage level
X = Don’t care

H or L
H or L
H or L
H or L
H or L
H or L

2
2
2
2
2
2

OA–OH > I/O0–I/O7 L H H L
OA–OH = I/O0–I/O7 H H H L
OA–OH < I/O0–I/O7 L H H L
OA–OH > I/O0–I/O7 L H L L
OA–OH = I/O0–I/O7 H L L H
OA–OH < I/O0–I/O7 L L H L

Compare

=

=

Compare

=

=

SF01012

1990 Aug 07

4

Philips Semiconductors Product specification

74F5248-bit register comparator (open collector + 3-State)

LOGIC DIAGRAM

1

S0

19

C/SI

S1

SE

18
17

16

C/SO

15

EQ

I/O0

I/O1

I/O2

I/O3

I/O4

2

3

4

5

6

CP
DQQ

CP
DQQ

CP
DQQ

CP
DQQ

CP
DQQ

14

GT

7

I/O5

8

I/O6

9

I/O7

11

CP

12

M

VCC= Pin 20
GND = Pin 10

1990 Aug 07

CP
DQQ

CP
DQQ

CP
DQQ

13

LT

SF00973

5

Philips Semiconductors Product specification

I

Current applied to output in Low output state

SYMBOL

PARAMETER

UNIT

IOHHigh-level output current

IOLLow-level output current

74F5248-bit register comparator (open collector + 3-State)

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL

V
V
I

IN

V

OUT

T
T

CC
IN

OUT

amb
stg

Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in High output state –0.5 to +V

pp

p

Operating free-air temperature range 0 to +70 °C
Storage temperature range –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

V
V
V
I
V

T

CC
IH
IL

IK

OH

amb

Supply voltage 4.5 5.0 5.5 V
High-level input voltage 2.0 V
Low-level input voltage 0.8 V
Input clamp current –18 mA
High-level output voltage L T, EQ, GT only 4.5 V

p

p

Operating free-air temperature range 0 70 °C

PARAMETER RATING UNIT

CC

p

All except I/O 40 mA
I/O only 48 mA

LIMITS

MIN NOM MAX

Not LT, EQ, GT, C/SO –3 mA
C/SO only –1 mA
All except I/O 20 mA
I/O only 24 mA

V

1990 Aug 07

6

Philips Semiconductors Product specification

NO TAG

SYMBOL

PARAMETER

TEST CONDITIONS

NO TAG

UNIT

V

CC

MIN

I/On onl

V

MIN

VOLLow-level output voltage

V

MAX

I

MAX

I

Except I/On

I/On onl

74F5248-bit register comparator (open collector + 3-State)

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

LIMITS

MIN TYP

I

OH

V

V

I

I

IH

I

IL

I

OZH

I

OZL

I

OS

I

CC

OH

IK

High-level output current

LT, EQ, GT
only

C/SO only

High-level output voltage

p

Input clamp voltage VCC = MIN, II = I
Input current at maximum

input voltage
High-level input current

Low-level input current

I/On VCC = MAX, VI = 5.5V 1 mA
Except I/On VCC = MAX, VI = 7.0V 100 µA

p

Off-state output current
High-level voltage applied

Off-state output current
Low-level voltage applied

Short-circuit output

3

current

Except LT,
EQ, GT

Supply current (total) VCC = MAX 110 150 mA

VCC = MIN, VIL = MAX,

y

V

= MIN, V

IH

=

VIL = MAX,

=

IH

VCC = MIN,

=

IL

V

= MIN

IH

,

,

= MAX

OH

IOH=MAX

OL

IK

=

±10%V
±10%V

±5%V

±10%V

±5%V

2.5 V

CC

2.4 V

CC

2.7 3.4 V

CC

CC

CC

VCC = MAX, VI = 2.7V 20 µA
VCC = MAX, VI = 0.5V –0.6 mA

VCC = MAX, VO = 2.7V 70 µA

y

VCC = MAX, VO = 0.5V –0.6 mA

VCC = MAX –60 –150 mA

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I

= 5V, T

CC

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

amb

= 25°C.

, the use of high-speed test apparatus and/or sample-and-hold

OS

of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I

tests should be performed last.

OS

2

MAX

250 µA

0.35 0.50 V

0.35 0.50 V

–0.73 –1.2 V

1990 Aug 07

7

Philips Semiconductors Product specification

74F5248-bit register comparator (open collector + 3-State)

AC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PHL

t

PLH

t

PLH

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Maximum clock frequency Waveform 4 50 65 45 MHz
Propagation delay

I/On to EQ
Propagation delay

I/On to GT
Propagation delay

I/On to LT
Propagation delay

I/On to C/SO
Propagation delay

CP to EQ
Propagation delay

CP to GT
Propagation delay

CP to LT
Propagation delay

CP to C/SO (Load)
Propagation delay

CP to C/SO (Serial shift)
Propagation delay

C/SI to GT
Propagation delay

C/SI to LT
Propagation delay

Sn to C/SO
Propagation delay

SE to EQ
Propagation delay

SE to GT
Propagation delay

SE to LT
Propagation delay

C/SI to C/SO
Propagation delay

M to GT
Propagation delay

M to LT

Output Enable time
Sn to I/On

Output Disable time
Sn to I/On

TEST

CONDITION

VCC = +5V

T

= +25°C

amb

C

= 50pF, RL = 500Ω

L

MIN TYP MAX MIN MAX

Waveform 2

Waveform 2

Waveform 2

Waveform 2

Waveform 4

Waveform 4

Waveform 4

9.0

4.5

8.5

6.5

8.0

6.0

7.0

6.5

11.0

4.0

11.0

10.0

11.0

8.0

11.5

7.5

11.0

9.5

11.0

10.5

13.0

9.0

17.0

8.0

16.0

16.5

16.0

14.0

17.0

11.0

17.0

15.5

17.0

14.0

16.0

14.0

22.0

14.0

20.0

21.0

23.0

18.0

Waveform 4 10.0 16.0 20.0 10.0 21.0 ns

Waveform 4

Waveform 1

Waveform 1

Waveform 2

Waveform 2

Waveform 2

Waveform 2

Waveform 2

Waveform 2

Waveform 2

4.5

8.0

3.0

8.0

3.0

6.5

5.5

3.5

2.5

6.0

3.5

5.0

3.5

4.0

4.0

8.0

8.0

10.0

6.0

10.0

10.5

10.5

10.0

13.0

10.0

15.0

9.0

4.5

6.0

8.0

7.0

4.5

8.0

5.0

8.0

5.5

7.0

7.0

8.0

13.0

11.5

16.0

8.5

17.0

8.5

14.5

17.0

10.5

8.0

13.0

8.0

12.0

8.0

11.0

11.0

18.0

15.5

20.0

12.0

5.0

Waveform

NO TAG

Waveform

4.5

5.5

7.0

9.0

13.0

15.0

NO TAG

Waveform

NO TAG

Waveform

3.0

4.5

5.0

8.0

12.0

12.5

NO TAG

VCC = +5V ± 10%

T

= 0°C to +70°C

amb

C

= 50pF, RL = 500Ω

L

9.0

4.5

8.5

6.5

8.0

6.0

7.0

5.5

10.0

4.0

10.0

10.0

10.0

8.0

5.0

4.5

9.0

2.5

8.0

2.5

6.5

5.5

3.5

2.5

6.0

3.0

5.0

3.0

4.0

4.0

8.0

8.0

10.0

5.0

4.5

5.5

2.0

4.5

18.0

12.0

18.0

16.5

18.0

15.0

17.0

15.0

23.0

15.0

21.0

22.0

24.0

19.0

14.0

12.5

17.0

9.5

18.0

9.5

15.5

18.0

11.5

9.0

14.0

9.0

13.0

9.0

12.0

12.0

19.0

16.5

21.0

13.0

14.0

16.0

13.0

13.5

UNIT

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

1990 Aug 07

8

Philips Semiconductors Product specification

74F5248-bit register comparator (open collector + 3-State)

AC SETUP REQUIREMENTS

LIMITS

T

= +25°C T

amb

SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT

CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

ts(H)
ts(L)

th(H)
th(L)

ts(H)
ts(L)

th(H)
th(L)

ts(H)
ts(L)

th(H)
th(L)

tw(H)
tw(L)

Setup time, High or Low
I/On to CP

Hold time, High or Low
I/On to CP

Setup time, High or Low
S0, S1 to CP

Hold time, High or Low
S0, S1 to CP

Setup time, High or Low
C/SI to CP

Hold time, High or Low
C/SI to CP

CP pulse width,
High or Low

Waveform 3

Waveform 3

Waveform 3

Waveform 3

Waveform 3

Waveform 3

Waveform 4

6.0

6.0
0

0

13.5

10.0
0

0

7.0

7.0
0

0

5.0

10.0

= 0°C to +70°C

amb

6.0

6.0
0

0

15.0

10.0
0

0

7.0

7.0
0

0

5.0

10.0

ns

ns

ns

ns

ns

ns

ns

AC WAVEFORMS

For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.

C/SI

GT, LT

V

M

t

PHL

V

M

t

PLH

V

M

V

SF00974

Waveform 1. Propagation Delay for Inverting Outputs

C/SI,
I/On,

CP

Sn

V

M

(H) th(H)

t

s

V

M

V

M

V

ts(L) th(L)

V

M

V

Waveform 3. Setup and Hold Times

M

M

M

SF00976

SE, C/SI, M

I/On, Sn

EQ, C/SO

GT , LT

Waveform 2. Propagation Delay for Non-Inverting Outputs

t

PHL

V

M

tW(H)

CP

EQ, C/SO,

GT , LT

Waveform 4. Propagation Delay, Clock to Output,

Clock Pulse Width, and Maximum Clock Frequency

V

M

t

PHL

1/f

MAX

tW(L)

V

M

V

M

t

PLH

V

M

V

M

SF00975

V

M

t

PLH

V

M

SF00977

1990 Aug 07

9

Philips Semiconductors Product specification

74F5248-bit register comparator (open collector + 3-State)

AC WAVEFORMS (Continued)

For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.

Sn

I/On

V

t

PZH

M

V

V

M

t

PHZ

M

VOH -0.3V

SF00978

Waveform 5. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

TEST CIRCUIT AND WAVEFORMS

V

CC

R

V

PULSE

GENERATOR

IN

D.U.T.

R

T

Test Circuit for 3-State Outputs

and Open Collector Outputs

SWITCH POSITION

TEST SWITCH

t

PLZ,

t

PZL

closed
Open Collector closed
All other open

V

OUT

L

C

R

L

L

7.0V

0V

NEGATIVE
PULSE

POSITIVE
PULSE

I/On

V

t

PZL

M

V

Sn

V

M

t

PLZ

M

VOL +0.3V

SF00979

Waveform 6. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

90%

10%

t

w

V

M

10%

)

t

THL (tf

)

t

TLH (tr

90%

V

M

t

t

t

w

TLH (tr

THL (tf

10%

)

)

90%

V

M

V

M

90%

10%

AMP (V)

0V

AMP (V)

0V

Input Pulse Definition

DEFINITIONS:

RL= Load resistor;

see AC electrical characteristics for value.

C

= Load capacitance includes jig and probe capacitance;

L

see AC electrical characteristics for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

1990 Aug 07

OUT

of

family

74F

10

INPUT PULSE REQUIREMENTS

V

amplitude

3.0V

M

1.5V

rep. rate

1MHz 500ns

t

w

t

TLHtTHL

2.5ns 2.5ns

SF00980

Philips Semiconductors Product specification

8-bit register comparator (open-collector + 3-State)

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

74F524

1990 Aug 07

11

Philips Semiconductors Product specification

8-bit register comparator (open-collector + 3-State)

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

74F524

1990 Aug 07

12

Philips Semiconductors Product specification

8-bit register comparator (open-collector + 3-State)

NOTES

74F524

1990 Aug 07

13

Philips Semiconductors Product specification

8-bit register comparator (open-collector + 3-State)

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

74F524

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 10-98
Document order number: 9397-750-05131

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yyyy mmm dd

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