Datasheet N74F377AD, N74F377AN Datasheet (Philips)

INTEGRATED CIRCUITS

74F377A

Octal D-type flip-flop with enable

Product specification
IC15 Data Handbook

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1996 Mar 12

Philips Semiconductors Product specification

74F377AOctal D-type flip-flop with enable

FEA TURES

•High impedance inputs for reduced loading (20µA in Low and

High states)

•Ideal for addressable register applications

•Enable for address and data synchronization applications

•Eight edge–triggered D–type flip–flops

•Buffered common clock

•See ’F273A for Master Reset version

DESCRIPTION

The 74F377A has 8 edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common buffered clock (CP) input loads
all flip-flops simultaneously when the Enable (E

The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.

The E

input must be stable one setup time prior to the Low-to-High

clock transition for predictable operation.

•See ’F373 for transparent latch version

•See ’F374 for 3–State version

TYPE

74F377A 165MHz 29mA

ORDERING INFORMATION

PACKAGES

20–pin plastic DIP N74F377AN SOT146-1

20–pin plastic SOL N74F377AD SOT163-1

TYPICAL f

MAX

COMMERCIAL RANGE

VCC = 5V±10%; T

TYPICAL SUPPLY CURRENT (TOTAL)

= 0°C to +70°C

amb

) input is Low.

PKG. DWG. #

INPUT AND OUTPUT LOADING AND FAN–OUT TABLE

PINS DESCRIPTION

D0 – D7 Data inputs 1.0/0.033 20µA/20µA

CP Clock pulse input (active rising edge) 1.0/0.033 20µA/20µA

E Enable input (active–Low) 1.0/0.033 20µA/20µA

Q0 – Q7 Data outputs 50/33 1.0mA/20mA

PIN CONFIGURATION

V

1

E

2

Q0

3

D0

4

D1

5

Q1

6

Q2

7

D2

8

D3

9

Q3

10 11

GND

20
19
18
17
16
15
14
13
12

SF00350

CC

Q7
D7
D6
Q6
Q5
D5
D4
Q4

CP

LOGIC SYMBOL

11

1

V

= Pin 20

CC

GND = Pin 10

CP
E

74F(U.L.)

HIGH/LOW

3 4 7 8 13 14 1817

D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

LOAD VALUE

HIGH/LOW

SF00351

1996 Mar 12 853–0026 16555

2

Philips Semiconductors Product specification

74F377AOctal D-type flip-flop with enable

LOGIC SYMBOL (IEEE/IEC)

1

G1

11

32
4

7

8
13
14
17
18

1C2

2D

LOGIC DIAGRAM

D0 D1 D2 D3

1

E

3478

12
15
16
19

SF00352

FUNCTION TABLE

INPUTS OUTPUTS OPERATING MODE

E CP Dn Qn

l ↑ h H Load “1”

5
6
9

l ↑ l L Load “0”

h
H

↑

X

X
X

no change
no change

Hold (do nothing)

H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High

clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High

clock transition
X = Don’t care
↑ = Low-to-High clock transition

D4 D5 D6 D7

13 14 17 18

11

CP

VCC = Pin 20
GND = Pin 10

DQ

CP

D

CP

2 5 6 9 12 15 16 19

Q0 Q1 Q2 Q3

D

QQ

CP

DQ

CP

DQ

CP

D

CP

Q4 Q5 Q6 Q7

D

QQ

CP

DQ

CP

SF00353

1996 Mar 12

3

Philips Semiconductors Product specification

ICCSupply current (total)

I

V

MAX

2740mA

74F377AOctal D-type flip-flop with enable

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)

SYMBOL

V

V

I

T

V

I

OUT

OUT

amb

T

Supply voltage –0.5 to +7.0 V

CC

Input voltage –0.5 to +7.0 V

IN

Input current –30 to +5 mA

IN

Voltage applied to output in High output state –0.5 to V
Current applied to output in Low output state 40 mA
Operating free air temperature range 0 to +70 °C
Storage temperature range –65 to +150 °C

stg

RECOMMENDED OPERATING CONDITIONS

SYMBOL

V

CC

V

IH

V

IL

I

Ik

I

OH

I

OL

T

amb

Supply voltage
High–level input voltage 2.0 V

Low–level input voltage 0.8 V
Input clamp current –18 mA
High–level output current –1 mA
Low–level output current 20 mA
Operating free air temperature range 0 +70

PARAMETER

PARAMETER RATING UNIT

CC

V

LIMITS UNIT

MIN NOM MAX

4.5 5.0 5.5 V

°C

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

SYMBOL PARAMETER TEST LIMITS UNIT

CONDITIONS

E & CP inputs VCC = MIN, VIL = 0.0V3, ±10%V

V

OH

High-level output voltage VIH = 4.5V3, IOH = MAX ±5%V

Other inputs VCC = MIN, VIL = MAX, ±10%V

VIH = MIN, IOH = MAX ±5%V

V

Low-level output voltage VCC = MIN, VIL = MAX, ±10%V

OL

VIH = MIN, IOL = MAX ±5%V

V

I

IH

I

I

OS

Input clamp voltage VCC = MIN, II = I

IK

I

Input current at maximum input voltage VCC = 0.0V, VI = 7.0V 100 µA

I

High–level input current
Low–level input current

IL

Short circuit output current

pp

4

CCH

I

CCL

VCC = MAX, VI = 2.7V
VCC = MAX, VI = 0.5V
VCC = MAX

=

CC

VCC = MAX 29 43 mA

IK

Notes to DC electrical characteristics

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. To reduce the effect of external noise during test. Special test conditions are not necessary for the ’377A.

= 5V, T

CC

4. Not more than one output should be shorted at a time. For testing I
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

amb

= 25°C.

, the use of high-speed test apparatus and/or sample-and-hold

OS

of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I

tests should be performed last.

OS

1

MIN TYP2MAX

2.5 V

CC

2.7 3.4 V

CC

2.5 V

CC

2.7 V

CC

CC

CC

0.35 0.50 V

0.35 0.50 V

–0.73 -1.2 V

20 µA

–20 µA

–60 –150 mA

1996 Mar 12

4

Philips Semiconductors Product specification

74F377AOctal D-type flip-flop with enable

AC CHARACTERISTICS

LIMITS

T

SYMBOL PARAMETER WAVEFORM

f

MAX

t

PLH

t

PHL

Maximum clock frequency 1 150 165 120 MHz
Propagation delay

CP to Qn

1

AC SETUP REQUIREMENTS

SYMBOL PARAMETER WAVEFORM

ts(H)
ts(L)

th(H)
th(L)

ts(H)
ts(L)

th(H)
th(L)

tw(H)
t

(L)

w

Setup time, High or Low
Dn to CP

Hold time, High or Low
Dn to CP

Setup time, High or Low
E to CP

Hold time, High or Low
E to CP

Clock Pulse width
High or Low

2

2

2

2

1

= +25oC

amb

VCC = +5.0V

C

= 50pF

L

RL = 500Ω

MIN TYP MAX MIN MAX

3.0

4.5

5.0

6.5

8.0

9.0

LIMITS

T

= +25oC

amb

VCC = +5.0V

CL = 50pF
RL = 500Ω

MIN TYP MAX MIN MAX

2.5

2.5

1.0

0.0

3.0

4.0

0.0

0.0

4.0

4.0

T

=0oC to +70oC

amb

VCC = +5.0V ±10%

C

= 50pF

L

RL = 500Ω

2.5

4.0

T

= 0oC to +70oC

amb

VCC = +5.0V ±10%

CL = 50pF
RL = 500Ω

2.5

2.5

1.0

0.0

3.0

4.5

0.0

0.0

5.0

4.0

9.0

10.5

UNIT

ns

UNIT

ns

ns

ns

ns

ns

AC WAVEFORMS

1/f

max

CP

Qn

V

M

tw(H)

PHL

V

M

tw(L)t

V

M

Waveform 1. Propagation Delay, Clock Input to Output, Clock

Pulse Width and Maximum Clock Frequency

NOTE: For all waveforms, VM = 1.5V.

The shaded areas indicate when the input is permitted to change for predictable output
performance.

V

M

t

PLH

V

M

SF00294

D

CP

M

t

ts(L)

V

M

t

h

s

V

V

M

M

th = 0

V

M

SF01237

V

th = 0

ts(H)

M

n

E

V

V

MVM

Waveform 2. Data and Enable

Setup and Hold Times

1996 Mar 12

5

Philips Semiconductors Product specification

74F377AOctal D-type flip-flop with enable

TEST CIRCUIT AND WAVEFORM

V

CC

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

Test Circuit for Open Collector Outputs

SWITCH POSITION

TEST SWITCH

t
t

PLZ
PZL

closed
closed

All other open

7.0V

R

L

R

C

L

L

NEGATIVE
PULSE

POSITIVE
PULSE

90%

10%

V

M

10%

t

THL (tf

t

TLH (tr

90%

V

M

Input Pulse Definition

t

w

V

M

10%

)

)

t

w

t

TLH (tr

t

THL (tf

)

)

90%

V

M

90%

10%

AMP (V)

0V

AMP (V)

0V

DEFINITIONS:

R

= Load resistor;

L

see AC electrical characteristics for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC electrical characteristics for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

OUT

of

family

74F

INPUT PULSE REQUIREMENTS

V

amplitude

3.0V

M

1.5V

rep. rate

1MHz 500ns

t

w

t

TLHtTHL

2.5ns 2.5ns

SF00128

1996 Mar 12

6

Philips Semiconductors Product specification

Octal D-type flip-flop with enable

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

74F377A

1996 Mar 12

7

Philips Semiconductors Product specification

Octal D-type flip-flop with enable

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

74F377A

1996 Mar 12

8

Philips Semiconductors Product specification

Octal D-type flip-flop with enable

74F377A

NOTES

1996 Mar 12

9

Philips Semiconductors Product specification

Octal D-type flip-flop with enable

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

74F377A

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 10-98
Document order number: 9397-750-05121

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