Page 1
INTEGRATED CIRCUITS
74F564
Octal D flip-flop (3-State)
Product specification 1996 Jan 05
IC15 Data Handbook
Page 2
Philips Semiconductors Product specification
74F564Octal D flip-flop (3-State)
FEA TURES
•74F564 is broadside pinout version of 74F534
•Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
•Useful as an Input or Ouput port for Microprocessors
•3-State Ouputs for Bus interfacing
•Common Output Enable
•74F574 is a non-inverting version of 74F564
DESCRIPTION
The 74F564 has a broadside pinout configuration to facilitate PC
board layout and allows easy interface with microprocessors.
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q
output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE
) controls all eight 3-State buffers
independently of the register operation. When OE
register appears at the outputs. When OE
high impedance “off” state, which means they will neither drive nor
load the bus.
) control gates.
is Low, data in the
is High, the outputs are in
PIN CONFIGURATION
1
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10 11
GND
TYPE TYPICAL f
MAX
74F564 180MHz 50mA
20OE
V
CC
Q0
19
18
1
Q
17
Q
2
16
Q
3
15
Q
4
14
5
Q
13
Q
6
12
Q
7
CP
SF01052
TYPICAL SUPPL Y
CURRENT
(TOTAL)
ORDERING INFORMATION
COMMERCIAL RANGE
DESCRIPTION
VCC = 5V ±10%,
T
= 0°C to +70°C
amb
20-Pin Plastic DIP N74F564N SOT146-1
20-Pin Plastic SOL N74F564D SOT163-1
PKG.
DWG #
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
D0 - D7 Data inputs 1.0/1.0 20µA/0.6mA
OE Output Enable input (active Low) 1.0/1.0 20µA/0.6mA
CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
Q0 - Q7 3-State outputs 150/40 3.0mA/24mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
2
D0 D1Q1D2
11 CP
1
OE
Q0
VCC=Pin 20
GND=Pin 10
345678
D5
Q2 Q3D3Q4D4Q5
Q6D6Q7
141516171819
SF01053
9
D7
1213
LOGIC SYMBOL (IEEE/IEC)
1
11
2
3
4
5
6
7
8
9
EN1
C2
2D
1
LOAD VALUE
HIGH/LOW
19
18
17
16
15
14
13
12
SF01054
1996 Jan 05 853-0166 16189
2
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Philips Semiconductors Product specification
OPERATING MODES
74F564Octal D flip-flop (3-State)
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
23456789
D
CP
OE
VCC=Pin 20
GND=Pin 10
CPDQ CPDQ CP Q
11
1
0Q1Q2Q3Q4Q5Q6Q7
Q
CPDQ CPDQ CPDQ CPDQ CPDQ
FUNCTION TABLE
INPUTS
OE CP Dn
L
L
↑
↑
l
h
INTERNAL
REGISTER
L
H
L ↑ X NC NC Hold
H
H
↑
↑
Dn
X
NC
Dn
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-High clock transition
= Not a Low-to-High clock transition
↑
OUTPUTS
Q0 – Q7
H
L
Z
Z
1213141516171819
SF01055
Load and read register
Disable outputs
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
1996 Jan 05
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5.0 mA
Voltage applied to output in High output state –0.5 to +V
Current applied to output in Low output state 48 mA
Operating free-air temperature range 0 to +70 °C
Storage temperature –65 to +150 °C
PARAMETER RATING UNIT
3
CC
V
Page 4
Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
NO TAG
VOHHigh-level output voltage
V
CC
MIN, V
IL
MAX,
VOLLow-level output voltage
V
CC
MIN, V
IL
MAX,
74F564Octal D flip-flop (3-State)
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN NOM MAX
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL PARAMETER TEST CONDITIONS
V
IK
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, T
3. Not more than one output should be shorted at a time. For testing I
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
Supply voltage 4.5 5.0 5.5 V
High-level input voltage 2.0 V
Low-level input voltage 0.8 V
Input clamp current –18 mA
High-level output current –3 mA
Low-level output current 24 mA
Operating free-air temperature range 0 70 °C
LIMITS
UNIT
V
= MIN, V
p
p
VIH = MIN, IOH = MAX
V
= MIN, V
VIH = MIN, IOL = MAX
= MAX,
= MAX,
Input clamp voltage VCC = MIN, II = I
Input current at
maximum input voltage
VCC = MAX, VI = 7.0V 100 µA
IK
±10%V
±5%V
±10%V
±5%V
CC
CC
CC
CC
MIN TYP
NO TAG
MAX
2.4 V
2.7 3.4 V
0.35 0.50 V
0.35 0.50 V
–0.73 –1.2 V
High-level input current VCC = MAX, VI = 2.7V 20 µA
Low-level input current VCC = MAX, VI = 0.5V –0.6 mA
Off-state output current,
High-level voltage applied
Off-state output current,
Low-level voltage applied
Short-circuit output current
Supply current (total)
amb
tests should be performed last.
OS
NO TAG
I
CCH
I
CCL
I
CCZ
= 25°C.
VCC = MAX, VO = 2.7V 50 µA
VCC = MAX, VO = 0.5V –50 µA
VCC = MAX –60 –150 mA
45 65 mA
VCC = MAX
50 75 mA
55 80 mA
, the use of high-speed test apparatus and/or sample-and-hold
OS
1996 Jan 05
4
Page 5
Philips Semiconductors Product specification
74F564Octal D flip-flop (3-State)
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL P ARAMETER
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Clock frequency
Propagation delay
CP to Qn
Output Enable time
to High or Low level
Output Disable time
from High or Low level
AC SETUP REQUIREMENTS
SYMBOL PARAMETER
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)
Setup time,
Dn to CP
Hold time,
Dn to CP
CP pulse width,
High or Low
TEST
CONDITIONS
Waveform
NO TAG
Waveform
NO TAG
Waveform 4
Waveform 5
Waveform 4
Waveform 5
TEST
CONDITIONS
Waveform 3
Waveform 3
Waveform NO TAG
T
= +25°C
amb
VCC = +5V
CL = 50pF, RL = 500Ω
T
= 0°C to +70°C
amb
VCC = +5V ± 10%
CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
160 180 150 MHz
3.5
3.5
2.5
4.0
1.0
1.0
5.0
5.0
4.5
5.5
3.0
2.5
8.0
8.0
7.5
8.0
6.0
5.5
3.0
3.0
2.0
3.5
1.0
1.0
8.5
8.5
8.0
8.5
7.0
6.0
LIMITS
T
= +25°C
amb
VCC = +5V
CL = 50pF, RL = 500Ω
T
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
2.0
2.0
1.0
1.0
3.5
3.5
2.0
2.5
1.5
1.5
3.5
3.5
UNIT
ns
ns
ns
UNIT
ns
ns
ns
AC WAVEFORMS
For all waveforms, VM = 1.5V
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
CP
Q
n
V
M
t
PHL
tW(H)
V
M
tW(L)
V
M
V
M
t
PLH
V
M
SF01051
Waveform 1. Propagation Delay, Clock and Enable Inputs
to Output, Enable, Clock Pulse Widths,
and Maximum Clock Frequency
Dn
Q
n
V
M
t
Waveform 2. Propagation Delay for Data to Outputs
PHL
V
M
t
PLH
V
M
V
M
SF00990
1996 Jan 05
5
Page 6
Philips Semiconductors Product specification
74F564Octal D flip-flop (3-State)
AC WAVEFORMS (Continued)
For all waveforms, VM = 1.5V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Dn
CP
V
V
M
M
V
M
VMV
ts(L)ts(H)
Waveform 3. Data Setup and Hold Times
OE
Qn
V
t
PZL
M
V
M
t
PLZ
V
M
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
V
CC
R
V
PULSE
GENERATOR
IN
R
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t
t
PLZ
PZL
closed
closed
All other open
T
D.U.T.
V
OUT
L
R
C
L
L
M
th(L)th(H)
V
M
SF00993
VOL +0.3V
SF00995
7.0V
NEGATIVE
PULSE
POSITIVE
PULSE
OE
Qn
V
M
t
PZH
V
V
M
t
PHZ
M
VOH -0.3V
SF00994
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
t
90%
10%
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
w
10%
)
)
t
w
t
TLH (tr
t
THL (tf
)
)
90%
90%
V
M
V
M
10%
Input Pulse Definition
0V
AMP (V)
0V
AMP (V)
0V
DEFINITIONS:
R
= Load resistor;
L
see AC electrical characteristics for value.
C
= Load capacitance includes jig and probe capacitance;
L
see AC electrical characteristics for value.
= Termination resistance should be equal to Z
R
T
pulse generators.
1996 Jan 05
OUT
of
family
74F
6
INPUT PULSE REQUIREMENTS
V
amplitude
3.0V
M
1.5V
rep. rate
1MHz 500ns
t
w
t
TLHtTHL
2.5ns 2.5ns
SF00777
Page 7
Philips Semiconductors Product specification
74F564Octal D flip-flop (3-State)
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
1996 Jan 05
7
Page 8
Philips Semiconductors Product specification
74F564Octal D flip-flop (3-State)
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
1996 Jan 05
8
Page 9
Philips Semiconductors Product specification
74F564Octal D flip-flop (3-State)
NOTES
1996 Jan 05
9
Page 10
Philips Semiconductors Product specification
74F564Octal D flip-flop (3-State)
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.
(print code) Date of release: July 1994
Document order number: 9397-750-05138
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