Datasheet N74F50728N, N74F50728D Datasheet (Philips)

INTEGRATED CIRCUITS

74F50728

Synchronizing cascaded dual positive
edge-triggered D-type flip-flop

Positive specification
IC15 Data Handbook

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1990 Sep 14

Philips Semiconductors Product specification

Synchronizing cascaded dual positive
edge-triggered D-type flip-flop

FEA TURES

•Metastable immune characteristics

•Output skew less than 1.5ns

•See 74F5074 for synchronizing dual D-type flip-flop

•See 74F50109 for synchronizing dual J–K positive edge-triggered

flip-flop

•See 74F50729 for synchronizing dual dual D-type flip-flop with

edge-triggered set and reset

•Industrial temperature range available (–40°C to +85°C)

DESCRIPTION

The 74F50728 is a cascaded dual positive edge–triggered D–type
featuring individual data, clock, set and reset inputs; also true and
complementary outputs.

Set (S

Dn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. They set and reset
both flip–flops of a cascaded pair simultaneously. Data must be
stable just one setup time prior to the low–to–high transition of the
clock for guaranteed propagation delays.

74F50728

Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive–going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output. Data entering the 74F50728 requires two
clock cycles to arrive at the outputs.

The 74F50728 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F50728
are: τ ≅ 135ps and T
function of the rate at which a latch in a metastable state resolves
that condition and T
the propensity of a latch to enter a metastable state.

TYPE

74F50728 145 MHz 23mA

≅ 9.8 X 10

0

represents a function of the measurement of

o

TYPICAL f

6

sec where τ represents a

TYPICAL SUPPL Y

max

CURRENT (TOTAL)

ORDERING INFORMATION

ORDER CODE

COMMERCIAL RANGE INDUSTRIAL RANGE

DESCRIPTION

14–pin plastic DIP N74F50728N I74F50728N SOT27-1

14–pin plastic SO N74F50728D I74F50728D SOT108-1

VCC = 5V ±10%, VCC = 5V ±10%,

T

= 0°C to +70°C T

amb

= –40°C to +85°C

amb

PKG DWG #

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS DESCRIPTION

D0, D1 Data inputs 1.0/0.417 20µA/250µA
CP0, CP1 Clock inputs (active rising edge) 1.0/1.0 20µA/20µA
SD0, SD1 Set inputs (active low) 1.0/1.0 20µA/20µA
RD0, RD1 Reset inputs (active low) 1.0/1.0 20µA/20µA

Q0, Q1, Q0, Q1 Data outputs 50/33 1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

74F (U.L.) HIGH/

LOW

LOAD VALUE HIGH/

LOW

September 14, 1990 853-1389 00421

2

Philips Semiconductors Product specification

Synchronizing cascaded dual positive
edge-triggered D-type flip-flop

PIN CONFIGURATION

V

SF00605

212

D1D0

14

CC

13

D1

R
D1

12
11

CP1

10

SD1

9

Q1

87

Q1

SF00606

3

6

R

D0
D0

CP0

D0

S

Q0
Q

0

GND

LOGIC SYMBOL

3
4

1
11
10

13

VCC = Pin 14
GND = Pin 7

IEC/IEEE SYMBOL

4

3

2

1

1
2
3
4
5
6

CP0
SD0

RD0
CP1
SD1

RD1

S

C1

1D

R

Q0 Q0 Q1 Q1

56 98

&

74F50728

LOGIC DIAGRAM

4, 10

SDn

Dn

CPn

R

Dn

Vcc = Pin 14
GND = Pin 7

2, 12

3, 11

1, 13

DQ

Q

CP

NOTE: Data entering the flip–flop requires two clock cycles to

arrive at the output.

SYNCHRONIZING SOLUTIONS

Synchronizing incoming signals to a system clock has proven to be
costly, either in terms of time delays or hardware. The reason for this
is that in order to synchronize the signals a flip–flop must be used to
”capture” the incoming signal. While this is perhaps the only way to
synchronize a signal, to this point, there have been problems with
this method. Whenever the flop’s setup or hold times are violated
the flop can enter a metastable state causing the outputs in turn to
glitch, oscillate, enter an intermediate state or change state in some
abnormal fashion. Any of these conditions could be responsible for
causing a system crash. T o minimize this risk, flip–flops are often
cascaded so that the input signal is captured on the first clock pulse
and released on the second clock pulse (see Fig.1). This gives the
first flop about one clock period minus the flop delay and minus the
second flop’s clock–to–Q setup time to resolve any metastable
condition. This method greatly reduces the probability of the outputs
of the synchronizing device displaying an abnormal state but the
trade-off is that one clock cycle is lost to synchronize the incoming
data and two separate flip–flops are required to produce the
cascaded flop circuit. In order to assist the designer of synchronizing
circuits Philips Semiconductors is offering the 74F50728.

DATA

CLOCK

D Q

CP

Q

DQ

CP

DQ

Q

CP

SF00608

Q OUTPUT

Q

Q OUTPUT

5, 9

6, 8

Qn

Q n

10

11

12

13

September 14, 1990

S

C2

2D

R

9

8

SF00607

SF00609

Figure 1.

The 50728 consists of two pair of cascaded D–type flip–flops with
metastable immune features and is pin compatible with the 74F74.
Because the flops are cascaded on a single part the metastability

3

Philips Semiconductors Product specification

Synchronizing cascaded dual positive
edge-triggered D-type flip-flop

characteristics are greatly improved over using two separate flops
that are cascaded. The pin compatibility with the 74F74 allows for
plug–in retrofitting of previously designed systems.

Because the probability of failure of the 74F50728 is so remote, the
metastability characteristics of the part were empirically determined
based on the characteristics of its sister part, the 74F5074. The
table below shows the 74F5074 metastability characteristics.

Having determined the T

and τ of the flop, calculating the mean

0

time between failures (MTBF) for the 74F50728 is simple. It is,
however, somewhat dif ferent than calculating MTBF for a typical part
because data requires two clock pulses to transit from the input to
the output. Also, in this case a failure is considered of the output
beyond the normal propagation delay.

TYPICAL VALUES FOR τ AND T0 AT VARIOUS VCCS AND TEMPERA TURES

T

= 0°C

amb

τ T
VCC = 5.5V 125ps 1.0 X 109 sec 138ps 5.4 X 106 sec 160ps 1.7 X 105 sec
VCC = 5.0V 115ps 1.3 X 1010 sec 135ps 9.8 X 106 sec 167ps 3.9 X 104 sec
VCC = 4.5V 115ps 3.4 X 1013 sec 132ps 5.1 X 108 sec 175ps 7.3 X 104 sec

0

Suppose a designer wants to use the flop for synchronizing
asynchronous data that is arriving at 10MHz (as measured by a
frequency counter), and is using a clock frequency of 50MHz. He
simply plugs his number into the equation below:

MTBF = e

(t’/t)

/TofCf

I

In this formula, fC is the frequency of the clock, fI is the average
input event frequency , and t’ is the period of the clock input (20
nanoseconds). In this situation the f

will be twice the data

I

frequency of 20 MHz because input events consist of both of low
and high data transitions. From Fig. 2 it is clear that the MTBF is
greater than 10
MTBF is 2.23 X 10

T

amb

τ T

= 25°C

41

seconds. Using the above formula the actual

42

seconds or about 7 X 1034 years.

T

amb

0

τ T

74F50728

= 70°C

0

MEAN TIME BETWEEN FAILURES VERSUS DATA FREQUENCY AT VARIOUS CLOCK FREQUENCY

70

10

Clock = 40MHz

Clock = 50MHz

Clock = 650MHz

Clock = 70MHz

Clock = 80MHz

Clock = 100MHz

Data frequency (Hz)

SF00610

Figure 2.

NOTE: V

CC

= 5V, T

60

10

50

Mean time

between failures

(seconds)

1 billion years

= 25°C, τ =135ps, To = 9.8 X 108 sec

amb

10

40

10

30

10

20

10

10

10

00

10

1K 100K 10M

September 14, 1990

4

Philips Semiconductors Product specification

OUTPUTS

Synchronizing cascaded dual positive
edge-triggered D-type flip-flop

FUNCTION TABLE

INTERNAL

REGISTER

INPUTS

SDn RDn CPn Dn Q Qn Qn

L H X X H H L Asynchronous set

H L X X L L H Asynchronous reset

L L X X X H H Undetermined*
H H ↑ h h H L Load ”1”
H H ↑ l l L H Load ”0”
H H L X NC NC NC Hold

NOTES:

H = High voltage level
h = High voltage level one setup time prior to low–to–high

clock transition
L = Low voltage level
l = Low voltage level one setup time prior to low–to–high

clock transition

NC= No change from the previous setup
X = Don’t care
* = This setup is unstable and will change when either set of

reset return to the high–level
↑ = Low–to–high clock transition.
** = Data entering the flip–flop requires two clock cycles to

arrive at the output (see logic diagram)

74F50728

OPERATING MODE

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)

SYMBOL PARAMETER RATING UNIT

V
V
I

IN

V
I

OUT

T

T

CC
IN

OUT

amb

stg

Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA

Voltage applied to output in high output state –0.5 to V
Current applied to output in low output state 40 mA
Operating free air temperature range Commercial range 0 to +70

Industrial range –40 to +85

Storage temperature range –65 to +150

CC

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS

MIN NOM MAX UNIT

V
V
V
I
I
I
T

CC
IH

IL
Ik
OH
OL

amb

Supply voltage 4.5 5.0 5.5 V
High–level input voltage 2.4 V
Low–level input voltage 0.8 V
Input clamp current –18 mA
High–level output current –3 mA
Low–level output current 20 mA
Operating free air temperature range Commercial range 0 +70

Industrial range –40 +85

V

°C
°C
°C

°C
°C

September 14, 1990

5

Philips Semiconductors Product specification

Synchronizing cascaded dual positive

edge-triggered D-type flip-flop

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

SYMBOL

V

OH

V

OL

V

IK

I

I

I

IH

I

IL

I

OS

I

CC

High-level output voltage VCC = MIN, VIH = MIN I

Low-level output voltage

Input clamp voltage VCC = MIN, II = I
Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA

High–level input current VCC = MAX, VI = 2.7V 20 µA
Low–level input current Dn VCC = MAX, VI = 0.5V -250 µA

Short–circuit output current
Supply current4 (total) VCC = MAX 23 34 mA

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I

4. Measure I

with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.

CC

PARAMETER TEST LIMITS UNIT

OH

I

OL

1

= MAX

= MAX

±10%V

±5%V

±10%V

±5%V

MIN TYP2MAX

2.5 V

CC

2.7 3.4 V

CC

CC

CC

CONDITIONS

VIL = MAX,
VCC = MIN, VIL =

MAX,
VIH = MIN

IK

CPn, SDn, RDn –20 µA

3

= 5V, T

CC

= 25°C.

amb

tests should be performed last.

OS

VCC = MAX, VO = 2.25V -60 -150 mA

, the use of high-speed test apparatus and/or sample-and-hold

OS

74F50728

0.30 0.50 V

0.30 0.50 V

-0.73 -1.2 V

AC ELECTRICAL CHARACTERISTICS

T

= +25°C T

amb

SYMBOL PARAMETER TEST VCC = +5.0V

CONDITION CL = 50pF,

= 500Ω

R

L

MIN TYP MAX MIN MAX MIN MAX

f

max

t

PLH

t

PHL

t

PLH

t

PHL

t

sk(o)

NOTES TO AC ELECTRICAL CHARACTERISTICS

1. | t

PLH

2. Skew lines are valid only under same conditions (temperature, V

Maximum clock frequency Waveform 1 100 145 85 70 ns
Propagation delay

CPn to Qn or Qn
Propagation delay

SDn RDn to Qn or Qn
Output skew

actual –t

actual | for any one output compare to any other output where N and M are either LH or HL.

PHL

1, 2

Waveform 1

Waveform 2
Waveform 4 1.5 1.5 1.5 ns

2.0

2.0

3.5

3.5

, loading, etc.,).

CC

3.8

3.8

5.0

5.0

LIMITS

amb

= 0°C to

T

= –40°C to +85°C

amb

+70°C

VCC = +5.0V ± 10% VCC = +5.0V ± 10%

CL = 50pF,

= 500Ω

R

L

6.0

6.0

8.0

8.0

1.5

2.0

3.0

3.0

6.5

6.5

9.0

8.5

1.5

2.0

3.0

3.0

CL = 50pF,

= 500Ω

R

L

7.5

7.0

10.5

10.0

UNIT

ns

ns

September 14, 1990

6

Philips Semiconductors Product specification

Synchronizing cascaded dual positive
edge-triggered D-type flip-flop

AC SETUP REQUIREMENTS

LIMITS

T

= +25°C T

amb

SYMBOL PARAMETER TEST VCC = +5.0V

CONDITION CL = 50pF,

R

= 500Ω

L

MIN TYP MAX MIN MAX MIN MAX

t

(H)

su

tsu(L)
t

(H)

h

t

(L)

h

t

(H)

w

t

(L)

w

t

(L) SDn, RDn pulse width, low Waveform 2 4.5 4.0 4.5 ns

w

t

rec

Setup time, high or low
Dn to CPn

Hold time, high or low
Dn to CPn

CPn pulse width,
high or low

Recovery time
SDn, RDn to CPn

Waveform 1

Waveform 1

Waveform 2

1.5

1.5

0.0

0.0

3.0

4.0

Waveform 3 3.5 3.5 3.5 ns

amb

= 0°C to

T

amb

+70°C

VCC = +5.0V ± 10% VCC = +5.0V ± 10%

CL = 50pF,

R

= 500Ω

L

2.0

2.0

1.5

1.5

3.5

5.0

2.0

2.0

1.5

1.5

4.0

5.5

74F50728

= –40°C to +85°C

CL = 50pF,

R

= 500Ω

L

UNIT

ns

ns

ns

AC WAVEFORMS

Jn, K

n

CPn

Qn

Qn

V

M

tsu(L) th(L)

V

M

V

t

t

M

PLH

PHL

tw(H)

V

tsu(H) th(H)

1/f

max

V

M

t

(L)

w

V

M

V

M

V

M

V

M

M

t

PHL

t

PLH

V

M

V

M

SF00139

SDn

V

M

RDn

Qn

Qn

Waveform 2. Propagation delay for set and reset to output,

Waveform 1. Propagation delay for data to output, data setup

time and hold times, and clock width, and
maximum clock frequency

Qn, Qn

SDn or RDn

CPn

V

M

t

rec

V

M

SF00603

Qn, Qn

Waveform 4. Output skew

Waveform 3. Recovery time for set or reset to output
NOTES:

For all waveforms, V
The shaded areas indicate when the input is permitted to change for predictable output performance.

= 1.5V.

M

tw(L)

t

PLH

t

PHL

set and reset pulse width

V

M

t

(L)

V

M

w

t

PHL

V

M

t

PLH

V

SF00590

V

M

M

SF00050

V

M

V

M

V

M

V

M

t

sk(o)

September 14, 1990

7

Philips Semiconductors Product specification

Synchronizing cascaded dual positive
edge-triggered D-type flip-flop

TEST CIRCUIT AND WAVEFORMS

V

CC

V

PULSE

GENERATOR

IN

R

T

Test Circuit for Totem-Pole Outputs

DEFINITIONS:

= Load resistor;

R

L

see AC ELECTRICAL CHARACTERISTICS for value.

C

= Load capacitance includes jig and probe capacitance;

L

see AC ELECTRICAL CHARACTERISTICS for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

D.U.T.

V

OUT

R

C

L

L

of

OUT

NEGATIVE
PULSE

POSITIVE
PULSE

family

74F

90%

10%

amplitude

3.0V 1.5V

t

w

V

M

10%

)

t

THL (tf

)

t

TLH (tr

90%

V

M

t

t

t

w

TLH (tr

THL (tf

10%

)

)

90%

V

M

V

Input Pulse Definition

INPUT PULSE REQUIREMENTS

V

M

rep. rate

t

w

1MHz 500ns

74F50728

90%

M

10%

t

TLHtTHL

2.5ns 2.5ns

AMP (V)

0V

AMP (V)

0V

SF00006

September 14, 1990

8

Philips Semiconductors Product specification

Synchronizing cascaded dual positive edge-triggered
D-type flip-flop

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

74F50728

1990 Sep 14

9

Philips Semiconductors Product specification

Synchronizing cascaded dual positive edge-triggered
D-type flip-flop

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

74F50728

1990 Sep 14

10

Philips Semiconductors Product specification

Synchronizing cascaded dual positive edge-triggered
D-type flip-flop

NOTES

74F50728

1990 Sep 14

11

Philips Semiconductors Product specification

Synchronizing cascaded dual positive edge-triggered
D-type flip-flop

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

74F50728

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 10-98
Document order number: 9397-750-05215

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yyyy mmm dd

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