Page 1
INTEGRATED CIRCUITS
74F50109
Synchronizing dual J-K
positive
edge-triggered flip-flop with metastable
immune characteristics
Product specification
IC15 Data Handbook
1990 Sep 14
Page 2
Philips Semiconductors Product specification
Synchronizing dual J–K
positive edge-triggered
flip-flop with metastable immune characteristics
FEA TURE
•Metastable immune characteristics
•Output skew guaranteed less than 1.5ns
•High source current (I
applications
= 15mA) ideal for clock driver
OH
•Pinout compatible with 74F109
•See 74F5074 for synchronizing dual D-type flip-flop
•See 74F50728 for synchronizing cascaded D-type flip-flop
•See 74F50729 for synchronizing dual D-type flip-flop with
edge-triggered set and reset
TYPE
TYPICAL f
max
74F50109 150MHz 22mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
DESCRIPTION
16–pin plastic DIP N74F50109N SOT38-4
16–pin plastic SO N74F50109D SOT109-1
VCC = 5V ±10%,
T
= 0°C to +70°C
amb
TYPICAL SUPPL Y
CURRENT( TOTAL)
PKG DWG #
PIN CONFIGURATION
LOGIC SYMBOL
74F50109
1
D0
R
J0
2
3
0
K
CP0
4
5
S
D0
Q0
6
Q0
GND
2 14 3 13
4
CP0
J0
5
SD0
1
RD0
12
CP1
11
SD1
15
RD1
Q0 Q0 Q1 Q1
16
V
CC
15
R
D1
14
J1
K1
13
12
CP1
11
SD1
Q1
107
98
Q1
SF00598
J1
K1
K0
INPUT AND OUTPUT LOADING
AND FAN OUT TABLE
74F (U.L.)
PINS DESCRIPTION
HIGH/
LOW
J0, J1 J inputs 1.0/0.417 20µA/250µA
K0, K1 K inputs 1.0/0.417 20µA/250µA
CP0, CP1
SD0, SD1
RD0, RD1
Clock inputs
(active rising edge)
Set inputs
(active low)
Reset inputs
(active low)
1.0/0.033 20µA/20µA
1.0/0.033 20µA/20µA
1.0/0.033 20µA/20µA
Q0, Q1, Q0, Q1 Data outputs 750/33 15mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high
state and 0.6mA in the low state.
LOAD
VALUE
HIGH/LOW
VCC = Pin 16
GND = Pin 8
IEC/IEEE SYMBOL
2
4
3
1
5
14
12
13
15
11
1J
1K
R
S
2J
2K
R
S
6 7 10 9
SF00599
6
C1
7
10
C2
9
SF00600
September 14, 1990 853-1388 00422
2
Page 3
Philips Semiconductors Product specification
Synchronizing dual J–K
positive edge-triggered
flip-flop with metastable immune characteristics
LOGIC DIAGRAM
6, 107, 9
QQ
3, 13
K
2, 14
J
4, 12
CP
5, 11
S
D
1, 15
D
R
VCC = Pin 16
GND = Pin 8
SF00601
DESCRIPTION
The 74F50109 is a dual positive edge-triggered JK-type flip-flop
featuring individual J, K
complementary outputs.
Set (S
D) and reset (RD) are asynchronous active low inputs and
operate independently of the clock (CP) input.
The J and K
are edge–triggered inputs which control the state
changes of the flip–flops as described in the function table.
The J and K
inputs must be stable just one setup time prior to the
low–to–high transition of the clock for guaranteed propagation
delays. The JK
inputs together.
and K
The 74F50109 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F50109
are: τ ≅ 135ps and τ ≅ 9.8 X 10
of the rate at which a latch in a metastable state resolves that
condition and T
propensity of a latch to enter a metastable state.
, clock, set, and reset inputs; also true and
design allows operation as a D flip–flop by tying J
6
sec where τ represents a function
represents a function of the measurement of the
0
device–under–test can be often be driven into a metastable state. If
the Q output is then used to trigger a digital scope set to infinite
persistence the Q
run by continuously operating the devices in the region where
metastability will occur.
When the device–under–test is a 74F74 (which was not designed
with metastable immune characteristics) the waveform will appear
as in Fig. 2.
Fig. 2 shows clearly that the Q
to the Q trigger point. This also implies that the Q or Q
waveshapes may be distorted. This can be verified on an analog
scope with a charge plate CRT. Perhaps of even greater interest are
the dots running along the 3.5V volt line in the upper right hand
quadrant. These show that the Q
though the Q output glitched to at least 1.5 volts, the trigger point of
the scope.
When the device–under–test is a metastable immune part, such as
the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q
output will appear as in Fig. 3. The 74F5074 Q output will not vary
with respect to the Q trigger point even when the a part is driven into
a metastable state. Any tendency towards internal metastability is
resolved by Philips Semiconductors patented circuitry. If a
metastable event occurs within the flop the only outward
manifestation of the event will be an increased clock–to–Q/Q
propagation delay. This propagation delay is, of course, a function of
the metastability characteristics of the part defined by τ and T
The metastability characteristics of the 74F5074 and related part
types represent state–of–the–art TTL technology.
After determining the T
between failures (MTBF) is simple. Suppose a designer wants to
use the 74F50729 for synchronizing asynchronous data that is
arriving at 10MHz (as measured by a frequency counter), has a
clock frequency of 50MHz, and has decided that he would like to
sample the output of the 74F50109 10 nanoseconds after the clock
edge. He simply plugs his number into the equation below:
MTBF = e
In this formula, fC is the frequency of the clock, fI is the average
input event frequency , and t’ is the time after the clock pulse that the
output is sampled (t’ < h, h being the normal propagation delay). In
this situation the fI will be twice the data frequency of 20 MHz
because input events consist of both of low and high transitions.
Multiplying f
clear that the MTBF is greater than 10
formula MTBF is 1.51 X 10
74F50109
output will build a waveform.0 An experiment was
output can vary in time with respect
output did not change state even
and t of the flop, calculating the mean time
0
(t’/t)
/ TofCf
I
by fC gives an answer of 10
I
10
seconds or about 480 years.
15
Hz2. From Fig. 4 it is
10
seconds. Using the above
output
0.
MET ASTABLE IMMUNE CHARACTERISTICS
Philips Semiconductors uses the term ’metastable immune’ to
describe characteristics of some of the products in its FAST family.
Specifically the 74F50XXX family presently consist of 4 products
which displays metastable immune characteristics. This term means
that the outputs will not glitch or display an output anomaly under
any circumstances including setup and hold time violations.
This claim is easily verified on the 74F5074. By running two
independent signal generators (see Fig. 1) at nearly the same
frequency (in this case 10MHz clock and 10.02 MHz data) the
September 14, 1990
SIGNAL GENERATOR
SIGNAL GENERATOR
DQ
CP
TRIGGER
DIGITAL
Q
SCOPE
INPUT
SF00586
Figure 1. Test setup
3
Page 4
Philips Semiconductors Product specification
Synchronizing dual J–K
positive edge-triggered
flip-flop with metastable immune characteristics
COMP ARISON OF METASTABLE IMMUNE AND NON–IMMUNE CHARACTERISTICS
4
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
Figure 2. 74F74 Q output triggered by Q output, Setup and Hold times violated
74F50109
SF00602
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
Figure 3. 74F74 Q output triggered by Q output, Setup and Hold times violated
SF00588
September 14, 1990
4
Page 5
Philips Semiconductors Product specification
Synchronizing dual J–K
positive edge-triggered
flip-flop with metastable immune characteristics
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’
6
8
10
MTBF in seconds
10,000 years
100 years
one year
one week
10
10
10
10
10
10
10
10
12
11
10
9
8
7
6
10
74F50109
10
12
10
14
10
1015 = fCf
I
78910
t’ in nanoseconds
NOTE: VCC = 5V, T
= 25°C, τ =135ps, To = 9.8 X 108 sec
amb
Figure 4.
TYPICAL VALUES FOR τ AND T0 AT VARIOUS VCCS AND TEMPERA TURES
T
= 0°C
amb
V
CC
τ T
0
T
= 25°C
amb
τ T
0
5.5V 125ps 1.0 X 109 sec 138ps 5.4 X 106 sec 160ps 1.7 X 105 sec
5.0V 115ps 1.3 X 1010 sec 135ps 9.8 X 106 sec 167ps 3.9 X 104 sec
4.5V 115ps 3.4 X 1013 sec 132ps 5.1 X 108 sec 175ps 7.3 X 104 sec
FUNCTION TABLE
INPUTS OUTPUTS OPERATING
SD RD CP J K Q Q MODE
L H X X X H L Asynchronous set
H L X X X L H Asynchronous reset
L L X X X H H Undetermined*
H H ↑ X X q q Hold
H H ↑ h l q q Toggle
H H ↑ h h H L Load ”1” (set)
H H ↑ l l L H Load ”0” (reset)
H H ↑ l h q q Hold ’no change”
NOTES:
H = High–voltage level
h = High–voltage level one setup time prior to
low–to–high clock transition
L = Low–voltage level
l = Low–voltage level one setup time prior to
low–to–high clock
transition
q = Lower case indicate the state of the referenced
output prior to the low–to–high clock transition
X = Don’t care
↑ = Low–to–high clock transition
↑
= Not low–to–high clock transition
* = Both outputs will be high if both S
simultaneously
SF00589
τ T
T
= 70°C
amb
0
D and RD go low
September 14, 1990
5
Page 6
Philips Semiconductors Product specification
Synchronizing dual J–K
flip-flop with metastable immune characteristics
positive edge-triggered
74F50109
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in high output state –0.5 to V
Current applied to output in low output state 40 mA
Operating free air temperature range 0 to +70
Storage temperature range –65 to +150
PARAMETER RATING UNIT
CC
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS UNIT
MIN NOM MAX
V
V
V
I
I
I
T
CC
IH
IL
Ik
OH
OL
amb
Supply voltage 4.5 5.0 5.5 V
High–level input voltage 2.0 V
Low–level input voltage 0.8 V
Input clamp current –18 mA
High–level output current –1 mA
Low–level output current 20 mA
Operating free air temperature range 0 +70
V
°C
°C
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
V
OH
V
OL
V
IK
I
I
I
IH
I
IL
I
OS
I
CC
High–level output voltage VCC = MIN, VIL =
Low–level output voltage
Input clamp voltage VCC = MIN, II = I
Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA
High–level input current VCC = MAX, VI = 2.7V 20 µA
Low–level input current Jn, Kn VCC = MAX, VI = 0.5V -250 µA
Short circuit output current
Supply current4 (total) VCC = MAX 22 32 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applic able type.
2. All typical values are at VCC = 5V, T
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. Measure I
with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
CC
PARAMETER TEST LIMITS UNIT
MAX,
VIH = MIN
VCC = MIN, VIL =
MAX,
VIH = MIN
CONDITIONS
IK
I
OH
I
OL
1
= MAX
= MAX
±10%V
±5%V
±10%V
±5%V
MIN TYP2MAX
2.5 V
CC
2.7 3.4 V
CC
CC
CC
0.30 0.50 V
0.30 0.50 V
-0.73 -1.2 V
CPn, SDn, RDn VCC = MAX, VI = 0.5V -20 µA
3
amb
= 25°C.
VCC = MAX -60 -150 mA
September 14, 1990
6
Page 7
Philips Semiconductors Product specification
Synchronizing dual J–K
flip-flop with metastable immune characteristics
positive edge-triggered
74F50109
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5.0V
CONDITION CL = 50pF,
= 500Ω
R
L
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
CL = 50pF,
= 500Ω
R
L
MIN TYP MAX MIN MAX
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
sk(o)
Maximum clock frequency Waveform 1 130 150 90 ns
Propagation delay
CPn to Qn or Qn
Propagation delay
SDn, RDn to Qn or Qn
Output skew
1, 2
Waveform 1
Waveform 2
Waveform 4 1.5 1.5 ns
2.0
2.0
3.5
3.5
3.8
3.8
5.5
5.5
6.0
6.0
8.0
8.0
2.0
2.0
3.0
3.0
6.5
6.5
8.5
8.5
NOTES:
1. | t
actual – tPM actual| for any output compared to any other output where N and M are either LH or HL.
PN
2. Skew times are valid only under same test conditions (temperature, V
, loading, etc.,).
CC
AC SETUP REQUIREMENTS
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5.0V
CONDITION CL = 50pF,
= 500Ω
R
L
MIN TYP MAX MIN MAX
t
(H)
su
t
(L)
su
t
(H)
h
t
(L)
h
t
(H)
w
t
(L)
w
t
(L) SDn or RDn pulse width, low Waveform 2 3.5 4.0 ns
w
t
rec
Setup time, high or low
Jn, K
n to CPn
Hold time, high or low
Jn, Kn to CPn
CPn pulse width,
high or low
Recovery time
S
Dn or RDn to CP
Waveform 1
Waveform 1
Waveform 1
1.5
1.5
1.0
1.0
3.0
4.0
Waveform 3 3.0 3.5 ns
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
CL = 50pF,
= 500Ω
R
L
2.0
2.0
1.5
1.5
3.5
5.0
UNIT
ns
ns
UNIT
ns
ns
ns
September 14, 1990
7
Page 8
Philips Semiconductors Product specification
Synchronizing dual J–K
positive edge-triggered
flip-flop with metastable immune characteristics
AC WAVEFORMS
Jn, K
n
CPn
Qn
Qn
Waveform 1. Propagation delay for data to output, data
V
M
tsu(L) th(L)
V
M
V
t
t
M
PLH
PHL
tw(H)
1/f
max
V
M
V
M
V
M
V
M
tsu(H) th(H)
(L)
t
w
setup time and hold times, and clock
width, and maximum clock frequency
V
V
t
M
M
PHL
t
PLH
V
M
V
M
SF00139
SDn
RDn
Qn
Qn
Waveform 2. Propagation delay for set and reset to output,
t
PLH
t
PHL
tw(L)
V
M
set and reset pulse width
Qn, Qn
74F50109
V
M
t
(L)
t
PHL
t
PLH
w
V
M
V
M
V
M
SF00050
V
M
V
M
V
M
V
M
SDn or RDn
CPn
V
M
t
rec
V
M
SF00603
Waveform 3. Recovery time for set or reset to output
NOTES:
For all waveforms, V
The shaded areas indicate when the input is permitted to change for
= 1.5V.
M
predictable output performance.
TEST CIRCUIT AND WAVEFORM
V
CC
NEGATIVE
PULSE
V
PULSE
GENERATOR
IN
R
T
Test Circuit for Totem-Pole Outputs
D.U.T.
V
OUT
R
C
L
L
POSITIVE
PULSE
Qn, Qn
Waveform 4. Output skew
90%
V
M
10%
)
t
THL (tf
t
)
TLH (tr
90%
V
10%
M
t
sk(o)
V
M
SF00590
t
w
V
M
10%
)
t
TLH (tr
t
)
THL (tf
90%
V
M
t
w
90%
10%
AMP (V)
0V
AMP (V)
0V
DEFINITIONS:
R
= Load resistor;
L
see AC ELECTRICAL CHARACTERISTICS for value.
= Load capacitance includes jig and probe capacitance;
C
L
see AC ELECTRICAL CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
September 14, 1990
OUT
of
family
74F
8
Input Pulse Definition
INPUT PULSE REQUIREMENTS
V
amplitude
3.0V
M
1.5V
rep. rate
1MHz 500ns
t
w
t
TLHtTHL
2.5ns 2.5ns
SF00006
Page 9
Philips Semiconductors Product specification
Synchronizing dual J-K
flip-flop with metastable immune characteristics
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
positive edge-triggered
74F50109
1990 Sep 14
9
Page 10
Philips Semiconductors Product specification
Synchronizing dual J-K
flip-flop with metastable immune characteristics
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
positive edge-triggered
74F50109
1990 Sep 14
10
Page 11
Philips Semiconductors Product specification
Synchronizing dual J-K
positive edge-triggered
flip-flop with metastable immune characteristics
NOTES
74F50109
1990 Sep 14
11
Page 12
Philips Semiconductors Product specification
Synchronizing dual J-K
positiveedge-triggered
flip-flop with metastable immune characteristics
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
74F50109
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05214
yyyy mmm dd
12
Loading...