Datasheet MTE53N50E Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

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by MTE53N50E/D

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Motorola Preferred Device

N–Channel Enhancement–Mode Silicon Gate

This advanced high voltage TMOS E–FET is designed to
withstand high energy in the avalanche mode and switch efficiently .
This new high energy device also offers a drain–to–source diode

TMOS POWER FET

53 AMPERES

500 VOL TS

R

DS(on)

= 0.080 OHM

with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability



is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.

• 2500 V RMS Isolated Isotop Package

• Avalanche Energy Specified

1

4

3

2

• Source–to–Drain Diode Recovery Time Comparable to a Discrete

Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• Very Low Internal Parasitic Inductance

• I

DSS

and V

Specified at Elevated Temperature

DS(on)

• U. L. Recognized, File #E69369

G

MAXIMUM RATINGS

Drain–Source Voltage V
Drain–Gate Voltage (RGS = 1.0 MΩ) V
Gate–Source Voltage — Continuous

Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)

Drain Current — Continuous

Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)

Total Power Dissipation

Derate above 25°C
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy

(VDD = 25 Vdc, VGS = 10 Vdc, IL= 53 Apk, L = 0.29 mH, RG =25Ω)
RMS Isolation Voltage V
Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
ISOTOP is a trademark of SGS–THOMSON Microelectronics.

(TC = 25°C unless otherwise noted)

Rating

D

SOT–227B

1. Source

2. Gate

3. Drain

S

Symbol Value Unit

DSS

DGR

V

GS

V

GSM

I

D

I

D

I

DM
P

D

stg

E

AS

ISO

R

θJC

R

θJA

L

4. Source 2

500 Vdc
500 Vdc

± 20
± 40

53
33

210
460

3.70

–40 to 150 °C

400

2500 Vac

0.28

62.5
260 °C

Vdc
Vpk

Adc

Watts

W/°C

mJ

°C/W

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

 Motorola, Inc. 1996

1

MTE53N50E

)

f = 1.0 MHz)

V

G

)

(

DS

,

D

,

(

S

,

GS

,

ELECTRICAL CHARACTERISTICS

OFF CHARACTERISTICS

Drain–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 250 µAdc)
T emperature Coef ficient (Positive)

Zero Gate Voltage Drain Current

(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)

Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) I

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)

Threshold Temperature Coefficient (Negative)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 26.5 Adc) R
Drain–Source On–Voltage (VGS = Vdc)

(ID = 53 Adc)

(ID = 26.5 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 26.5 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance
Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (1)

Reverse Recovery Time

Reverse Recovery Stored Charge Q

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from contact screw on tab to center of die)

(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance

(Measured from the source lead 0.25″ from package to center of die)

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.

(T

= 25°C unless otherwise noted)

J

Characteristic

(VDS = 25 Vdc, VGS = 0 Vdc,

(VDD = 250 Vdc, ID = 53 Adc,

(VDS = 400 Vdc, ID = 53 Adc,

(IS = 53 Adc, VGS = 0 Vdc, TJ = 125°C)

f = 1.0 MHz

= 10 Vdc,

GS

RG = 4.7 Ω)

VGS = 10 Vdc)

(IS = 53 Adc, VGS = 0 Vdc)

(IS = 53 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/µs)

Symbol Min Typ Max Unit

V

(BR)DSS

I

DSS

GSS

V

GS(th)

DS(on)

V

DS(on)

FS

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

Q

T

Q

1

Q

2

Q

3

V

SD

t

rr

t

a

t

b

RR

L

D

L

S

500

—

—
—

— — 200 nAdc

2.0
—

— 63 80 mOhm

—
—

25 45 — mhos

— 14400 — pF
— 1560 —
— 240 —

— 67 — ns
— 322 —
— 362 —
— 310 —
— 474 700 nC
— 86 —
— 206 —
— 148 —

—
—

— 720 —
— 460 —
— 260 —
— 15 — µC

—
—

— 5.0 — nH

560
550

—
—

3.2
—

—
—

0.95

0.90

3.5

5.0

—
—

10

100

4.0
—

4.8

4.3

1.3
—

—
—

mV/°C

mV/°C

Vdc

µAdc

Vdc

Vdc

Vdc

ns

nH

2

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

MTE53N50E

120

100

80

60

40

, DRAIN CURRENT (AMPS)

D

I

20

0

0

0.16

0.12

0.08

TJ = 25°C

135

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

VGS = 10 V

8 V

6 V

Figure 1. On–Region Characteristics

VGS = 10 V

TJ = 100°C

25°C

5 V

4 V

8

7 V

120

V

≥ 10 V

100

80

60

40

, DRAIN CURRENT (AMPS)

D

I

20

97642

DS

100°C

25°C

0

34

VGS, GATE–T O–SOURCE VOLTAGE (VOLTS)

TJ = –55°C

652

Figure 2. Transfer Characteristics

0.085
TJ = 25°C

0.08

0.075

VGS = 10 V

0.07

0.04

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0

DS(on)

R

0 40 60 80 100 120

20

ID, DRAIN CURRENT (AMPS)

–55°C

Figure 3. On–Resistance versus Drain Current

and T emperature

2.5
VGS = 10 V

ID = 26.5 A

2

1.5

1

(NORMALIZED)

, DRAIN–TO–SOURCE RESIST ANCE

0.5

DS(on)

R

0

–50 0 50 100 150

–25 25 75

TJ, JUNCTION TEMPERATURE (°C)

125

0.065

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0.06

DS(on)

R

ID, DRAIN CURRENT (AMPS)

15 V

6040200 80 120

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

100000

VGS = 0 V

10000

1000

, LEAKAGE (nA)

100

DSS

I

10

1

0 100 300200 400 500

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

TJ = 125°C

100°C

25°C

100

Figure 5. On–Resistance Variation with

Temperature

Motorola TMOS Power MOSFET Transistor Device Data

Figure 6. Drain–T o–Source Leakage Current

versus V oltage

3

MTE53N50E

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I

) can be made from a rudimentary analysis of

G(A V)

the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V

. Therefore, rise and fall times may

SGP

be approximated by the following:
tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V

GSP

GSP

)

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(VGG – V

iss

In (VGG/V

iss

GSP

)]

GSP

)

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off–state condition when cal­culating t
on–state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently , is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

60000

50000

40000

30000

20000

C, CAPACITANCE (pF)

10000

VGS = 0 VVDS = 0 V

C

iss

C

rss

C

iss

C

C

rss

0

50 51015202510

V

GATE–T O–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

GS

V

oss

DS

TJ = 25°C

Figure 7. Capacitance Variation

100000

10000

1000

C, CAPACITANCE (pF)

100

VGS = 0 V

C

iss

C

oss

C

rss

10

DRAIN–TO–SOURCE VOL TAGE (VOLTS)

100 100010

Figure 7b. High V oltage Capacitance Variation

TJ = 25°C

4

Motorola TMOS Power MOSFET Transistor Device Data

12

10

8

6

Q1 Q2

4

QT

V

GS

ID = 53 A
TJ = 25

°

MTE53N50E

V

DS

, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

10000

1000

t, TIME (ns)

100

VDD = 250 V
ID = 53 A
VGS = 10 V
TJ = 25

°

C

t

d(off)

t

r

t

f

t

d(on)

420

350

280

210

140

C

, GATE–T O–SOURCE VOLT AGE (VOLTS)

GS

V

2

V

0

Q3

0

100 200 300

Qg, TOTAL GATE CHARGE (nC)

DS
400

500

70

0

Figure 8. Gate–T o–Source and

Drain–T o–Source Voltage versus Total Charge

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for­ward biased. Curves are based upon maximum peak junc­tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”

Switching between the off–state and the on–state may tra­verse any load line provided neither rated peak current (IDM)
nor rated voltage (V
(tr,tf) do not exceed 10 µs. In addition the total power aver-

) is exceeded and the transition time

DSS

10

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

aged over a complete switching cycle must not exceed
(T

J(MAX)

– TC)/(R

θJC

).

A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli­able operation, the stored energy from circuit inductance dis­sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con­stant. The energy rating decreases non–linearly with an in­crease of peak current in avalanche and peak junction
temperature.

60

VGS = 0 V

50

TJ = 25

°

C

40

30

20

, SOURCE CURRENT (AMPS)

10

S

I

0

VSD, SOURCE–TO–DRAIN VOL TAGE (VOLTS)

Figure 10. Diode Forward V oltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

1.110.90.80.70.60.5

5

MTE53N50E

SAFE OPERATING AREA

1000

VGS = 20 V
SINGLE PULSE
TC = 25

°

100

10

, DRAIN CURRENT (AMPS)

1

D

I

0.1

0.1 1 1000

C

R

LIMIT

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

10

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

100 µs

1 ms

10 ms

dc

100

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1

D = 0.5

0.2

0.1

0.1

0.05

0.02

0.01

0.01

0.001

RESISTANCE (NORMALIZED)

r(t), EFFECTIVE TRANSIENT THERMAL

SINGLE PULSE

400
350

300
250
200
150

AVALANCHE ENERGY (mJ)

100

, SINGLE PULSE DRAIN–TO–SOURCE

AS

50

E

0

25 50 75 100 125 150

TJ, STARTING JUNCTION TEMPERATURE (

Figure 12. Maximum Avalanche Energy versus

Starting Junction T emperature

CHIP

JUNCTION

0.0315 Ω0.1856 Ω0.0629

0.0318 F 0.1239 F 0.9536 F

Ω

AMBIENT

ID = 53 A

°

C)

0.0001

1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)

Figure 13. Thermal Response

di/dt

I

S

t

rr

t

t

a

b

TIME

t

p

0.25 I

S

I

S

Figure 14. Diode Reverse Recovery Waveform

6

Motorola TMOS Power MOSFET Transistor Device Data

P ACKAGE DIMENSIONS

MTE53N50E

A

B

C

Q

34

12

D
E

F

Recommended screw torque: 1.3" 0.2 Nm
Maximum screw torque: 1.5 Nm

G

P

SOT–227B

H

L

R

MN

STYLE 1:

PIN 1. SOURCE

2. GATE

3. DRAIN

4. SOURCE 2

S

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS.

MILLIMETERS

DIMAMIN MAX MIN MAX

31.50 31.70 1.240 1.248

B 7.80 8.20 0.307 0.322
C 4.10 4.30 0.161 0.169
D 14.90 15.10 0.586 0.590
E 30.10 30.30 1.185 1.193
F 38.00 38.20 1.496 1.503

G 4.00 0.157

H 11.80 12.20 0.464 0.480
L 8.90 9.10 0.350 0.358

M 12.60 12.80 0.496 0.503

N 25.20 25.40 0.992 1.000
P 1.95 2.05 0.076 0.080

Q 4.10 0.157

R 0.75 0.85 0.030 0.033
S 5.50 0.217

INCHES

Motorola TMOS Power MOSFET Transistor Device Data

7

MTE53N50E

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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8

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Motorola TMOS Power MOSFET Transistor Device Data

MTE53N50E/D

*MTE53N50E/D*