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MYSON
On-chip output PLL provide clock frequency fine-tune (inverse, duty cycle
Double scan capability for interlaced input.
MTL001
TECHNOLOGY
(Rev. 0.95)
XGA Flat Panel Controller
FEATURES
General
• Auto configuration of sampling clock frequency, phase, H/V center, as well as white ba lance.
• Auto detection of present or non-present or over range sync signals and their polarities.
• Composite sync separation and odd/even field detection of interlaced video.
•
• Selection of serial 2-wire I
• 3.3V supplier, 5V I/O tolerance in 256-pin PQFP or 272-pin BGA package.
2
C or 8-bit direct host interface to 8-bit MCU.
Input Processor
• Single RGB (24-bit) or Dual RGB (48-bit) input rates up to 100MHz.
• Support both non-interlaced and interlaced RGB graphic input signals.
• YUV 4:2:2 or YUV 4:1:1 (CCIR601) interlaced video input.
• Glue-less connection to Philips SAA711x digital video decoder.
• Built-in YUV to RGB color space converter.
• Compliant with digital LVDS/PanelLink TMDS input interface.
• PC input resolution up to XGA 1024x768 @85Hz.
and delay).
Video Processor
• Independent programmable Horizontal and Vertical scaling ratios from 1/32 to 32
• Flexible de-interlacing unit for digital YUV video input data.
• Zoom to full screen resolution of de-interlaced YUV video data stream.
• Built-in programmable gain control for white balance alignments.
• Built-in programmable 8-bit or 10-bit gamma correction table.
• Built-in programmable temporal color dithering.
• Built-in programmable interpolation look-up table.
• Support smooth panning under viewing window change.
Output Processo r
• Single pixel (18/24-bit) or Dual pixel (36/48-bit) per clock digital RGB output.
• Built-in output timing generator with programmable clock and H/V sync.
• Support VGA/SVGA/XGA display resolution.
• Overlay input interface with external OSD controller.
•
Memory Interf ace
• Support 48/32/24 bit bus width, SDRAM/SGRAM x2 or x3 configuration.
• Optional display through internal line buffer without external frame-buffer mem ory.
• Support power down mode.
GENERAL DESCRIPTION
The MTL001 Flat Panel Display (FPD) Controller is an input format converter for TFT-LCD Monitor or LCD
TV application which accepts 15-pin D-sub RGB graphic signals (through ADC), YUV sign als from digital
video decoder or digital RGB graphic signals from PanelLink TMDS receiver. It includes a RGB/YUV input
processor, configurable frame-buffer memory interface, video scaling up/down processor, OSD input
interface and output display processor in 256-pin PQFP or 272-pin BGA package.
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MYSON
video
RGB
To SDRAM/SGRAM
Generator
8-bit MCU
MTV130
OSD
SDRAM/
SGRAM
Decoder
S-Video
MTL001
TECHNOLOGY
BL OCK DIAGRAM
Digital
PC
YUV
Input
RGB
Input
Auto
Calibration
YUV
to
RGB
Mode
Detect
Scale
Down
Frame
Buffer
Control
Host
Interface
To 8-bit MCU
Scale
Up
Gain
Control
Dithering
Gamma
Correct
(Rev. 0.95)
To external OSD
OSD
&
Output
MUX
Output &
Memory
Timing
RGB
output
APPLICA TIONS
LVDS/PanelLink
TMDS Receiver
Composite/
D-sub RGB
graphic signals
Digital
Video
ADC1
ADC2
MTL001
FPD Monitor
Controller
MTV212
TFT-LCD
Flat Panel
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
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MYSON
64* PVDD
63* AVDD
62* AVDD
61* XI
65* PVSS
PVDD *129
PVSS *130
OSDRED *131
OSDGRN *132
OSDBLU *133
OSDEN *134
MTL001
TECHNOLOGY
1. PIN CONNECTION
BA/MA11 *182
MA8 *183
MA7 *184
MA6 *185
MA5 *186
MA4 *187
11* G1IN7/UVIN7
10* DVSS
9* R1IN0/YIN0
8* R1IN1/YIN1
7* R1IN2/YIN2
PVSS *193
PVSS *194
MWE# *195
MCAS# *196
MRAS# *197
DQM1 *198
DQM0 *199
DVSS *200
DVDD *201
MD7 *202
MD6 *203
MD5 *204
MD4 *205
MD3 *206
MD2 *207
MD1 *208
MD0 *209
PVDD *210
MD31 *211
MD30 *212
MD29 *213
MD28 *214
MD27 *215
MD26 *216
MD25 *217
MD24 *218
PVSS *219
AD0 *220
AD1 *221
AD2 *222
AD3 *223
AD4 *224
AD5 *225
AD6 *226
AD7 *227
HCS# *228
PVDD *229
ALE *230
PVSS *231
HWR# *232
HRD# *233
EXTMCLK *234
RST# *235
BUSSEL *236
IRQ *237
GPIO7 *238
GPIO6 *239
GPIO5 *240
GPIO4 *241
GPIO3 *242
GPIO2 *243
GPIO1 *244
GPIO0 *245
EXTDCLK *246
CLAMP *247
HSYNC/CS*248
VSYNC *249
TMDSSEL *250
TDIE/SOG*251
PVDD *252
IPCLK *253
NC *254
PVSS *255
PVSS *256
PVDD *192
MA3 *188
MA2 *189
MA1 *190
MA0 *191
6* R1IN3/YIN3
5* R1IN4/YIN4
4* R1IN5/YIN5
3* R1IN6/YIN6
2* R1IN7/YIN7
1* PVDD
12* G1IN6/UVUN6
(Rev. 0.95)
DQM3/MA10 *149
PVSS *181
MCK *180
MD9 *166
MD8 *167
MCS# *168
DVSS *169
MD39 *170
MD38 *171
MD37 *172
MD36 *173
MD35 *174
MD34 *175
MD33 *176
MD32 *177
MCKE *178
DVDD *179
MD15 *160
MD14 *161
MD13 *162
MD12 *163
MD11 *164
MD10 *165
MD44 *154
MD43 *155
MD42 *156
MD41 *157
MD40 *158
DVDD *159
DQM2/MA9 *148
MD22 *141
MD21 *142
MD20 *143
MD19 *144
MD18 *145
MD17 *146
MD16 *147
DVSS *150
MD47 *151
MD46 *152
MD45 *153
MTL001
(256-pin PQFP)
52* B2IN4
51* B2IN5
50* B2IN6
49* B2IN7
48* PVDD
47* G2IN0
46* G2IN1
45* G2IN2
44* G2IN3
43* G2IN4
42* G2IN5
41* G2IN6
40* G2IN7
39* PVSS
38* R2IN0
37* R2IN1
36* R2IN2
35* R2IN3
34* R2IN4
33* R2IN5
32* R2IN6
31* R2IN7
30* DVDD
29* RGBSEL
28* DVSS
27* B1IN0
26* B1IN1
25* B1IN2
24* B1IN3
23* B1IN4
22* B1IN5
21* B1IN6
20* B1IN7
19* DVDD
18* G1IN0/UVIN0
17* G1IN1/UVIN1
16* G1IN2/UVIN2
15* G1IN3/UVUN3
14* G1IN4/UVIN3
13* G1IN5/UVUN5
OSDINT *135
OVSYNC *136
OHSYNC *138
DVSS *137
DVDD *139
MD23 *140
128* PVSS
127* PVSS
126* OCLK
125* PVDD
124* DDEN
123* DVSYNC
122* DHSYNC
121* DVDD
120* R1OUT0
119* R1OUT1
118* R1OUT2
117* R1OUT3
116* R1OUT4
115* R1OUT5
114* R1OUT6
113* R1OUT7
112* DVSS
111* G1OUT0
110* G1OUT1
109* G1OUT2
108* G1OUT3
107* G1OUT4
106* G1OUT5
105* G1OUT6
104* G1OUT7
103* B1OUT0
102* B1OUT1
101* B1OUT2
100* B1OUT3
99* B1OUT4
98* B1OUT5
97* B1OUT6
96* B1OUT7
95* DVSS
94* DDCLK1
93* DDCLK2
92* DVDD
91* R2OUT0
90* R2OUT1
89* R2OUT2
88* R2OUT3
87* R2OUT4
86* R2OUT5
85* R2OUT6
84* R2OUT7
83* PVDD
82* G2OUT0
81* G2OUT1
80* G2OUT2
79* G2OUT3
78* G2OUT4
77* G2OUT5
76* G2OUT6
75* G2OUT7
74* B2OUT0
73* B2OUT1
72* B2OUT2
71* B2OUT3
70* B2OUT4
69* B2OUT5
68* B2OUT6
67* B2OUT7
66* PVSS
60* XO
59* AVSS
58* AVSS
57* PVSS
56* B2IN0
55* B2IN1
54* B2IN2
53* B2IN3
Note: Pin connection of 272-pin BGA to be defined later
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MYSON
Vertical sync input
MTL001
TECHNOLOGY
(Rev. 0.95)
2. PIN DESCRIPTION
ADC1 Input Inter face (YUV or RGB or TMDS Inpu t Data)
Name Type Pin# Description
VSYNC I 249
HSYNC/CS I 248 Horizontal or Composite sync input
RGBSEL O 29 Input select. 1:RGB input, 0:YUV input
TMDSSEL O 250 TMDS input select, active high
CLAMP O 247 Clamp pulse output for ADC
IPCLK I 253 Input pixel clock
R1IN[7:0]/YIN[7:0] I 2-9 Red or Y channel or TMDS input data (Single/Dual ADC)
G1IN[7:0]/UVIN[7:0] I 11-18 Green or UV channel or TMDS input data (Single/Dual ADC)
B1IN[7:0] I 20-27 Blue channel or TMDS input data (Single/Dual ADC)
TDIE I 251 TMDS digital input enable
ADC2 Input Inter face (RGB Data)
Name Type Pin# Description
R2IN[7:0] I 31-38 Red channel input data (Dual ADC)
or Control bit for YUV video input
Bit 4: VPHREF, Video input Horizontal reference signal
Bit 3: VPVS, Video input VSYNC signal
Bit 2: VPODD, Video input ODD/EVEN field signal
Bit 1: VPHS, Video input HSYNC signal
Bit 0: VPCLK, Video input clock signal
G2IN[7:0] I 40-47 Green channel input data (Dual ADC)
B2IN[7:0] I 49-56 Blue channel input data (Dual ADC)
Displ ay Outp ut Interface
Name Type Pin# Description
DDEN O 124 Display data output enable for LCD panel
DVSYNC O 123 Display Vertical sync output
DHSYNC O 122 Display Horizontal sync output
DDCLK1 O 94 Display output clock for odd data
DDCLK2 O 93 Display output clock for even data
R1OUT[7:0] O 113-120 Red output even data , bit[7:2] for 6-bit panel
G1OUT[7:0] O 104-111 Green output even data , bit[7:2] for 6-bit panel
B1OUT[7:0] O 96-103 Blue output even data , bit[7:2] for 6-bit panel
R2OUT[7:0] O 84-91 Red output odd data , bit[7:2] for 6-bit panel
G2OUT[7:0] O 75-82 Green output odd data , bit[7:2] for 6-bit panel
B2OUT[7:0] O 67-74 Blue output odd data , bit[7:2] for 6-bit panel
Memory Interf ace
Name Type Pin# Description
MCK O 180 Memory output clock
MCKE O 178 Memory clock enable
MCS# O 168 Memory chip select, active low.
MRAS# O 197 Mem ory row address strobe, active low
MCAS# O 196 Mem ory column address strobe, active low
MWE# O 195 Memory write enable, active low
DQM[1:0] O 198-199 Memory data mask byte enable
BA/MA11 O 182 Memory bank address or Memory address line
DQM3/MA10 O 149 SGRAM data mask byte enable or SDRAM address line
DQM2/MA9 O 148 SGRAM data mask byte enable or SDRAM address line
MA[8:0] O 183-191 Memory address line
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MYSON
Vertical sync for external OSD
Horizontal sync for external OSD
OSD intensity input
OSD overlay enable
Oscillator frequency input
Oscillator frequency output
Bit 6: ADHS, Horizontal sync for A/D converter
Input Sync On Green
MTL001
TECHNOLOGY
MD[47:40] I/O 151-158 Memory Blue (B1) data
MD[39:32] I/O 170-177 Memory Green (G1) data
MD[31:24] I/O 211-218 Memory Red (R1) data
MD[23:16] I/O 140-147 Memory Blue (B0) data
MD[15:8] I/O 160-167 Memory Green (G0) data
MD[7:0] I/O 202-209 Memory Red (R0) data
(Rev. 0.95)
Host Interface
Name Type Pin# Descrip tio n
RST# I 235 System reset input, active low.
AD[7:0] I/O 227-220 T he address and da ta bus of 8-bit direct interface or
2-wire I2C series bus
Bit 1: SDA, serial bus data
Bit 0: SCK, serial bus clock
HWR# I 232 Host write strobe , active low
HRD# I 233 Host read strobe, active low
ALE I 230 Host address latch enable for 8-bit direct bus
HCS# I 228 Host chip select
BUSSEL I 236 Bus mode selection. 0: I2C bus, 1: 8-bit direct bus
IRQ O 237 Interrupt request output
OSD Interf ac e
Name Type Pin# Description
OCLK O 126 Clock for external OSD
OVSYNC O 136
OHSYNC O 138
OSDRED I 131 OSD red input
OSDGRN I 132 OSD green input
OSDBLU I 133 OSD blue input
OSDINT I 135
OSDEN I 134
Other Interface
Name Type Pin# Description
XI I 61
XO O 60
EXTDCLK I 246 External display clock input
EXTMCLK I 234 External memory clock input
GPIO[7:0] I/O 238-245 General purpose I/O or
NC - 254 No connection
Bit 7: ADVS, Vertical sync for A/D converter
Bit 2: MA9_SGRAM, Memory address 9 for SGRAM
Bit 0: RAWHS/SOG, Input source HSYNC or
Default: Bit[7:2]: Output direction
Bit[1:0]: Input direction
3.3V Power and Grou n d
Name Pin# Description
DVDD 19, 30, 92, 121, 139, 159, 179, 201 Digital power 3.3V
DVSS 10, 28, 95, 112, 137, 150, 169, 200 Digital ground
PVDD 1, 48, 64, 83, 125, 129, 192, 210, 229, 252 Pad power 3.3V
PVSS 39, 57, 65, 66, 127, 128, 130, 181, 193, 194, Pad ground
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MYSON
MTL001
TECHNOLOGY
219, 231, 255, 256
AVDD 62, 63 Analog power 3.3V
AVSS 58, 59 Analog ground
(Rev. 0.95)
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MYSON
Single Pixel mode, only the ports
The Digital RGB input port works just in the same way as Sec 3.1.1 except that pin
With a flexible single or double
The 16 bit data bus is shared by ports
depending on the type of input images.
MTL001
TECHNOLOGY
(Rev. 0.95)
3. FUNCTIONAL DESCRIPTION
3.1 Input Process or
General Descrip t io n
The function of Input Interface is to provide the interface between MTL001 and external in put devices. It can
process both non-interlaced and interlaced RGB graphic input, YUV video input, and digita l RGB input
compliant with digital LVDS/PanelLink TMDS interface. It also contains the Decimation circuit to scale down
the input image with arbitrary ratios down to 1/32 and the built-in YUV to RGB color space converter.
3.1.1 RGB Inpu t Format
The RGB input port can work in two modes: Single Pixel mode (24 bits) and Double Pixel mode (48 bits). For
R1IN[7:0], G1IN[7:0], and B1IN[7:0] are internally sampled. For Double
Pixel mode, besides the ports R1IN[7:0], G1IN[7:0], and B1IN[7:0], the ports R2IN[7:0], G2IN[7:0], and
B2IN[7:0] are needed additionally. The R/G/B1IN ports are sampled at the rising edge of the RGB input clock,
and the R/G/B2IN ports are sampled at the falling edge.
3.1.2 TMDS Input Form at
“Digital Input Enable
DIEN” is needed.
pixel input interface, the supported format is up to true color, including the 18
bit/pixel or 24 bit/pixel in 1 or 2 pixels/clock mode.
3.1.3 YUV Input Form at
The YUV input port supports interlaced video data from the most common video decoder ICs like SAA711x.
R1IN[7:0] and G1IN[7:0]. The 5 bit control signals are shared with the
port R2IN[4:0]. The 16 bit data is sampled at the rising edge of the shared video clock VPCLK when the
shared data enable HREF is active. The supported formats are YUV4:1:1 and YUV4:2:2 with CCIR601
standard.
3.1.4 YUV to RGB Convert er
It is used to convert YCbCr format into RGB format. The basic equations are as follows:
R = Y + 1.371(Cr – 128)
G = Y – 0.698(Cr – 128) – 0.336(Cb – 128)
B = Y + 1.732(Cb - 128)
3.1.5 De-interlace mod e
For interlace input, MTL001 features several de-interlacing algorithms for processing interlaced video data
¨ Static Mode
In this mode, the first and second fields are simply put together without an y filtering. Memory for two fields is
needed. It is commonly used in still image input.
¨ Tog gl e Mode
In this mode, only one field is displayed at a time. First field and second field is toggling displayed. The
missing lines are calculated from duplicating the neighboring lines. For moving picture, it has a good quality.
¨ Spatial Mod e
In this mode, two fields are toggled displayed, just like Toggle mode. The missing lines are calculated from
interpolating the neighboring lines. This mode has an generally good quality for still and moving picture.
3.1.6 Sync Processor
The V/H SYNC processing block performs the functions of Composite signal separation/insertion, SYNC
inputs the presence check, frequency counting, polarity detection and control. It contains a de-glitch circuit to
filter out any pulse shorter than one OSC period which is treated as noise am ong V/H SYNC pulses.
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MYSON
input sample registers to aid in centering the screen automatically.
s phase and frequency. MTL001
colors. This advanced function helps the firmware to analyze ADC performance. Usually the firmware can
s phase and frequency.
MTL001
TECHNOLOGY
¨ V/H SYNC Frequency Counter
(Rev. 0.95)
MTL001 measures VSYNC/HSYNC frequency counted in the proper clock and save the information in
register. Users can read the figure and calculate VSYNC/HSYNC frequency using the following formulae:
f
= f
= f
osc
osc
/ N
/ N
vsync
f
hsync
Where f
f
f
N
N
¨ V/H SYNC Presenc e Chec k
vsync
hsync
osc
vsync
hsync
51/256
vsync
58
hsync
: VSYNC frequency
: HSYNC frequency
: oscillator clock with 14.31818 MHz
: counted number of VSYNC
: counted number of HSYNC
This function checks the input VSYNC, where Vpre flag is set when VSYNC is over 40Hz or cleared when
VSYNC is under 10Hz and the input is HSYNC, where Hpre flag is set when HSYNC is over 10KHz or
cleared when HSYNC is under 10Hz.
¨ V/H Polari ty Detect
This function detects the input VSYNC/HSYNC high and low pulse duty cycle. If the high pulse duration is
longer than that of low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted.
¨ Comp os it e SYNC separatio n/ins erti on
MTL001 continuously monitors the input HSYNC. If the input VSYNC can be extracted from it, a CVpre flag is
set. MTL001 can insert HSYNC pulse during Composite VSYNC’s active time and the insertion frequency
can adapt to original HSYNC’s.
3.1.7 Aut o Tune
Auto Tune function consists of Auto Position that automatically centering the screen and A uto Calibration
which contains Phase Calibration, Histogram, Min/Max Value, and Pixel Grab described as below. With this
auto adjustment support it is possible to measure the correct phase, frequency, gain, and offset of ADC. The
horizontal and vertical back porches of input image and the horizontal and vertical active reg ions can also be
measured. Firmware can adjust input image registers automatically by reading Auto Tune’s registers in single
or burst mode.
¨ Auto Position
MTL001 provides Horizontal/Vertical back porch and active region values. Users can use these values to set
¨ Phase Calibrati on
MTL001 provides Auto Calibration registers to measure the quality of current ADC’s phase and frequency.
The biggest Auto Calibration registers value means the right value of ADC’
has two kinds of algorithms to calculate Auto Calibration’s value. One is the traditional Difference method, the
other is MYSON’s proprietary method; the latter one is recommended for a better performance.
¨ Histogr am
Histogram means the total number of input pixels below/above one threshold value, for individual R/G/B
use this information to measure ADC’s noise margin, and adjust its offset and gain, or even aid in the mode
detection.
¨ Mi n /Max Value
Min/Max value means minimum or maximum pixel value within the specified input act ive image region for
each RGB channel. This information is usually used to adjust ADC’s offset and gain.
¨ Pixel Grab
Pixel Grab means users can grab a single input pixel at any one point. The position of the point can be
programmed by users. This is another traditional method to measure ADC’
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MYSON
because they share the same line buffers.
: Image will be scaled up/down based on scaling factor. Every point of output image data
image data will be filtered by the
MTL001
TECHNOLOGY
(Rev. 0.95)
3.2 Video Proc ess o r
General Descrip t io n
MTL001 possesses a powerful and programmable video processor b y providing the following functions:
Scaling Up/Down, Gain Control, Brightness Control, Gamma Correction, and Dithering Control.
The block diagram of Video Processor is as follows:
Scaling Factor
SCALING
GAIN
BRIGHTNESS
Transition Table
Gain Factor
Brightness Factor
GAMMA
DITHERING
Fig. 3.2.1 Video Processor Block Diagram
3.2.1 Scaling
MTL001 provides scaling function ranging from 1/32 to 32 for both up and down sca ling, and for both
horizontal and vertical processing. Note that the up and down scaling cannot operate in the same time,
For scaling up, both horizontal and vertical processing, MTL001 provides four methods:
¨ Pass Mod e: Image will be passed through without considering any scaling factor.
¨ Dupl ic ate Mode: Image will be scaled up/down based on scaling factor. Every point of output image
comes from the input. In this method, Output image will have the good contrast but may be nonuniformed.
¨ Bi linear Mode
will be filtered by bilinear filter. In this method, output image will have the good scaling quality but may
be blurred.
Gamma Table
Dithering Table
¨ Interpo l atio n Table Mode: Image will be scaled up/down based on scaling factor. Every point of output
user defined filter.
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MYSON
programming the gain and brightness coefficients. This adjustment is applied to RGB colors individually.
Gamma Correction is used to compensate the non-linearity of LCD display panel. MTL001 contains an 8/10-
true color (8 bits per color) or high color (6 bits per color) display.
MTL001
TECHNOLOGY
Input pixel A B
Interpolation pixel
SC
64
SC’
[a]
63
32
[b]
O
(Rev. 0.95)
[a]: duplicate filter
[b]: bilinear filter
[c]: user defined filter
[c]
32 63
Fig. 3.2.2 Scaling filter
Note: For scaling down, for both horizontal and vertical processing, MTL001 provides three methods: Pass
mode, Duplicate mode, and Bilinear mode.
3.2.2 Gain/Brightness Control
MTL001 provides Gain and Brightness control to adjust the contrast and brightness of output color by
Auto-white balance can be achieved by using this function.
3.2.3 Gamma Correcti on
bit Gamma table to fix this phenomenon. The 10-bit Gamma Table performs a better output quality, and is
commonly used together with dithering function. A traditional 8-bit Gamma correction table can also be used.
3.2.4 Color Dithering
MTL001 supports
In the latter case, users can turn on dithering function to avoid artificial contour due to truncation. The
dithering function works in two modes:
O = [(64-SC’)*A + SC’*B]/64
SC
¨ Static dithering: Dithering coefficient is fixed.
¨ Temporal dithering : Dithering coefficient is time dependent.
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MYSON
Output processor provides the interface for both LCD panel and OSD controller. MTL001 can work for framebuffer or non-frame-buffer mode. When in frame-buffer mode, there is no restriction between the timing of
input and output. When in non-frame-butter mode, output frame rate must be equal to input frame rate and
output display time must be equal to input display time due to the absence of frame buffer. Some features
based on using the frame buffer do not work in non-frame-buffer mode, for example the screen write, static
display timing modes:
Frame SYNC Mode
3.2.3 Display Timing modes
MTL001
TECHNOLOGY
(Rev. 0.95)
3.3 Outpu t Process or
General Descrip t io n
mode in de-interlace etc.
3.3.1 Display Timing Generatio n
There are three
¨ Frame-buf fer Mode: is used for frame rate conversion. External frame buffer is needed.
¨ Non-fr ame-buffer Mode: performs a low cost version of solution where the external frame buffer is not
needed. This mode is used in the condition that output frame rate is equal to input frame; some features
are disabled in this mode.
¨
gives the moving picture a smooth change.
: is used for video input. In this m ode, output frame is synchronized to input frame,
Frame Buff er Mode:
Input Frame
Non Frame Buf f er Mode
Input Frame
x
Lock point
Frame SYNC Mode
Input Frame
x
Lock point
Output Frame
External Frame Buffer
Output Frame
Output Frame
External Frame Buffer
Fig.
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MYSON
Is designed to support TFT panels with single pixel input. Only PORT1 is active. The frequency of DCLK1 is
R1OUT/G1OUT
R1OUT/G1OUT
R2OUT/G2OUT
SINGLE PO RT
3.2.4 Display Data Timing
MTL001
TECHNOLOGY
3.3.2 OSD Overlay
MTL001 allows the integration of overlay data with the scaled output pixel stream. It provides a fully
compatible OSD interface. Individual OSD clock, OSD HSYNC and OSD VSYNC are sent to external OSD
device. MTL003 receives OSD Enable, OSD Red, OSD Green, OSD Blue, and OSD Intensity from external
OSD device.
3.3.3 RGB Outp u t Format
MTL001 output interface consists of two pixel ports, each containing Red, Green, and Blue color information
with a resolution of 6/8 bits per color. These two ports are PORT1 and PORT 2 respectively.
The control signals for output port are the display horizontal sync signal (DHSYNC), the display vertical sync
signal (DVSYNC) and the display data enable signal (DDEN).
All the signals mentioned above are synchronous to the output clock. The output timing relative to the active
edge of the output clock is programmable.
There are two RGB output formats:
¨ Sing l e Pixel Mode
equal to the internal display clock.
¨ Dual Pixel Mod e
Is designed to support TFT panels with dual pixel input. PORT1 and PORT2 are used. The first pixel is at
PORT1, and the second at PORT2.
(Rev. 0.95)
DCLK
DDEN
/B1OUT
DUAL PORT
DCLK
DCLK1
000 rgb0 rgb1 rgb2 rgb3 rgb4
DCLK2
DDEN
/B1OUT
/B2OUT
000 rgb0 rgb2 rgb4 rgb6 rgb8
000 rgb1 rgb3 rgb5 rgb7 rgb9
Fig.
Revision 0.95 - 12 - 2000/06/14
Page 13
MYSON
SDRAM Config ur atio n
SGRAM Config u ratio n
MTL001
TECHNOLOGY
(Rev. 0.95)
3.4 Memo r y Inter f ace
General Descrip t io n
In frame buffer mode, the MTL001 connects to the external frame buffers by means of memory interface. The
external frame memory can be made for 1M516bits SDRAM, 256K532bits or 512K532bits SGRAM
devices. Due to different applications such as VGA, SVGA, XGA as well as SXGA, the image resolution of
input and output will be limited resulting from the bandwidth of memory interface. Two configurations with 24,
32 and 48 bits bus modes will be supported to resolve the bandwidth constraint in most of applications. The
clock for external frame memory devices can be provided from the internal PLL circuit or the external clock
applied to pin EXTMCLK and its frequency can be up to 118 MHz. The MTL001 also supplies a simple and
complete memory self-testing mechanism for SDRAM and SGRAM, which can be used to detect memory cell
status and to check connection in memory interface.
3.4.1
In current applications, the most popular arrangement of SDRAM is 1M516bits. To achieve the desired
bandwidth in memory interface, 2 or 3 devices are constructed in parallel. The m emory clock ranging from
50MHz to 118MHz is tuned by giving appropriate parameters f or the internal PLL circuit. In two devices
configuration, the 24 and 32 bits bus modes are supported. In three devices, the 48 bits bus mode is
supported. In 24 bits bus mode, the maximum supported input image resolution is up to 10245768 @ 60Hz.
In 32 and 48 bits bus mode, the maximum supported input image resolution is up to 1 0245768 @ 85Hz.
Table 3.4.1 gives the configuration for different input and output image format. Figure 3.4.1 sho ws the
connection between the MTL001 and SDRAM devices in 2 configurations.
Unit: device
Output Resolution
Input Resolution
YUV 2 2
VGA (6405480) 2 2
SVGA (8005600) 2 2
XGA (10245768) 2 2
Table 3.4.1 SDRAM configuration in different input and output modes
3.4.2
The SGRAM devices in 256K532bits and 512K532bits constructions are usually used to feature the wide
data bus for high speed applications. In case of SGRAM usage, the 32 bits data bus of each device is divided
into 2 parts to store input image data. The memory clock is adjustable to achieve the desired range of
performance like the SDRAM case above. The maximum supported input image resolution in 24 bits bus
mode (2 devices) is up to 8005600 @ 85Hz, and both the 32 bits bus mode (2 devices) and the 48 bits bus
mode (3 devices) can support maximum input image resolution up to 10245768 @ 85Hz. Table 3.4.2
provides the configuration for different input and output image form at. Figure 3.4.2 and 3.4.3 show the
connection between the MTL001 and SGRAM devices in 2 configurations by 256K532bits and 512K532bits
constructions respectively.
Unit: device
Output Resolution
Input Resolution
YUV 2 2
VGA (6405480) 2 2
SVGA (8005600) 2 2
XGA (10245768)
(512Kx32 bits / 256Kx32 bits)
SVGA XGA
SVGA XGA
2 / 3 2 / 3
Table 3.4.2 SGRAM configurations in different input and output modes
Revision 0.95 - 13 - 2000/06/14
Page 14
MYSON
DQ7~0
DQ15~8
A8~0
LDQM
UDQM
/CS
/RAS
/CAS
CKE
/WE
MCKE
MCS
MRAS#
MCAS#
MWE#
DQM0
DQM1
MA[8:0]
SDRAM(1M
CLK
MCK
MD[7:0]
MD[31:24]
A10BAA9
DQM2/MA9
DQM3/MA10
BA/MA11
DQ7~0
DQ15~8
A8~0
LDQM
UDQM
/CS
/RAS
/CAS
CKE
/WE
CLK
A10BAA9
MCKE
MCS#
MRAS#
MCAS#
MWE#
DQM0
DQM1
MA[8:0]
MCK
DQM2/MA9
DQM3/MA10
BA/MA11
MD[15:8]
MD[39:32]
SDRAM(1M
/WE
/WE
/WE
MTL001
TECHNOLOGY
516bits) 5 2
516bits) 5 3
(Rev. 0.95)
MD[7:0]
MD[31:24]
BA/MA11
DQM3/MA10
MA[8:0]
DQM0
DQM1
MCKE
MCS#
MRAS#
MCAS#
MWE#
DQ7~0
DQ15~8
BA
A10
A9DQM2/MA9
A8~0
LDQM
UDQM
CLKMCK
CKE
/CS
/RAS
/CAS
MD[15:8]
MD[39:32]
BA/MA11
DQM3/MA10
DQM2/MA9
MA[8:0]
DQM0
DQM1
MCK
MCKE
MCS#
MRAS#
MCAS#
MWE#
DQ7~0
DQ15~8
BA
A10
A9
A8~0
LDQM
UDQM
CLK
CKE
/CS
/RAS
/CAS
MD[23:16]
MD[47:40]
BA/MA11
DQM3/MA10
DQM2/MA9
MA[8:0]
DQM0
DQM1
MCK
MCKE
MCS#
MRAS#
MCAS#
MWE#
Fig. 3.4.1 The interface between MTL001 and 1Mx16 bits SDRAM
DQ7~0
DQ15~8
BA
A10
A9
A8~0
LDQM
UDQM
CLK
CKE
/CS
/RAS
/CAS
Revision 0.95 - 14 - 2000/06/14
Page 15
MYSON
/WE
/WE
/WE
/WE
/WE
MTL001
TECHNOLOGY
SGRAM(128K532bits52 ) 5 2
MD[7:0]
MD[31:24]
BA/MA11 A9(BA)
MA[8:0]
DQM0
DQM1
DQM2/MA9
DQM3/MA10
MCKE
MCS#
MRAS#
MCAS#
MWE#
DQ7~0
DQ15~8
DQ23~16
DQ31~24
A8~0
DQM0
DQM1
DQM2
DQM3
CLKMCK
CKE
/CS
/RAS
/CAS
DSF
MD[15:8]
MD[39:32]
BA/MA11
MA[8:0]
DQM0
DQM1
DQM2/MA9
DQM3/MA10
MCK
MCKE
MCS#
MRAS#
MCAS#
MWE#
(Rev. 0.95)
DQ7~0
DQ15~8
DQ23~16
DQ31~24
A9(BA)
A8~0
DQM0
DQM1
DQM2
DQM3
CLK
CKE
/CS
/RAS
/CAS
DSF
SGRAM(128K532bits52 ) 5 3
MD[7:0]
MD[31:24]
BA/MA11 A9(BA)
MA[8:0]
DQM0
DQM1
DQM2/MA9
DQM3/MA10
MCKE
MCS#
MRAS#
MCAS#
MWE#
DQ7~0
DQ15~8
DQ23~16
DQ31~24
A8~0
DQM0
DQM1
DQM2
DQM3
CLKMCK
CKE
/CS
/RAS
/CAS
Fig. 3.4.2 The interface between MTL001 and 256Kx32 bits SGRAM
DSF
MD[15:8]
MD[39:32]
BA/MA11
MA[8:0]
DQM0
DQM1
DQM2/MA9
DQM3/MA10
MCK
MCKE
MCS#
MRAS#
MCAS#
MWE#
DQ7~0
DQ15~8
DQ23~16
DQ31~24
A9(BA)
A8~0
DQM0
DQM1
DQM2
DQM3
CLK
CKE
/CS
/RAS
/CAS
DSF
MD[23:16]
MD[47:40]
BA/MA11
MA[8:0]
DQM0
DQM1
DQM2/MA9
DQM3/MA10
MCK
MCKE
MCS#
MRAS#
MCAS#
MWE#
DQ7~0
DQ15~8
DQ23~16
DQ31~24
A9(BA)
A8~0
DQM0
DQM1
DQM2
DQM3
CLK
CKE
/CS
/RAS
/CAS
DSF
Revision 0.95 - 15 - 2000/06/14
Page 16
MYSON
GPIO[2]
GPIO[2]
GPIO[2]
GPIO[2]
GPIO[2]
MTL001
MD[7:0]
MD[31:24]
BA/MA11
MA[8:0]
DQM0
DQM1
DQM2/MA9
DQM3/MA10
MCKE
MCS#
MRAS#
MCAS#
MWE#
TECHNOLOGY
SGRAM(256K532bit s52 ) 5 2
DQ7~0
DQ15~8
DQ23~16
DQ31~24
A10(BA)
A9
A8~0
DQM0
DQM1
DQM2
DQM3
CLKMCK
CKE
/CS
/RAS
/CAS
/WE
DSF
MD[15:8]
MD[39:32]
BA/MA11 A10(BA)
MA[8:0]
DQM0
DQM1
DQM2/MA9
DQM3/MA10
MCKE
MCS#
MRAS#
MCAS#
MWE#
DQ7~0
DQ15~8
DQ23~16
DQ31~24
A9
A8~0
DQM0
DQM1
DQM2
DQM3
CLKMCK
CKE
/CS
/RAS
/CAS
/WE
(Rev. 0.95)
DSF
MD[7:0]
MD[31:24]
BA/MA11
MA[8:0]
DQM0
DQM1
DQM2/MA9
DQM3/MA10
MCKE
MCS#
MRAS#
MCAS#
MWE#
SGRAM(256K532bit s52 ) 5 3
DQ7~0
DQ15~8
DQ23~16
DQ31~24
A10(BA)
A9
A8~0
DQM0
DQM1
DQM2
DQM3
CLKMCK
CKE
/CS
/RAS
/CAS
/WE
DSF
MD[15:8]
MD[39:32]
BA/MA11 A10(BA)
MA[8:0]
DQM0
DQM1
DQM2/MA9
DQM3/MA10
MCKE
MCS#
MRAS#
MCAS#
MWE#
DQ7~0
DQ15~8
DQ23~16
DQ31~24
A9
A8~0
DQM0
DQM1
DQM2
DQM3
CLKMCK
CKE
/CS
/RAS
/CAS
/WE
DSF
MD[23:16]
MD[47:40]
BA/MA11
MA[8:0]
DQM0
DQM1
DQM2/MA9
DQM3/MA10
MCKE
MCS#
MRAS#
MCAS#
MWE#
DQ7~0
DQ15~8
DQ23~16
DQ31~24
A10(BA)
A9
A8~0
DQM0
DQM1
DQM2
DQM3
CLKMCK
CKE
/CS
/RAS
/CAS
/WE
DSF
Fig. 3.4.3 The interface between MTL001 and 512Kx32 bits SGRAM
Revision 0.95 - 16 - 2000/06/14
Page 17
MYSON
frame buffer, and display output as well.
C interface supports Random Write, Sequential Write, Current Address Read, Random Read and
For Random Write operation, it contains the slave address with R/W bit set to 0 and the word address which
is comprised of 8 bits that provides the access to any one of the 256 bytes in the selected memory range.
MTL001
TECHNOLOGY
(Rev. 0.95)
3.5 Host Inter fac e
General Descrip t io n
The primary function of Host Interface is to provide the interface between MTL001 and external CPU by 2wire I2C Bus or Direct Bus selected by the input pin BUSSEL. It can generate a ll the I/O decoded control
timing to control all the registers in MTL001. The other function is Screen Write, which allows users to clear
3.5.1 I2C Serial Bus
The I2C serial interface uses 2 wires, SCK (clock) and SDA(data I/O) respectively. The SCK is used as the
sampling clock and SDA is a bi-directional signal for the data. The communication must be started with a
valid START condition, concluded with STOP condition and acknowledged by ACK condition by the receiver.
The I2C bus device address of MTL001 is 0111010x.
AD[0] SCK, serial bus clock.
AD[1] SDA, bi-directional serial bus data.
The START condition means a HIGH to LOW transition of SDA when SCK is high, the STOP condition
means a LOW to HIGH transition of SDA when SCK is high. And data of SDA can only change when SCK is
low. Ref. Fig.3.5.1.
SDA
SCK
START
Fig. 3.5.1 START, STOP ,and DATA definition
2
The I
Sequential Read operations.
¨ Random Write
Upon receipt of the word address, MTL003 responds with an Acknowledge and waits for the next eight bits of
data again, responding with an Acknowledge, and then the master generates a stop co ndition. Ref. Fig.3.5.2.
DATA
CHANGE
DATA
CHANGE
STOP
Revision 0.95 - 17 - 2000/06/14
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MYSON
3.5.2 Random Write
Current Add ress Read
access address is n, the read data should access from address n+1. Upon receipt of the slave address with
bits data. After receiving data
MTL001
TECHNOLOGY
S
T
A
R
T
SDA
¨ Sequential Writ e
The initial step of Sequential Write is the same as Random Write, after the receipt of each word data,
MTL001 will respond with an Acknowledge and then internal address counter will increment by one for next
data write. If the master stops writing data, it will generate stop condition. Ref. Fig. 3.5.3.
S
T
A
SLAVE
R
ADDRESS
T
SLAVE
ADDRESS
WORD
ADDRESS
A
W
C
K
Fig.
DATA n
WORD
ADDRESS
DATA n+1
DATA
A
C
K
DATA n+x
(Rev. 0.95)
S
T
O
P
A
C
K
S
T
O
P
SDA
A
W
C
K
Fig. 3.5.3 Sequential Write
¨
MTL001 contains an address counter which maintains the last access address incremented by one. If the last
R/W bit set to 1, MTL001 generates an Acknowledge and transmits the eight
the master will generate a stop condition instead of an Acknowledge. Ref. Fig. 3.5.4.
SDA
S
T
A
R
T
A
C
K
SLAVE
ADDRESS
A
C
K
A
R
C
K
A
C
K
DATA
A
C
K
S
T
O
P
Fig. 3.5.4 Current Address Read
Revision 0.95 - 18 - 2000/06/14
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MYSON
The operation of Random Read allows access to any address. Before the reading data operation, it must
the master issues the start condition, slave address and then the word
address it is to read. After the word address acknowledge, the master generating a start condition again and
slave address with R/W bit is set to 1. MTL001 then transmits the 8 bits of data. Upon the completion of
The Direct Bus use AD[7:0], HWR#, HRD#, ALE, HCS# as the interface with host. ALE is used to latch read
S
MTL001
TECHNOLOGY
¨ Rando m Read
issue a “dummy write” operation —
receiving data, the master will generate a stop condition instead of an Acknowledge. Ref. Fig 3.5.5.
S
T
A
R
T
A
C
K
SLAVE
ADDRESS
A
R
C
K
SDA
T
A
R
T
SLAVE
ADDRESS
WORD
ADDRESS
A
W
C
K
Fig. 3.5.5 Random Read
(Rev. 0.95)
S
T
DATA
O
P
¨ Sequent i al Read
The initial step can be as either Current Address Read or Random Read. The first read data is transmitted in
the same manner as other read methods. However, the master generates an Acknowledge indicating that it
requires more data to read. MTL001 continues to output data for each Acknowledge received. The output
data is sequential and the internal address counter increments by one for next read data. Ref. Fig. 3.5.6.
S
T
A
SLAVE
R
ADDRESS
T
SDA
A
R
C
K
Fig. 3.5.6 Sequential Read
3.5.2 8-bit Direct Bus
or write address from AD[7:0] and HRD#, HWR# to access data. Ref. Fig. 3.5.7.
DATA n
A
C
K
DATA n+1
DATA n+x
A
C
K
S
T
O
P
AD[7:0] Address and data multiplex bus.
HRD# CPU read data strobe, Active Low.
HWR# CPU write data strobe, Active Low.
ALE ALE =1 latch read or write address, ALE=0 represents I/O data.
HCS# Enable signal for CPU access, Active Low.
Revision 0.95 - 19 - 2000/06/14
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MYSON
what events are happening. After the operation is completed, Firmware needs to clear interrupt status by
GPIO[7:6] pins. One is to set them as output only GPIO pins, and the other is to set them as Composite
Writing data to Reg. F4h/D0 when
pin to output ADHS which is HSYNC signal decoded from VGA input Composite signal by the
Writing data to F4h/D6 when
HWR/HRD
MTL001
TECHNOLOGY
AD[7:0]
ALE
Fig. 3.5.7 Direct Bus Timing
3.5.3 Interrupt
MTL001 supports one interrupt output signal (IRQ) which can be programmed to provide SYNC related or
function status related interrupts to the system. Upon receiving the interrupt request, Firmware needs to
firstly check the interrupt event by reading the Interrupt Flag Control registers (Reg. E8h and E9h) to decide
writing the same registers Reg. E8h and E9h. Furthermore, by using the Interrupt Flag Enable registers (Reg.
EAh and EBh), each interrupt event can be masked.
3.5.4 Screen Write
Screen Write function can be used to clear frame buffer m emory and display output by a fixed value defined
in Reg. C6h, C7h, C8h.
DATAADDRESS
(Rev. 0.95)
3.5.5 Bi-directi o nal GPIO
MTL001 supports eight General Purpose Input and Output (GPIO) pins GPIO[7:0] on chip. The GPIO[5:0]
pins are bi-directional GPIO pins, and the GPIO[7:6] pins are output only GPIO pins. T here are two functions
for
decoded VSYNC/HSYNC for A/D converters in VGA input path. The data and I/O dir ection of GPIO[7:0] pins
are controlled by Reg. F4h and F5h respectively, and each bit in the register is mapped to GPIO[7:0]
correspondingly. The following description is the process to control GPIO[0] and GPIO[6] in detail, and the
control processes of GPIO[4:1] and GPIO[7] also follows in the same m anner.
¨ Bi -directio nal GPIO contr ol proc ess
q Setting Reg. F5h /D0 = 0 or 1 to assign GPIO[0] as output or input.
q
Reg. F4h/D0 when GPIO[0] is input.
¨ Outpu t onl y GPIO contro l proc ess
q Setting Reg. F5h/D6 = 0 or 1 to assign GPIO[6] as output or tri-state.
q Setting Reg. F6h/D0 = 0 to select output source from Reg. F4h/D6 or setting it as 1 to make GPIO[6]
MTL001.
q
F5h/D6 = 0. If F6h/D0 is set to 1, the GPIO[6] pin outputs ADHS for AD converters in VGA input path.
3.5.6 Update Regist er Contents
I/O write operation to some consecutive register set can have the “Double Buffer” effect by setting the
Reg. C1h/D4. Written data is first stored in an intermediate bank of latches and then transf erred to the active
register set by setting Reg. C1h/D1-0.
GPIO[0] is assigned to output status, otherwise reading data from
GPIO[6] is assigned to output only GPIO pin, that is, F6h/D0 = 0 and
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MYSON
The MTL001 needs three clock sources to drive synchronous circuits on chip. These cl ocks are generated
XI and XO by an external quartz crystal at 14.31818 MHz. First one is the same as to the oscillator clock at
MTL001
TECHNOLOGY
(Rev. 0.95)
3.6 On-Chip PLL
General Descrip t io n
from the internal Phase Lock Loop (PLL) circuits with reference to the oscillator clock which is applied to pin
frequency (14.31818 MHz) to detect and measure graphic vertical and horizontal SYNC Frequency, Polarity
as well as Presence. The second is memory clock to synchronize memory controller with the external frame
buffers. The third is the display clock for display controller on chip and output signals to LCD pa nel.
3.6.1 Reference Cloc k
It is the counting basis of counter values in SYNC Processor such as VS and HS period count registers; that
is, the read back values from these registers must multiply the period of this clock to estimate VS and HS
frequency. Incorporating with polarity and frequency information of VS and HS, it can show the input graphic
image mode and pixel clock frequency.
3.6.2 Memory Clock
This clock is the synchronous clock for the external frame buffer. Depending on the ban dwidth needed by the
applications, DRAM types and configurations, the memory clock changes from 50 MHz to 118 MHz by
means of adjusting a set of appropriate values for M, N as well as R. The formula for calculating the desired
frequency of memory clock is as follows:
f
= f
mclk
Where f
3.6.3 Display Clock
This clock is the synchronous clock for LCD panel. According to the LCD panel resolution of applications, the
display clock range is from 50 MHz to 100 MHz by means of choosing a set of appropriate values for M, N as
well as R. The computing formula is exactly the same as for the memory clock.
5(M+2)/(N+2)51/R
osc
mclk
f
osc
M : post-divider ratio
N : pre-divider ratio
R : optional divider ratio
: the desired memory clock
: oscillator clock with 14.31818 MHz
Revision 0.95 - 21 - 2000/06/14
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MYSON
Input Delay Control 2
AUTO CALIBRATION REGISTERS
Auto Calibration RED Value - Byte 0
Auto Calibration RED Value - Byte 1
Auto Calibration RED Value - Byte 2
Auto Calibration RED Value - Byte 3
Auto Calibration GREEN Value - Byte 0
Auto Calibration GREEN Value - Byte 1
Auto Calibration GREEN Value - Byte 2
Auto Calibration GREEN Value - Byte 3
MTL001
TECHNOLOGY
(Rev. 0.95)
4. REGISTER DESCRIPTION
INPUT CONTROL REGISTERS
Address Mod e Regist ers Reset value
00h R/W Input Image Vertical Active Line Start - Low 00h
01h R/W Input Image Vertical Active Line Start - High 00h
02h R/W Input Image Vertical Active Lines - Low 00h
03h R/W Input Image Vertical Active Lines - High 00h
04h R/W Input Image Horizontal Active Pixel Start - Low 00h
05h R/W Input Image Horizontal Active Pixel Start - High 00h
06h R/W Input Image Horizontal Active Pixels - Low 00h
07h R/W Input Image Horizontal Active Pixels - High 00h
10h R/W Input Image Control Register 0 00h
11h R/W Input Image Control Register 1 00h
12h R/W Input Image Control Register 2 00h
13h R/W Input Image Control Register 3 00h
14h R/W Input Image Control Register 4 00h
15h R/W Input Image Control Register 5 00h
16h R/W Input Image Control Register 6 00h
1Ah R/W
1Ch R/W HS1 Sample Window Forward Extend 00h
1Dh R/W HS1 Sample Window Backward Extend 00h
1Fh RO Input Image Status Register -
00h
20h R/W Input Image Back Porch Guard Band 00h
21h R/W Input Image Front Porch Guard Band 00h
FRAME SYNC REGISTERS
Address Mod e Regist ers Reset value
28h R/W Frame Sync Control 00h
2Ch R/W Input Image Vertical Lock Position - Low 00h
2Dh R/W Input Image Vertical Lock Position - High 00h
2Eh R/W Input Image Horizontal Lock Position - Low 00h
2Fh R/W Input Image Horizontal Lock Position - High 00h
Address Mod e Regist ers Reset value
30h R/W Auto Calibration Control 0 80h
31h R/W Auto Calibration Control 1 00h
34h RO
35h RO
36h RO
37h RO
38h RO
39h RO
3Ah RO
3Bh RO
3Ch RO Auto Calibration BLUE Value - Byte 0 3Dh RO Auto Calibration BLUE Value - Byte 1 3Eh RO Auto Calibration BLUE Value - Byte 2 3Fh RO Auto Calibration BLUE Value - Byte 3 -
-
-
-
-
-
-
-
-
Revision 0.95 - 22 - 2000/06/14
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MYSON
Input VS Period Count by REFCLK - Low
Input VS Period Count by REFCLK - High
Input V Back Porch Count by Input HS - Low
Input V Back Porch Count by Input HS - High
Input V Total Lines Count by Input HS - Low
Input V Total Lines Count by Input HS - High
Input HS Period Count by REFCLK - Low
Input HS Period Count by REFCLK - High
DISPLAY CONTROL REGISTERS
MTL001
TECHNOLOGY
40h R/W Pixel Grab V Reference Position - Low 00h
41h R/W Pixel Grab V Reference Position - High 00h
42h R/W Pixel Grab H Reference Position - Low 00h
43h R/W Pixel Grab H Reference Position - High 00h
44h R/W Histogram Reference Color - RED 00h
45h R/W Histogram Reference Color - GREEN 00h
46h R/W Histogram Reference Color - BLUE 00h
SYNC PROCESSOR REGISTERS
Address Mod e Regist ers Reset value
48h R/W SYNC Processor Control 00h
49h R/W Auto Position Control 00h
4Ah R/W Auto Position Reference Color - RED 00h
4Bh R/W Auto Position Reference Color - GREEN 00h
4Ch R/W Auto Position Reference Color - BLUE 00h
4Eh R/W Clamp Pulse Control 0 00h
4Fh R/W Clamp Pulse Control 1 00h
(Rev. 0.95)
50h RO
51h RO
52h RO
53h RO
54h RO Input V Active Lines Count by Input HS - Low 55h RO Input V Active Lines Count by Input HS - High 56h RO
57h RO
58h RO
59h RO
5Ah RO Input H Back Porch Count by Input Pixel Clock - Low 5Bh RO Input H Back Porch Count by Input Pixel Clock - High 5Ch RO Input H Active Pixels Count by Input Pixel Clock - Low 5Dh RO Input H Active Pixels Count by Input Pixel Clock - High 5Eh RO Input H Total Pixels Count by Input Pixel Clock - Low 5Fh RO Input H Total Pixels Count by Input Pixel Clock - High -
Address Mod e Regist ers Reset value
60h R/W Display Vertical Total - Low 00h
61h R/W Display Vertical Total - High 00h
62h R/W Display Vertical SYNC End- Low 00h
63h R/W Display Vertical SYNC End - High 00h
64h R/W Display Vertical Active Start - Low 00h
65h R/W Display Vertical Active Start - High 00h
66h R/W Display Vertical Active End - Low 00h
67h R/W Display Vertical Active End - High 00h
68h R/W Display Vertical Border Start - Low 00h
69h R/W Display Vertical Border Start - High 00h
6Ah R/W Display Vertical Border End - Low 00h
6Bh R/W Display Vertical Border End - High 00h
-
-
-
-
-
-
-
-
70h R/W Display Horizontal Total - Low 00h
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MYSON
Border Window Color - RED
Border Window Color - GREEN
Border Window Color - BLUE
Output Clocks Duty Cycle Adjustment
MTL001
TECHNOLOGY
71h R/W Display Horizontal Total - High 00h
72h R/W Display Horizontal SYNC End - Low 00h
73h R/W Display Horizontal SYNC End - High 00h
74h R/W Display Horizontal Active Start - Low 00h
75h R/W Display Horizontal Active Start - High 00h
76h R/W Display Horizontal Active End - Low 00h
77h R/W Display Horizontal Active End - High 00h
78h R/W Display Horizontal Border Start - Low 00h
79h R/W Display Horizontal Border Start - High 00h
7Ah R/W Display Horizontal Border End - Low 00h
7Bh R/W Display Horizontal Border End - High 00h
88h R/W Output Image Control Register 0 00h
89h R/W Output Image Control Register 1 00h
8Ah R/W Output Image Control Register 2 00h
90h R/W Color Gain Control - RED 80h
91h R/W Color Gain Control - GREEN 80h
92h R/W Color Gain Control - BLUE 80h
93h R/W Brightn ess Control - RED 00h
94h R/W Brightness Control - GREEN 00h
95h R/W Brightn ess Control - BLUE 00h
96h R/W
97h R/W
98h R/W
9Eh R/W Dithering Table Data Port 9Fh R/W Gamma Table Data Port -
(Rev. 0.95)
00h
00h
00h
A0h R/W OSD Control Register 0 08h
A1h R/W OSD Control Register 1 00h
A2h R/W OSD Control Register 2 00h
A4h R/W Output Invert Control 00h
A5h R/W Output Tri-State Control 00h
A6h R/W Output Clocks Delay Adjustment 00h
A7h R/W
A9h R/W Output Miscellaneous Control 00h
AAh R/W Output Vertical Line Number - Low FFh
ABh R/W Output Vertical Line Number - High 02h
ACh RO Output Horizontal Total Pixel Number – Low ADh RO Output Horizontal Total Pixel Number – High -
AEh RO Output Horizontal Total Residue Number – Low AFh RO Output Horizontal Total Residue Number - High -
ZOOM CONTROL REGISTERS
Address Mod e Regist ers Reset value
B0h R/W Zoom Control Register 0 00h
B1h R/W Zoom Control Register 1 00h
B2h R/W Zoom Vertical Scale Down Integer 00h
B3h R/W Zoom Horizontal Scale Down Integer 00h
B4h R/W Zoom Vertical Scale Ratio - Low 00h
B5h R/W Zoom Vertical Scale Ratio - High 00h
B6h R/W Zoom Horizontal Scale Ratio - Low 00h
B7h R/W Zoom Horizontal Scale Ratio - High 00h
00h
Revision 0.95 - 24 - 2000/06/14
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MYSON
HS Frequency Change interrupt Compare
Input Image Vertical Act iv e Line Start - Low
It defines the low byte of the start position of the Vertical Active Window.
MTL001
TECHNOLOGY
BFh R/W Interpolation Table Data Port -
HOST CONTROL REGISTERS
Address Mod e Regist ers Reset value
C0h R/W Host Control Reg ister 0 00h
C1h R/W Host Control Reg ister 1 00h
C4h R/W Host Screen Write Line Length - Low 00h
C5h R/W Host Screen Write Line Length - High 03h
C6h R/W Host Fill Color - RED 00h
C7h R/W Host Fill Color - GREEN 00h
C8h R/W Host Fill Color - BLUE 00h
CBh RO Host Access Mode Status -
MEMORY CONTROL REGISTERS
Address Mod e Regist ers Reset value
D0h R/W Memory Type Control 00h
D2h R/W Memory Self Test Control 00h
D4h R/W Memory Line Offset - Low 00h
D5h R/W Memory Line Offset - High 04h
(Rev. 0.95)
DBh RO Memory Self-Test Compare Error Address - Low DCh RO Memory Self-Test Com pare Error Address - Middle DDh RO Memory Self-Test Com pare Error Address - High -
CLOCK CONTROL REGISTERS
Address Mod e Regist ers Reset value
E0h R/W Clock Control Register 00h
E1h WO Clock Synthesizer Value Load -
E2h R/W Display Clock Synthesizer N Value 0Bh
E3h R/W Display Clock Synthesizer M Value 32h
E4h R/W Memory Clock Synthesizer N Value 0Bh
E5h R/W Memory Clock Synthesizer M Value 32h
E6h R/W Clock Synthesizer R Value 00h
INTERRUPT CONTROL REGISTERS
Address Mod e Regist ers Reset value
E8h R/W SYNC Interrupt Flag Control 00h
E9h R/W General Interrupt Flag Control 00h
EAh R/W SYNC Interrupt Enable 00h
EBh R/W General Interrupt Enable 00h
ECh R/W
MISCELLANEOUS REGISTERS
Address Mod e Regist ers Reset value
F1h R/W Power Management Control 00h
F4h R/W GPIO Control Register 00h
F5h R/W GPIO Direction Control 00h
F6h R/W GPIO Misc Control 00h
00h
(Add r es s 00h) (R/W)
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MYSON
(Address 01h) (R/W)
It defines the high byte of the start position of the Vertical Active W indow.
Inpu t Image Verti c al Act iv e Lines - Low
Input Image Vertical Ac ti v e Lines - High (Add r es s 03h) (R/W)
It defines the low byte of the start position of the Horizontal Active Window.
(Add ress 05h) (R/W)
Inpu t Image Horizont al Acti v e Pixels - Low
Inpu t Image Horizon t al Acti v e Pixels - High (A d dress 07h) (R/W)
(Address 10h) (R/W)
MTL001
TECHNOLOGY
D7-0 IV_ACT_START[7:0]
Input Image Vertic al Act i v e Lin e Start - High
D7-3 Reserved
D2-0 IV_ACT_START[10:8]
(Add ress 02h) (R/W)
It defines the low byte of the number of active lines of the Vertical Active Window.
D7-0 IV_ACT_LEN[7:0]
It defines the high byte of the number of active lines of the Vertical Active Window.
D7-3 Reserved
(Rev. 0.95)
D2-0 IV_ACT_LEN[10:8]
Inpu t Image Horizon t al Acti v e Pixel Start - Low (Ad dress 04h) (R/W)
D7-0 IH_ACT_START[7:0]
Input Image Horizon t al Act i v e Pixel Start - High
It defines the high byte of the start position of the Horizontal Active Window.
D7-3 Reserved
D2-0 IH_ACT_START[10:8]
It defines the low byte of the number of active pixels of the Horizontal Active Window.
D7-0 IH_ACT_WIDTH[7:0]
It defines the high byte of the number of active pixels of the Horizontal Active Window.
(Add r es s 06h) (R/W)
D7-3 Reserved
D2-0 IH_ACT_WIDTH[10:8]
Input Image Cont ro l Regist er 0
D7 Horizontal Sampling Point Reference
0: from Input HSYNC.
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MYSON
1: from Input HREF (only for V
(Address 11h) (R/W)
(Address 12h) (R/W)
MTL001
TECHNOLOGY
D6 Input YCBCR Format
D5 Digital RGB 6 bit Mode
D4 Digital RGB Mode Select
D3 Input Image Format
D2 Input Clock Source
0: 4-2-2
1: 4-1-1
0: 8 bits
1: 6 bits
0: RGB Input from ADC
1: RGB Input from Panel Link
0: RGB888
1: YCBCR
0: from Graphic PLL clock.
1: from Video Decoder clock.
(Rev. 0.95)
ideo Decoder).
D1 Input Image Source
0: from Graphic source through ADC.
1: from Video source through Video Decoder like SAA7111A.
D0 ADC Configuration
0: Double Pixel mode
1: Single Pixel mode
Input Image Cont ro l Regist er 1
D7 Reserved
D6-4 De-interlace mode Select
000: All Fields write mode
001: Toggle Field write mode
010: Spatial Filtering write mode
D3 Input YUV CCIR656 Format
0: Disable
1: Enable
D2-1 Reserved
D0 Still mode Enable
0: Live mode
1: Still mode
Input Image Cont ro l Regist er 2
D7 Input ODD Field Invert
0: Normal
1: Invert
D6 External Input Interlace Select
0: Non-interlace
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Input VSYNC Polarity Source
(Address 13h) (R/W)
0: Select Normal HSYNC/ Composite Sync
(Address 14h) (R/W)
MTL001
TECHNOLOGY
1: Interlace
D5 External Input VSYNC Polarity
0: Active Low
1: Active High
D4 External Input HSYNC Polarity
0: Active Low
1: Active High
D3 Input ODD Field Source
0: from Internal Detection
1: from External pin.
D2 Input Interlace Source
0: from Internal detection
1: from Register setting (D6)
D1
0: from Internal detection
1: from Register setting (D5)
(Rev. 0.95)
D0 Input HSYNC Polarity Source
0: from Internal detection
1: from Register setting (D4)
Input Image Cont ro l Regist er 3
D7 Active Position Area for Auto Position in TMDS
0: from Internal Detection
1: from External Data Enable (TDIE)
D6-3 Reserved
D2 Sync On Green Select
1: Select Sync On Green
D1 Input Vertical Timing based on VSYNC
0: Leading Edge
1: Trailing Edge
D0 Input Horizontal Timing based on HSYNC
0: Leading Edge
1: Trailing Edge
Input Image Cont ro l Regist er 4
D7 Input ODD Field Detection Point
0: at the start of VSYNC pulse.
1: at the end of VSYNC pulse.
D6 Input Image Port A, B Data and Clocks Swap
0: Normal
1: Swap
D5 Reserved
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(Address 15h) (R/W)
(Address 16h) (R/W)
ADC HS Polarity Invert when D1=1
(Add r es s 1Ah ) (R/W)
Input VSYNC Delay Adjustment
(Add ress 1Ch) (R/W)
Input HS Pulse Width Forward Extend by IDCLK
MTL001
TECHNOLOGY
D4 Input Image CBCR Order Swap
0: Normal
1: Swap
D3-0 Reserved
Input Image Cont ro l Regist er 5
D7 Horizontal Pixel Valid Select
0: from Internal Programming
1: from External HREF/TDIE
D6-0 Reserved
Input Image Cont ro l Regist er 6
D7-3 Reserved
D2
0: Active Low
1: Active High
(Rev. 0.95)
D1 Raw HS path Enable
0: Disable
1: Enable
D0 Reserved
Inpu t Delay Contro l 2
D7-4
1111: 7 IDCLKs delay
1110: 6 IDCLKs delay
1101: 5 IDCLKs delay
1100: 4 IDCLKs delay
1011: 3 IDCLKs delay
1010: 2 IDCLKs delay
1001: 1 IDCLK delay
1000: Reserved
0111: 7ns gate delay
0110: 6ns gate delay
0101: 5ns gate delay
0100: 4ns gate delay
0011: 3ns gate delay
0010: 2ns gate delay
0001: 1ns gate delay
0000: No delay
D3-0 Input HSYNC Delay Adjustment
16 steps to change, each of them is 1ns delay/step.
Input HS Pulse Width Forw ard Extend
D7-0
HS1FWEXT[7:0]: Used when Interlace First/Second Field Detection.
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(Add ress 1Dh) (R/W)
Input HS Pulse Width Backward Extend by IDCLK
HS1BWEXT[7:0]: Used when Interlace First/Second Field Detection.
(Add ress 1Fh) (RO)
Show Display VSYNC signal directly.
C Polarity Status
(Add ress 20h) (R/W)
Input Image Back Porch Guard Band by IDCLK
Frame Sync Con t r o l 0 (Add r ess 28h) (R/W)
MTL001
TECHNOLOGY
Inpu t HS Pulse Width Backw ard Extend
D7-0
Input Image Status Register
D7 Display VSYNC Monitor
D6 Input VSYNC Monitor
D5 External Input Interlace Status
D4 Extracted CVSYNC Present Status
D3 External Input VSYNC Present Status
Show Input VSYNC signal directly.
0: Non-interlace
1: Interlace
0: Not Present
1: Present
0: Not Present
1: Present
(Rev. 0.95)
D2 External Input HSYNC Present Status
0: Not Present
1: Present
D1 External Input VSYNC Polarity Status
0: Active Low
1: Active High
D0 External Input HSYN
0: Active Low
1: Active High
Input Image Back Porc h Guard Band
D7-0
HBPGB[7:0]: Used in Auto Position detection to mask out unwanted data.
Inpu t Image Front Porch Guard Band (Ad dress 21h) (R/W)
D7-0 Input Image Front Porch Guard Band by IDCLK
HFPGB[7:0]: Used in Auto Position detection to mask out unwanted data.
D7-5 Reserved
D1 Frame Sync Select in Frame Buffer mode
0: Normal
1: Frame Sync
D0 Frame Buffer mode Select
0: Frame Buffer mode
Revision 0.95 - 30 - 2000/06/14
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MYSON
Auto Calibr atio n Cont r ol 0 (Address 30h) (R/W)
Pixel Grab Ready Flag
0: MYSON proprietary method
MTL001
TECHNOLOGY
1: Non Frame Buffer mode
Input Image Vertic al Loc k Posi t io n - Low (Add ress 2Ch) (R/W)
It defines the low byte of the number of input lines where Display image tim ing
synchronizes the input image source.
D7-0 IPV_LOCK_POS[7:0]
Input Image Verti cal Lo c k Posi t i on - High (Addr ess 2Dh) (R/W)
It defines the high byte of the number of input lines where Display image timing
synchronizes the input image source.
D7-3 Reserved
D2-0 IPV_LOCK_POS[10:8]
Input Image Hori zon t al Loc k Posi t i o n - Low (Addr ess 2Eh) (R/W)
It defines the low byte of the number of input pixel clocks where Displa y image
timing synchronizes the input image source.
(Rev. 0.95)
D7-0 IPH_LOCK_POS[7:0]
Input Image Hori zon t al Loc k Posit i o n - High (Add r ess 2Fh) (R/W)
It defines the high byte of the number of input pixel clocks where Display image
timing synchronizes the input image source.
D7-3 Reserved
D2-0 IPH_LOCK_POS[10:8]
D7
0: Ready
1: Not Ready
D6 Pixel Grab Update Enable
0: Stop updating
1: Continue updating
D5 Threshold Select
Used in Histogram mode or MIN/MAX mode.
0: High bound / MAX
1: Low bound / MIN
(RO)
D4 Phase Calibration Method Select
1: Difference Value method
D3-2 Auto Calibration Modes Select
The measured value is available one item at a time,
selected as shown:
00: Phase Calibration Mode
Revision 0.95 - 31 - 2000/06/14
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MYSON
ation Ready Flag
Auto Calibr atio n Cont r ol 1 (Address 31h) (R/W)
MTL001
TECHNOLOGY
01: Histogram Mode
10: MIN/MAX Mode
11: Pixel Grab Mode
D1 Auto Calibration Burst Mode Enable
(except Pixel Grab Mode)
0: Single Mode
1: Burst Mode
D0 Auto Calibration Enable (W)
(except Pixel Grab Value)
0: Disable
1: Enable
Auto Calibr
0: Ready
1: Not Ready
D7-3 Reserved
D2-0 Mask LSBs of Input Image Select
It is used only for Phase Calibration to mask noise.
000: No Mask
001: Mask bit0
010: Mask bit0,1
011: Mask bit0,1,2
100: Mask bit0,1,2,3
101: Mask bit0,1,2,3,4
110: Mask bit0,1,2,3,4,5
111: Mask bit0,0,1,2,3,4,5,6
(R)
(Rev. 0.95)
Auto Calib ration RED Value - By t e 0 (Addres s 34h) (RO)
It states the byte 0 of the number of Phase Calibration RED value in one frame or
the byte 0 of the number of Histogram Red value in one frame or the Pixel Grab RED
value in one frame of Non_interlace mode or FIRST field of Interlace mode.
D7-0 CALVAL_R[7:0]
Aut o Calib r ation RED Value - Byte 1 (Addr ess 35h) (RO)
It states the byte 1 of the number of Phase Calibration RED value in one frame or
the byte 1 of the number of Histogram Red value in one frame or the Pixel Grab GREEN
value in one frame of Non_interlace mode or FIRST field of Interlace mode.
D7-0 CALVAL_R[15:8]
Aut o Calib r ation RED Value - Byte 2 (Addr ess 36h) (RO)
It states the byte 2 of the number of Phase Calibration RED value in one frame or
the byte 2 of the number of Histogram Red value in one frame or the Pixel Grab BLUE
value in one frame of Non_interlace mode or FIRST field of Interlace mode.
D7-0 CALVAL_R[23:16]
Aut o Calib r ation RED Value - Byte 3 (Addr ess 37h) (RO)
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MYSON
the byte 0 of the number of Histogram BLUE value in one frame or
the byte 1 of the number of Histogram BLUE value in one frame or
MTL001
TECHNOLOGY
It states the byte 3 of the number of Phase Calibration RED value in one frame.
D7-6 Reserved
D5-0 CALVAL_R[29:24]
Aut o Calib ration GREEN Value - Byt e 0 (Addr ess 38h) (RO)
It states the byte 0 of the number of Phase Calibration GREEN value in one frame
or the byte 0 of the number of Histogram GREEN value in one frame or
the Pixel Grab RED value in SECOND field of Interlace mode.
D7-0 CALVAL_G[7:0]
Aut o Calib ration GREEN Value - Byt e 1 (Addr ess 39h) (RO)
It states the byte 1 of the number of Phase Calibration GREEN value in one frame
or the byte 1 of the number of Histogram GREEN value in one frame or
the Pixel Grab GREEN value in SECOND field of Interlace mode.
D7-0 CALVAL_G[15:8]
(Rev. 0.95)
Aut o Calib r ation GREEN Value - Byte 2 (Addres s 3Ah) (RO)
It states the byte 2 of the number of Phase Calibration GREEN value in one frame
or the byte 2 of the number of Histogram GREEN value in one frame or
the Pixel Grab BLUE value in SECOND field of Interlace mode.
D7-0 CALVAL_G[23:16]
Aut o Calib r ation GREEN Value - Byte 3 (Address 3Bh ) (RO)
It states the byte 3 of the number of Phase Calibration GREEN value in one frame.
D7-6 Reserved
D5-0 CALVAL_G[29:24]
Auto Calib r ati o n BL UE Value - Byte 0 (Address 3Ch) (RO)
It states the byte 0 of the number of Phase Calibration BLUE value in one frame or
the MIN/MAX RED value in one frame.
D7-0 CALVAL_B[7:0]
Auto Calib r ati o n BL UE Value - Byte 1 (Address 3Dh) (RO)
It states the byte 1 of the number of Phase Calibration BLUE value in one frame or
the MIN/MAX GREEN value in one frame.
D7-0 CALVAL_B[15:8]
Auto Calib r ati o n BL UE Value - Byte 2 (Address 3Eh) (RO)
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MYSON
the byte 2 of the number of Histogram BLUE value in one frame or
It states the high byte of Vertical Reference Position in Pixel Grab Mode.
It states the high byte of Horizontal Reference Position in Pixel Grab Mode.
RED (Addres s 44h) (R/W)
GREEN (Address 45h) (R/W)
BLUE (Add ress 46h) (R/W)
MTL001
TECHNOLOGY
It states the byte 2 of the number of Phase Calibration BLUE value in one frame or
the MIN/MAX BLUE value in one frame.
D7-0 CALVAL_B[23:16]
Auto Calib r ati o n BL UE Value - Byte 3 (Address 3Fh) (RO)
It states the byte 3 of the number of Phase Calibration BLUE value in one frame.
D7-6 Reserved
D5-0 CALVAL_B[29:24]
Pixel Grab V Reference Posit i on - Low (Address 40h) (R/W)
It states the low byte of Vertical Reference Position in Pixel Grab Mode.
D7-0 VGRAB_POS[7:0]
Pixel Grab V Reference Posit i on - High (Address 41h) (R/W)
(Rev. 0.95)
D7-3 Reserved
D2-0 VGRAB_POS[10:8]
Pixel Grab H Reference Position - Low (Add r ess 42h) (R/W)
It states the low byte of Horizontal Reference Position in Pixel Grab Mode.
D7-0 HGRAB_POS[7:0]
Pixel Grab H Referenc e Position - High (Address 43h) (R/W)
D7-3 Reserved
D2-0 HGRAB_POS[10:8]
Histogr am Reference Colo r It states the Histogram Reference RED Color in Histogram Mode.
D7-0 HIST_R[7:0]
Histogr am Reference Colo r It states the Histogram Reference GREEN Color in Histogram Mode.
D7-0 HIST_G[7:0]
Histogr am Reference Colo r It states the Histogram Reference BLUE Color in Histogram Mode.
Revision 0.95 - 34 - 2000/06/14
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SYNC Process o r Contro l (Add ress 48h) (R/W)
Auto Posit i o n Cont ro l (Addr ess 49h) (R/W)
Auto Position Ready Flag
0 (Address 4Eh) (R/W)
MTL001
TECHNOLOGY
D7-0 HIST_B[7:0]
D7-2 Reserved
D1-0 SYNC Source
00: from H/V SYNC
01: from CVSYNC (Composite SYNC)
1x: Auto switch to CVSYNC when CVSYNC is present, but VSYNC not.
D7-2 Reserved
D1 Auto Position Burst Mode Enable
0: Single Mode
1: Burst Mode
D0 Auto Position Enable (W)
0: Disable
1: Enable
(R)
0: Ready
1: Not Ready
(Rev. 0.95)
Auto Posi t i o n Reference Color - RED (Address 4Ah) (R/W)
It defines the red component color for selecting between black and non-black pixels.
D7-0 REF_COLOR_RED[7:0]
Auto Pos i t i o n Reference Colo r - GREEN (Addr ess 4Bh) (R/W)
It defines the green component color for selecting between black and non-black pixels.
D7-0 REF_COLOR_GREEN[7:0]
Auto Posi t i o n Reference Color - BLUE (Address 4Ch) (R/W)
It defines the blue component color for selecting between black and non-black pixels.
D7-0 REF_COLOR_BLUE[7:0]
Clamp Pulse Contro l
D7 Clamp Pulse Mask
D6 Clamp Pulse Start Reference Edge
0: Normal
1: Mask out Clamp Pulse
0: From Input HSYNC trailing edge.
1: From Input HSYNC leading edge.
D5 Clamp Pulse output Polarity
0: Active High
Revision 0.95 - 35 - 2000/06/14
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1 (Address 4Fh) (R/W)
To Adjust Clamp Pulse Width by Input DCLK.
It states the high byte of the number
It states the high byte of the number of lines between the end of VSYNC and the acti ve image
Input V Acti ve Image Count b y Inpu t HS - Low (Add r ess 54h) (RO)
Input V Acti ve Image Count b y Inpu t HS - High (Address 55h) (RO)
MTL001
TECHNOLOGY
1: Active Low
D4-0 Clamp Pulse Start
Start of Clamp Pulse after the selected edge of Input HSYNC by Input DCLK.
Clamp Pulse Contro l
D7-5 Reserved
D4-0 Clamp Pulse Width
Input VS Period Count by REFCLK - Low (Add r ess 50h) (RO)
It states the low byte of the number of REFCLK of the Vertical Sync period measurement.
D7-0 VSPRD[7:0]
Input VS Period Count by REFCLK - High (Add r ess 51h) (RO)
of REFCLK of the Vertical Sync period measurement.
(Rev. 0.95)
D7-4 Reserved
D3-0 VSPRD[11:8]
Input V Back Porch Coun t b y Inpu t HS - Low (Add r ess 52h) (RO)
It states the low byte of the number of lines between the end of VSYNC and the active image.
D7-0 VBPW[7:0]
Input V Back Porch Coun t b y Inpu t HS - High (Addr ess 53h) (RO)
D7-3 Reserved
D2-0 VBPW[10:8]
It states the low byte of the number of the active image lines.
D7-0 VACTW[7:0]
It states the high byte of the number of the active image lines
D7-3 Reserved
D2-0 VACTW[10:8]
Input V Total Image Cou n t b y Inpu t HS - Low (Address 56h) (RO)
It states the low byte of the number of the total image lines.
Revision 0.95 - 36 - 2000/06/14
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MYSON
It states the high byte of the number of
Input H Back Porch Count by Input Pixel Clock -Low (Addr ess 5Ah) (RO)
It states the high byte of the number of pixels between the end of HSYNC and the active image.
It states the high byte of the number of the Horizontal active image pixels.
MTL001
TECHNOLOGY
D7-0 VTOTW[7:0]
Input V Total Image Cou n t b y Inp u t HS - High (Ad d r es s 57h) (RO)
It states the high byte of the number of the total image lines.
D7-3 Reserved
D2-0 VTOTW[10:8]
Input HS Period Cou n t by REFCLK - Low (Add r ess 58h) (RO)
It states the low byte of the number of REFCLKs of the Horizontal Sync period measurement.
D7-0 HSPRD[7:0]
Input HS Period Count by REFCLK - High (Address 59h) (RO)
REFCLKs of the Horizontal Sync period measurement.
D7-5 Reserved
(Rev. 0.95)
D4-0 HSPRD[12:8]
It states the low byte of the number of pixels between the end of HSYNC and the active image.
D7-0 HBPW[7:0]
Input H Back Porc h Count by Input Pixel Clock -High (Address 5Bh) (RO)
D7-3 Reserved
D2-0 HBPW[10:8]
Input H Activ e Image Count b y Input Pixel Clock -Low(Address 5Ch) (RO)
It states the low byte of the number of the Horizontal active image pixels.
D7-0 HACTW[7:0]
Input H Activ e Image Count b y Input Pixel Clock -High(Ad d r ess 5Dh)(RO)
D7-3 Reserved
D2-0 HACTW[10:8]
Input H Total Image Count b y Inpu t Pixel Cloc k- Low (Address 5Eh) (RO)
It states the low byte of the number of the Horizontal total image pixels.
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It states the high byte of the number of the Horizontal total image pixels.
It defines the high byte of the number of lines per display frame.
(Add ress 63h) (R/W)
Disp lay Vertical Act iv e Start - Low
It defines the low byte of
Display Verti c al Acti v e Start - High
It defines the high byte of
Disp lay Vertical Acti v e End - Low
It defines the low byte of
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TECHNOLOGY
D7-0 HTOTW[7:0]
Input H Total Image Count b y Inpu t Pixel Cloc k- High (Add ress 5Fh) (RO)
D7-3 Reserved
D2-0 HTOTW[10:8]
Display Verti c al Total - Low (Address 60h) (R/W)
It defines the low byte of the number of lines per display frame.
D7-0 DV_TOTAL[7:0]
Display Vertical Total - High (Add r es s 61h) (R/W)
D7-3 Reserved
(Rev. 0.95)
D2-0 DV_TOTAL[10:8]
Display Verti c al SYNC End - Low (Address 62h) (R/W)
It defines the low byte of Vertical SYNC end position in lines.
D7-0 DV_SYNC_END[7:0]
Display Verti c al VSYNC End - High
It defines the high byte of Vertical SYNC end position in lines.
D7-3 Reserved
D2-0 DV_SYNC_END[10:8]
Note: Display Vertical SYNC Start is always equal 0.
D7-0 DV_ACT_START[7:0]
Vertical Active region start position in lines.
(Add ress 64h) (R/W)
(Add ress 65h) (R/W)
D7-3 Reserved
D2-0 DV_ACT_START[10:8]
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Vertical Active region start position in lines.
(Add r es s 66h) (R/W)
Vertical Active region end position in lines.
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Display Verti c al Acti v e End - High (Ad dress 67h) (R/W)
It defines the high byte of
It defines the low byte of Vertical Border start position in lines.
(Add ress 69h) (R/W)
It defines the high byte of Vertical Border start position in lines.
Display Vertic al Bo rd er End - Low (Addr ess 6Ah) (R/W)
(Add ress 71h) (R/W)
MTL001
TECHNOLOGY
D7-0 DV_ACT_END[7:0]
D7-3 Reserved
D2-0 DV_ACT_END[10:8]
Disp lay Vertical Bo rd er Start - Low (Addr ess 68h) (R/W)
D7-0 DV_BOR_START[7:0]
Display Verti c al Bor d er Start - High
D7-3 Reserved
Vertical Active region end position in lines.
(Rev. 0.95)
D2-0 DV_BOR_START[10:8]
It defines the low byte of Vertical Border end position in lines.
D7-0 DV_BOR_END[7:0]
Display Vertic al Bo rd er End - High (Addr ess 6Bh) (R/W)
It defines the high byte of Vertical Border end position in lines.
D7-3 Reserved
D2-0 DV_BOR_END[10:8]
Disp lay Horizon t al Total - Low (Addres s 70h) (R/W)
It defines the low byte of the number of display clock cycles per display line.
D7-0 DH_TOTAL[7:0]
Display Horizont al Total - High
It defines the high byte of the number of display clock cycles per display line.
D7-3 Reserved
D2-0 DH_TOTAL[10:8]
Display Horizo nt al SYNC End - Low (Address 72h) (R/W)
It defines the low byte of Horizontal SYNC end position in display clock cycles.
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(Add ress 73h) (R/W)
Disp lay Horizont al Act iv e Start - Low
It defines the low byte of Horizontal Active region start position in display clock cycles.
Disp lay Horizon t al Acti v e Start - High (Addr es s 75h) (R/W)
It defines the high byte of
Displ ay Horizontal Act i ve End - Low
It defines the low byte of Horizontal Active region end position in display clock cycles.
Disp lay Horizon t al Acti v e End - High (Address 77h) (R/W)
It defines the high byte of
Display Horizon t al Bo rd er End - Low (Addr ess 7Ah) (R/W)
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TECHNOLOGY
D7-0 DH_SYNC_END[7:0]
Display Hori zo n t al SYNC End - High
It defines the high byte of Horizontal SYNC end position in display clock cycles.
D7-3 Reserved
D2-0 DH_SYNC_END[10:8]
Note: Display Horizontal SYNC Start is always equal 0.
D7-0 DH_ACT_START[7:0]
Horizontal Active region start position in display clock cycles.
(Add r es s 74h) (R/W)
(Rev. 0.95)
D7-3 Reserved
D2-0 DH_ACT_START[10:8]
(Add r es s 76h) (R/W)
D7-0 DH_ACT_END[7:0]
D7-3 Reserved
D2-0 DH_ACT_END[10:8]
Disp lay Horizont al Bor der Start - Low (Ad dress 78h) (R/W)
It defines the low byte of Horizontal Border start position in display clock cycles.
D7-0 DH_BOR_START[7:0]
Display Horizo nt al Bo r d er Start - High (Addr ess 79h) (R/W)
Horizontal Active region end position in display clock c ycles.
It defines the high byte of Horizontal Border start position in display clock cycles.
D7-3 Reserved
D2-0 DH_BOR_START[10:8]
It defines the low byte of Horizontal Border end position in display clock cycles.
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(Add ress 88h) (R/W)
(Add ress 89h) (R/W)
(Add r es s 8Ah ) (R/W)
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TECHNOLOGY
D7-0 DH_BOR_END[7:0]
Display Horizon t al Bo rd er End - High (Address 7Bh) (R/W)
It defines the high byte of Horizontal Border end position in display clock cycles.
D7-3 Reserved
D2-0 DH_BOR_END[10:8]
Output Image Contro l Register 0
D7-3 Reserved
D2 Output Pixel 18 bit RGB Mode Select
0: 24 bit RGB
1: 18 bit RGB
D1 Output Dual Pixel Data Exchange
0: Normal
1: Exchange
(Rev. 0.95)
D0 Output Dual Pixel Select
0: Dual Pixel
1: Single Pixel
Output Image Contro l Register 1
D7-6 Reserved
D5 RGB Brightness Control Enable
0: Disable
1: Enable
D4 RGB Gain Control Enable
0: Disable
1: Enable
D3-2 Reserved
D1 Border Window Function
0: OFF
1: ON
D0 Output Blank Screen
0: Normal
1: Output Pixel masked as BLACK color
Output Image Contro l Register 2
D7 Reserved
D6 Temporal Dithering Enable
0: Static Dithering
1: Temporal Dithering
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Dithering Table R/W Access Enable
Colo r Gain Cont r ol - RED (Add r ess 90h) (R/W)
It can be used to adjust the gain of RED component of the Display Image.
(Add ress 91h) (R/W)
It can be used to adjust the gain of GREEN component of the Display Image.
(Address 92h) (R/W)
It can be used to adjust the brightness of RED component of the Display Image.
It can be used to adjust the brightness of GREEN component of the Display Image.
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D5
0: Disable
1: Enable
D4 Dithering Enable
0: Disable
1: Enable
D3 Reserved
D2 10 bit Gamma Table Enable
0: 8 bit Gamma Table
1: 10 bit Gamma Table
D1 Gamma Table R/W Access Enable
0: Disable
1: Enable
D0 Gamma Correction Function
0: OFF
1: ON
(Rev. 0.95)
D7-0 RGAIN[7:0]
0(00h) ~ x1(80h) ~ x1.992185(FFh)
Color Gain Control - GREEN
D7-0 GGAIN[7:0]
0(00h) ~ x1(80h) ~ x1.992185(FFh)
Color Gain Contr ol - BLUE
It can be used to adjust the gain of BLUE component of the Display Im age.
D7-0 BGAIN[7:0]
0(00h) ~ x1(80h) ~ x1.992185(FFh)
Color Br i gh t n ess Cont r o l - RED (Addr ess 93h) (R/W)
D7-0 RBRIGHT[7:0]
-128(80h) ~ 0(00h) ~127(7Fh)
Color Br i g h t n ess Cont r o l - GREEN (Address 94h) (R/W)
D7-0 GBRIGHT[7:0]
-128(80h) ~ 0(00h) ~127(7Fh)
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Bor d er Win d o w Col o r - RED (Address 96h) (R/W)
When the Display Image is not expanded to full screen, it can be specified as the
Border Windo w Color - GREEN (Address 97h) (R/W)
When the Display Image is not expanded to full screen, it can be specified as the
Bor d er Wind o w Color - BLUE (Addr ess 98h) (R/W)
When the Display Image is not expanded to full screen, it can be specified as the
Since the Gamma Table is downloadable, this data port is the entry address.
OSD Control Register 0 (Addr ess A0h) (R/W)
0: from Internal Display Dot Clock
1: from Internal Display Dot Clock x 2
OSD Intensity Enable (For MOTOROLA)
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TECHNOLOGY
Color Bri g h t n ess Cont r o l - BLUE (Address 95h) (R/W)
It can be used to adjust the brightness of BLUE component of the Display Image.
D7-0 BBRIGHT[7:0]
-128(80h) ~ 0(00h) ~127(7Fh)
RED component of the border color.
D7-0 BCR[7:0]
GREEN component of the border color.
D7-0 BCG[7:0]
(Rev. 0.95)
BLUE component of the border color.
D7-0 BCB[7:0]
Ditherin g Table Data Port (Address 9Eh) (R/W)
Since the Dithering Table is downloadable, this data port is the entry address.
D7-0 DITHER_PORT[7:0]
Gamma Tabl e Data Port (Addr es s 9Fh) (R/W)
D7-0 GAMMA_PORT[7:0]
D7 OSD Output Clock Select
D6 OSD Output VS Invert
0: Normal
1: Invert
D5-4 Reserved
D3 OSD Function
0: OFF
1: ON
D2
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OSD Control Register 1 (Addr ess A1h) (R/W)
o change, each of them is 1ns delay/step.
8 steps to change, each of them is 1ns delay/step.
OSD Con t r o l Regis t er 2 (Addr ess A2h ) (R/W)
(Addr es s A4h ) (R/W)
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TECHNOLOGY
0: Disable
1: Enable
D1-0 OSD TYPE Select
00: OSDRGB = {R0000000, G0000000, B0000000}
01: OSDRGB = {RR000000, GG000000, BB000000}
10: OSDRGB = {RRRR0000, GGGG0000, BBBB0000}
11: OSDRGB = {RRRRRRRR, GGGGGGGG, BBBBBBBB}
R = OSDR, G = OSDG, B = OSDB
D7 OSD Output HS Invert
0: Normal
1: Invert.
D6 OSD Output DCLK Invert
0: Normal
1: Invert.
D5-4 OSD Output HS Delay
4 steps t
(Rev. 0.95)
D3 OSD Input Data Sample Clock Invert
D2-0 OSD Input Data Sample Clock Delay
D7-4 Reserved
D3-0 OSD Output Clock Delay
Output Invert Contro l
D7 Reserved
D6 RGB Data Invert Enable
D5 Display DCLK2 Invert
0: Normal.
1: Invert.
16 steps to change, each of them is 1ns delay/step.
0: Disable
1: Enable
0: Normal
1: Invert
D4 Display DCLK1 Invert
0: Normal
1: Invert
D3 Reserved
D2 Display Data Enable (DDEN) Invert
0: Normal
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(Add r es s A5h ) (R/W)
Output Clocks Duty Cycle Adjust ment (Ad dress A7h) (R/W)
Display DCLK2 duty cycle Increase/Decrease
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TECHNOLOGY
1: Invert
D1 Display VSYNC Invert
0: Normal
1: Invert
D0 Display HSYNC Invert
0: Normal
1: Invert
Output Tri_state Control
D7 Display Data R2OUT, G2OUT, B2OUT Output Disable
0: Normal
1: Tri_stated
D6 Display Data R1OUT, G1OUT, B1OUT Output Disable
0: Normal
1: Tri_stated
D5 Display DCLK2 Output Disable
0: Normal
1: Tri_stated
(Rev. 0.95)
D4 Display DCLK1 Output Disable
0: Normal
1: Tri_stated
D3 OSD OCLK / OVSYNC / OHSYNC Output Disable
0: Normal
1: Tri_stated
D2 Display Data Enable (DDEN) Output Disable
0: Normal
1: Tri_stated
D1 Display VSYNC Output Disable
0: Normal
1: Tri_stated
D0 Display HSYNC Output Disable
0: Normal
1: Tri_stated
Outpu t Clock s Delay Adjus tm ent (Add ress A6h) (R/W)
D7-4 Display DCLK2 delay adjustment
16 steps to adjust, Typical 1ns delay/step
D3-0 Display DCLK1 delay adjustment
16 steps to adjust, Typical 1ns delay/step
D7
0: Decrease
1: Increase
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Display DCLK2 duty cycle adjustment
Display DCLK1 duty cycle Increase/Decrease
Display DCLK1 duty cycle adjustment
(Add r es s A9h) (R/W)
Auto Output Horizontal Total Calculation Ready Flag
Output Vertical Activ e Line Number - Low
AAh) (R/W)
It defines the low byte of Output Vertical Active Line Number only used for getting the values of
Output Vertical Acti v e Line Number - High
ABh) (R/W)
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TECHNOLOGY
D6-4
8 steps to adjust, Typical 0.5ns delay/step
D3
0: Decrease
1: Increase
D2-0
8 steps to adjust, Typical 0.5ns delay/step
Outpu t Miscellaneous Contr ol
D7 Second field Line Buffer Overflow status for Interlace input (RO)
0: Not Overflow
1: Overflow
D6 Second field Line Buffer Underflow status for Interlace input (RO)
0: Not Underflow
1: Underflow
D5 First field Line Buffer Overflow status for Interlace input or
Line buffer Overflow status for Non-interlace input (RO)
0: Not Overflow
1: Overflow
(Rev. 0.95)
D4 First field Line Buffer Underflow status for Interlace input or
Line Buffer Overflow status for Non-interlace input (RO)
0: Not Underflow
1: Underflow
D3 Auto Output Horizontal Total Calculation Start (W)
0: Disable
1: Enable
(R)
0: Ready
1: Not Ready
D2-0 Reserved
(Address
Reg. ACh and ADh.
D7-0 OVDE[7:0]
It defines the high byte of Output Vertical Active Line Number only used for getting the values of
Reg. ACh and ADh.
(Address
D1-0 OVDE[9:8]
Output Horizon t al Total Pixel Number - Low (Address ACh ) (RO)
It states the low byte of Output Horizontal Total Pixel Number.
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It states the high byte of Output Horizontal Total Pixel Residue Number.
Zoom Cont r o l Register 0 (Address B0h) (R/W)
INTERPOLATION TABLE mode (only for Scale Up)
Zoom Contr o l Regist er 1 (Address B 1h) (R/W)
Interpolation Table R/W Access Enable
MTL001
TECHNOLOGY
D7-0 OHTOT[7:0]
Output Horizont al Total Pixel Numb er - High (Address ADh) (RO)
It states the high byte of Output Horizontal Total Pixel Number.
D2-0 OHTOT[10:8]
Output Horizon t al Total Residu e Numb er - Low (Address AEh) (RO)
It states the low byte of Output Horizontal Total Pixel Residue Number.
D7-0 OHTOT_RES[7:0]
Output Horizont al Total Resid ue Number - High (Ad dress AFh) (RO)
D7-2 Reserved
D1-0 OHTOT_RES[9:8]
(Rev. 0.95)
D7 Vertical Scale Mode
0: Scale Up
1: Scale Down
D6-4 Vertical Scale Select
0XX: PASS mode
10X: DUPLICATE mode
110: BILINEAR mode
111:
D3 Horizontal Scale Mode
D2-0 Horizontal Scale Select
D7-1 Reserved
D0
0: scale up
1: scale down
0xx: PASS mode
10x: DUPLICATE mode
110: BILINEAR mode
111: INTERPOLATION TABLE mode
0: Disable
1: Enable
Zoom Vertic al Scale Down Integer Ratio Region (Address B2h) (R/W)
It defines vertical scale down integer ratio value region
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It defines the low byte of vertical scale ratio value for scale up and down.
(Add r es s B5h ) (R/W)
It defines the low byte of vertical scale ratio value for scale up and down.
(Add r es s B7h ) (R/W)
It defines the entry address of the Interpolation table data port.
MTL001
TECHNOLOGY
D7-3 Reserved
D2-0 ZVDIV[2:0]
0 : scale down ratio = 1-1/2(exclude 1)
1 : scale down ratio = 1/2-1/4(exclude 1/2)
2: scale down ratio = 1/4-1/8(exclude 1/4)
3: scale down ratio = 1/8-1/16(exclude 1/8)
4: scale down ratio = 1/16-1/32(exclude 1/16)
Zoom Horizon t al Scale Down Integer Ratio Region (Add r ess B3h) (R/W)
It defines horizontal scale down integer ratio value region.
D7-3 Reserved
D2-0 ZHDIV[2:0]
0 : scale down ratio = 1-1/2(exclude 1)
1 : scale down ratio = 1/2-1/4(exclude 1/2)
2: scale down ratio = 1/4-1/8(exclude 1/4)
3: scale down ratio = 1/8-1/16(exclude 1/8)
4: scale down ratio = 1/16-1/32(exclude 1/16)
(Rev. 0.95)
Zoom Vertic al Scale Ratio – Low (Add ress B4h) (R/W)
D7-0 ZVSF[7:0]
Zoom Vertic al Scale Ratio - High
D7-0 ZVSF[15:8]
For Scale Up ZVSF = CEIL[(input_height – 1)/ (output_height – 1)* 216]
For Scale Down ZVSF = CEIL{[(input_height’ – 1)/ (output_height – 1)-1]* 216}
,where input_height’ = input_height / 2^ZVDIV. The means of ZVDIV is referenced to Reg. B2h.
Zoom Horizon t al Scale Ratio - Low (Add r ess B6h) (R/W)
It defines the low byte of horizontal scale ratio value for scale up and down.
D7-0 ZHSF[7:0]
Zoom Horizo nt al Scale Ratio - High
It defines the high byte of horizontal scale ratio value for scale up and down.
D7-0 ZHSF[15:8]
For Scale Up ZHSF = ROUND[(input_width – 1)/ (output_width – 1)* 216]
For Scale Down ZVSF = ROUND{[(input_width’ – 1)/ (output_width – 1)-1]* 216}
,where input_width’ = input_width / 2^ZHDIV. The means of ZHDIV is referenced to Reg. B3h.
Interpolati o n Table Data Port (Address BFh) (R/W)
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Host Cont r o l Regist er 0 (Address C0h) (R/W)
st Screen Write Stop Enable
Host Screen Write Start Enable
Host Screen Write Ready Flag
Host Cont ro l Regis t er 1 (Addr ess C1h) (R/W)
1: Delay to Display VSYNC
It defines the low byte of the vertical line length for Host Screen Write.
(Add ress C5h) (R/W)
It defines the high byte of the vertical line length for Host Screen Write.
(Add ress C6h) (R/W)
It defines Fill Red color for Host Screen Write.
MTL001
TECHNOLOGY
D7-0 TFPORT[7:0]
D7 Ho
0: Disable
1: Enable
D6-1 Force to 001010
D0
0: Disable
1: Enable
0: Ready
1: Not Ready
D7 Reserved
(Rev. 0.95)
(WO)
(W)
(R)
D6 I2C Bus Address No Increment
0: Normal
1: No Increment
D5 Double Buffer load Select
0: Immediately
D4 Registers Double Buffer function Enable
D3-2 Reserved
D1 Display Registers Double Buffer Load (WO)
D0 Input Registers Double Buffer Load (WO)
Host Screen Write Line Length - Low (Ad dress C4h) (R/W)
D7-0 HS_LEN[7:0]
Host Screen Write Line Length - High
0: Disable
1: Enable
D7-3 Reserved
D2-0 HS_LEN[10:8]
Host Fill RED Color
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(Address C7h) (R/W)
It defines Fill Green color for Host Screen Write.
(Add ress C8h) (R/W)
It defines Fill Blue color for Host Screen Write.
Host Acc ess Mode Status (Address
Contr o l (Add r ess D0h) (R/W)
32 bits Memory Bus (Only for X2 Memory Confi
Memory Self Test Contr o l (Ad d res s D2h) (R/W)
MTL001
TECHNOLOGY
D7-0 HFR[7:0]
Host Fill GREEN Color
D7-0 HFG[7:0]
Host Fill BLUE Color
D7-0 HFB[7:0]
CBh ) (RO)
D7-1 Reserved
D0 Host Access Mode
0: 2-wire Serial mode (IIC)
1: 8-bit Parallel mode
(Rev. 0.95)
Memory Type
It defines the Memory type and size.
D7-5 Reserved
D4
D3 Reserved
D2-0 000: 16M SDRAM X 3
It controls the operation of Memory Self Test Mode.
D7-3 Reserved
0: Disable
1: Enable
001: 16M SDRAM X 2
010: 8M SGRAM X 3
011: 8M SGRAM X 2
10x: Reserved
110: 16M SGRAM X 3
111: 16M SGRAM X 2
guration)
D2 Memory Self Test mode Result Status (RO)
0: Success
1: Fail
D1 Memory Self Test mode Finish Status (RO)
0: Finish
1: Not Finish
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High (Ad d ress D5h) (R/W)
Memory Self-Test Compare Error Add r ess
It defines the low byte of Memory Base Address for Memory Self-Test comparing error report.
Memory Self-Test Compare Error Add r ess
It defines the middle byte of Memory Base Address for Memory Self-Test comparing error report.
Memory Self-Test Compare Error Add r ess
It defines the high byte of Memory Base Address for Memory Self-Test comparing error report
(Add ress E0h) (R/W)
0: Internal Display Clock
1: External Display Clock from pin EXTDCLK
MTL001
TECHNOLOGY
D0 Memory Self Test mode Enable
0: Disable
1: Enable
Memory Line Offset – Low (Address D4h) (R/W)
It defines the low byte of Memory Line Offset Address Length for Memory Read/Write.
D7-0 Line_offset[7:0]
Memory Line Offset –
It defines the high byte of Memory Line Offset Address Length for Memory Read/Write.
D7-3 Reserved
D2-0 Line_offset[10:8]
– Low (Addr ess DBh) (RO)
(Rev. 0.95)
D7-0 MSFTBA [7:0]
– Middle (Address DCh) (RO)
D7-0 MSFTBA [15:8]
– High (Add ress DDh) (RO)
and Patterns Number.
D7 Reserved
D6-5 Memory Self-Test Patterns Number when Comparing Error
00: Pattern Constructed by Linear Memory Address
01: 48 Bits Pattern Toggled between 55 and AA
10: 48 Bits Pattern Toggled between AA and 55
11: Reserved
D4-0 MSFTBA [20:16]
Clock Synthesizer Control Regist er
D7-4 Reserved
D3 Memory Clock Source
0: Internal Memory Clock
1: External Memory Clock from pin EXTMCLK
D2 Display Clock Source
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(Add r es s E1h) (WO)
(Add ress E3h) (R/W)
Clock Syn t hesizer R Value (Addr ess E6h) (R/W)
0: No Display VSYNC pulse detected
1: Any Display VSYNC pulse detec
MTL001
TECHNOLOGY
D1 Memory Clock Synthesizer Enable
0: Enable
1: Disable
D0 Display Clock Synthesizer Enable
0: Enable
1: Disable
Clock Synth esizer Value Load
D7-2 Reserved
D1 Memory Clock Synthesizer Value Load (WO)
D0 Display Clock Synthesizer Value Load (WO)
Display Cloc k Syn t h esi zer N Value (Add r ess E2h) (R/W)
D7-0 Display Clock Synthesizer N value
Display Cloc k Synth esizer M Value
(Rev. 0.95)
D7-0 Display Clock Synthesizer M value
Memory Cloc k Syn t h esi zer N Value (Add r ess E4h) (R/W)
D7-0 Memory Clock Synthesizer N value
Memory Cloc k Syn t h esi zer M Value (Add res s E5h) (R/W)
D7-0 Memory Clock Synthesizer M value
D7-4 Reserved
D3-2 Memory Clock Synthesizer R value
00: No divided
01: Divided by 2
1x: Divided by 4
D1-0 Display Clock Synthesizer R value
00: No divided
01: Divided by 2
1x: Divided by 4
SYNC Interru p t Flag Cont r o l (Add r es s E8h) (R)
It contains the status of SYNC Interrupts.
D7 Display VSYNC Pulse Interrupt Status
D6 Input VSYNC Pulse Interrupt Status
Revision 0.95 - 52 - 2000/06/14
0: No Input VSYNC pulse detected
1: Any Input VSYNC pulse detected
ted
Page 53
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HSYNC Polarity Change Status
HSYNC Frequency Change Status
SYNC Interr u p t Flag Contr o l (Add r ess E8h) (W)
MTL001
TECHNOLOGY
D5 VSYNC Presence Change Status
0: No Change
1: Change
D4 HSYNC Presence Change Status
0: No Change
1: Change
D3 VSYNC Polarity Change Status
0: No Change
1: Change
D2
0: No Change
1: Change
D1 VSYNC Frequency Change Status
0: No Change
1: Change
D0
0: No Change
1: Change
(Rev. 0.95)
It is used to clear the corresponding SYNC interrupt signal when Software finishes
serving the interrupt service routine.
D7 Clear Display VSYNC Pulse Interrupt Enable
0: Disable
1: Enable
D6 Clear Input VSYNC Pulse Interrupt Enable
0: Disable
1: Enable
D5 Clear VSYNC Presence Change Interrupt Enable
0: Disable
1: Enable
D4 Clear HSYNC Presence Change Interrupt Enable
0: Disable
1: Enable
D3 Clear VSYNC Polarity Change Interrupt Enable
0: Disable
1: Enable
D2 Clear HSYNC Polarity Change Interrupt Enable
0: Disable
1: Enable
D1 Clear VSYNC Frequency Change Interrupt Enable
0: Disable
1: Enable
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MYSON
General Interr up t Flag Contr o l (Add res s E9h) (R)
Auto Position Finish Status (valid for Single mode only)
Auto Calibration Finish Status (valid for Single mode only)
General Interru p t Flag Contro l (Add ress E9h) (W)
VSYNC Polarity Change Interrupt Enabl
MTL001
TECHNOLOGY
D0 Clear HSYNC Frequency Change Interrupt Enable
0: Disable
1: Enable
It contains the status of General Interrupts.
D7-2 Reserved
D1
0: Not Finish
1: Finish
D0
0: Not Finish
1: Finish
It is used to clear the corresponding general interrupt signal when Software finishes
serving the interrupt service routine.
(Rev. 0.95)
D7-2 Reserved
D1 Clear Auto Position Finish Interrupt Enable
0: Disable
1: Enable
D0 Clear Auto Calibration Finish Interrupt Enable
0: Disable
1: Enable
SYNC Interr u p t Flag Enable (Address EAh) (R/W)
It is used to enable SYNC Interrupt function.
D7 Display VSYNC Pulse Interrupt Enable
0: Disable
1: Enable
D6 Input VSYNC Pulse Interrupt Enable
0: Disable
1: Enable
D5 VSYNC Presence Change Interrupt Enable
0: Disable
1: Enable
D4 HSYNC Presence Change Interrupt Enable
0: Disable
1: Enable
D3
0: Disable
1: Enable
Revision 0.95 - 54 - 2000/06/14
e
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MYSON
HSYNC Polarity Change Interrupt Enable
HSYNC Frequency Change Interrupt Enable
General Interru p t Flag Enable (Add ress
Interrupt Output Polarity Invert
HS Frequenc y Change Interrup t Comp are (Address
It is used to control Interrupt generation by comparing the frequency change value
MTL001
TECHNOLOGY
D2
0: Disable
1: Enable
D1 VSYNC Frequency Change Interrupt Enable
0: Disable
1: Enable
D0
0: Disable
1: Enable
EBh ) (R/W)
It is used to enable General Interrupt functions.
D7
0: Active Low
1: Active High
D6-2 Reserved
(Rev. 0.95)
D1 Auto Position Finish Interrupt Enable
0: Disable
1: Enable
D0 Auto Calibration Finish Interrupt Enable
0: Disable
1: Enable
ECh) (R/W)
when Input HS Frequency Changes.
D7-0 HSCMPREG[7:0]
Power Management Contr o l (Add r ess F1h) (R/W)
D7 Reserved
D6 Power Down Gamma & Interpolation Table
0: Normal
1: Power Down
D5 Power Down Output Line Buffers
0: Normal
1: Power Down
D4 Power Down Input Line Buffers
0: Normal
1: Power Down
D3-2 Reserved
D1 Power Down all the clocks except REFCLK
0: Normal
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MYSON
GPIO Cont r ol Regist er (Address F4h) (R/W)
Misc Cont r o l (Add r ess F6h) (R/W)
MTL001
TECHNOLOGY
1: Power Down
D0 Software Reset Enable
0: Disable
1: Enable
It controls the data of the GPIO pins.
D7-0 GPIO[7:0]
GPIO Direct i o n Cont r o l (Addres s F5h) (R/W)
It controls the In/Out direction of the GPIO pins, where “0” means Output, and
“1” means Tri_state or Input.
D7-6 GPIO[7:6] Output Enable
0: Output
1: Tri_state
D5-0 GPIO[5:0] In/Out Select
0: Output
1: Input
(Rev. 0.95)
GPIO
It defines the GPIO pins miscellaneous control.
D7-1 Reserved
D0 GPIO[7:6] Output Pins Source
0: from Reg. F4h/D7-6
1: from ADVS/ADHS
Revision 0.95 - 56 - 2000/06/14
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MYSON
5. ELECTRICAL CHA R ACTERISTICS
5.1 DC CHARACTERISTICS
PAR AMETER
MTL001
TECHNOLOGY
Table 5.1 Recommended Operating Conditio ns
SYMBOL
Vcc Operation Voltage 3.0 3.3 3.6 V
Tamb Operating Ambient Temperature 0 70
Tstg Storage Temperature -55 150
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
Vt- Input Schmitt Trigger
Vt+ Input Schmitt Trigger
VOL Output Low Voltage 0.4 V
VOH Output High Voltage 2.4 V
RI Input Pull-up/Down
ILI Input Leakage Current -10 10 uA
ILO Output Leakage Current -20 20 uA
Table 5.2 DC Electric al Characteris t ic s fo r 3.3 V Operation
Low Voltage at pins
SDA and SCK
High Voltage at pins
SDA and SCK
VIL = 0v or
Resistance
VIH = VCC
MIN TYP MAX UNIT
1.0
1.7
75 Kohm
(Rev. 0.95)
o
C
o
C
Revision 0.95 - 57 - 2000/06/14
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MYSON
5.2 AC CHARA CTERISTICS
PARAMETER
MTL001
TECHNOLOGY
¨ Inpu t Interface Timin g
Figur e 5.2.1 Input Interface Timing
IPCLK
Input VS/HS
PIXIN[23:0]
(Rev. 0.95)
TivhhTivhs
Tids
Tidh
Table 5.2.1 Input Interface Timing
SYMBOL
Tids Input Image Signal Setup Time for IPCLK 2 ns
Tidh Input Image Signal Hold Time for IPCLK 3 ns
Tivhs Input VSYNC/HSYNC Setup Time for IPCLK 2 ns
Tivhh Input VSYNC/HSYNC Hold Time for IPCLK 3 ns
MIN MAX UNIT
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MYSON
PARAMETER
Display VSYNC Output Delay to DDCLK
Display HSYNC Output Delay to DDCLK
Display DDEN Output Delay to DDCLK
Display Data Output Delay to DDCLK
MTL001
TECHNOLOGY
¨ Outpu t Interface Ti m in g
Figur e 5.2.2 Outpu t Interface Timing
DDCLK
Display VS
Display HS
(Rev. 0.95)
Tdvs
Tdhs
Tdde
Display DDEN
Tddp
PIXOUT1[23:0] / PIXOUT2[23:0]
Table 5.2.2 Output Interface Timing
SYMBOL
Tdck Display Clock DDCLK Frequency 10 ns
Tdvs
Tdhs
Tdde
Tddp
Note: DDCLK phase can be adjusted relative to data and control outputs using the DDCLK_INV
(Reg. A4h/D5-4) and DDCLK_DELAY[2:0] (Reg. A6h/D7-0) programming controls.
MIN MAX UNIT
2 ns
0.5 ns
1 ns
1.5 ns
Revision 0.95 - 59 - 2000/06/14
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MYSON
PARAMETER
OSD VS / HS Output Delay to OCLK
MTL001
TECHNOLOGY
¨ OSD Interface Timin g
Figur e 5.2.3 OSD Interface Timin g
OCLK
OVSYNC / OHSYNC
Input OSDDEN / OSDRED /
OSDGRN / OSDBLU
(Rev. 0.95)
Tosdd
Tosds Tosdh
Table 5.2.3 OSD Interf ace Timin g
SYMBOL
Tosdd
Tosds OSD Signal Input Setup Time for OCLK 5.5 ns
Tosdh OSD Signal Input Hold Time for OCLK 0 ns
Note: OCLK phase can be adjusted using OCLK_INV (Reg. A1h/D3) programming control and OHSYNC
phase can be adjusted using OHSYNC_DELAY[1:0] (Reg. A1h/D5-4) programming control.
MIN MAX UNIT
2 ns
Revision 0.95 - 60 - 2000/06/14
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MYSON
PARAMETER
MTL001
TECHNOLOGY
¨ I2C Host Interf ace Tim i n g
Figur e 5.2.4 I2C Host Interface Timin g
Thigh
Tsu:sta Thd:sto
Thd:sta
Tlow
Tsu:dat
Thd:dat
(Rev. 0.95)
Tsu:sto
Table 5.2.4 I2C Host Interface Timin g
SYMBOL
Thigh Clock High Period 500 ns
Tlow Clock Low Period 500 ns
Tsu:dat Data in Setup Time 200 ns
Thd:dat Data in Hold Time 100 ns
Tsu:sta Start condition Setup Time 500 ns
Thd:sta Start condition Hold Time 500 ns
Tsu:sto Stop condition Setup Time 500 ns
Thd:sto Stop condition Hold Time 500 ns
MIN MAX UNIT
Revision 0.95 - 61 - 2000/06/14
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MYSON
PARAMETER
WR/RD Pulse Width
ALE Low to WR/RD Low
WR/RD High to ALE High
WR/RD
MTL001
TECHNOLOGY
¨ 8-bit Direct Host Interface Timing
Figur e 5.2.5 8-bit Direct Host Interface Timing
ALE
Tllwl Trwpw
Tavll Tllax
AD(7:0)/WR
A0-A7
(Rev. 0.95)
Twhlh
Tqvwh
DATA IN
AD(7:0)/RD
Trlaz
Table 5.2.5 8-bit Direct Host Interface Timing
SYMBOL
Tavll Addr ess Valid to ALE Low 3 ns
Tllax Address Hold After A LE Low 5 ns
Trwpw
Tllwl
Tqvwh Data Valid to WR High 3 ns
Twhqx Data Hold After WR 10 ns
Twhlh
Trlaz RD Low to Address Float -5 ns
Trldv RD Low to Valid Data In 30 ns
Trhdz Data Float after RD High 0 15 ns
DATA OUTA0-A7
TrhdzTrldv
MIN MAX UNIT
35 ns
5 ns
0 ns
Revision 0.95 - 62 - 2000/06/14
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MYSON
PARAMETER
Memory Output Delay to MCK
MCKE, MCS#, MRAS#,
MCAS#, MWE#,
DQM[1:0], MA[11:0]
mck
MTL001
TECHNOLOGY
¨ Memory Interf ac e (SDRAM/SGRAM) Tim i n g
Figur e 5.2.6 Memory Interface Timing
T
Tmch
MCK
Tmds Tmdh
MD[47:0]
Tmod
(Rev. 0.95)
Table 5.2.6 Memor y Interface Timi ng
SYMBOL
Tmck Memory Clock Cycle Time 8.5 ns
Tmch/Tmck Memory Clock Duty Cycle 0.4 0.6 ns
Tmds Data-in Setup Time for MCK 1 ns
Tmdh Data-in Hold Time for MCK 2 ns
Tmod
MIN MAX UNIT
2 8.5 ns
Revision 0.95 - 63 - 2000/06/14
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MYSON
6. PACKAGE DIMENSION
3
D
A-B
b
A-B D
A-B D
e
EE1E2
D1
B
A
S
S
L
0.25mm
0.05
;L1
S
MTL001
TECHNOLOGY
120/128/132/144/160/184/208/256L OFP
28 X 28 X 3.32 mm
2.6mm FOOTPRINT
1
D2
D
4X
ddd
4X
bbb
C
aaa
(Rev. 0.95)
A2
C
H
S
A1
C
2
R1
R2
GAGE PLANE
ccc
C
MIN. NOM. MAX. MIN. NOM. MAX.
0.13 0.16 0.23 0.005 0.006 0.009
0.40 BSC. 0.016 BSC.
25.20 0.992
25.20 0.992
TOLERANCES OF FORM AND POSITION
0.20 0.008
0.20 0.008
X 0.08 X X 0.003 X
X 0.07 X X 0.003 X
NOTES:
1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
2. SIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE
LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE
THAN 0.08mm.
DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE
FOOT. THE MINIMUM SPACE BETWEEN PROTRUSION AND AN
ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 mm.
3. THE TOP PACKAGE BOOY SIZE MAY BE SMALLER THAN THE
BOTTOM PACKAGE BOOY SIZE.
C
SEATING PLANE
SYMBOL
MILLIMETER INCH
MIN. NOM.
A X X 4.10 X X 0.161
A1 0.25 X X 0.010 X X
A2 3.20 3.32 3.60 0.126 0.131 0.142
D 30.60 BSC 1.205 BSC
D1 28.00 BSC 1.102 BSC
E 30.60 BSC 1.205 BSC
E1 28.00 BSC 1.102 BSC
R2 0.08 X 0.25 0.003 X 0.010
R1 0.08 X 0.003 X X
0° 3.5° 7° 0° 3.5° 7°
1 0° X X 0° X X
2 8° REF 8° REF
3 8° REF 8° REF
C 0.09 0.15 0.20 0.004 0.005 0.008
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.30 0.051 REF
MAX
MIN. NOM. MAX.
.
Revision 0.95 - 64 - 2000/06/14
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