Datasheet MT89L80AP, MT89L80AN Datasheet (MITEL)

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Page 1

CMOS ST-BUS FAMILY

MT89L80

Digital Switch

Advance Information

Features

• 3.3 volt supply

• 5V tolerant inputs and TTL compatible outputs.

• 256 x 256 channel non-blocking switch

• Accepts serial streams at 2.048Mb/s

• Per-channel three-state control

• Patented per channel message mode

• Non-multiplexed microprocessor interface

• Mitel ST-BUS compatible

• Low power consumption: typical 15mW

• Pin compatible with the MT8980DP

Applications

• Key telephone systems

• PBX systems

• Small and medium voice switching systems

DS5196 ISSUE 2 September 1999

Ordering Information

MT89L80AP 44 Pin PLCC MT89L80AN 48 Pin SSOP

-40°C to +85°C

Description

This VLSI CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digital exchange, PBX or Central Ofﬁce. It provides simultaneous connections for up to 256 64 kbit/s channels. Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s ST-BUS stream. In addition, the MT89L80 provides microprocessor read and write access to individual ST-BUS channels.

STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7

** for 48-pin SSOP only

Serial

Parallel

Converter

Data

Memory

RESET

F0i

C4i

Frame

Counter

Control Register

Control Interface

CS R/W A5/A0DTA D7/

Figure 1 - Functional Block Diagram

Output

MUX

Connection

Memory

CSTo

ODE

Parallel

Serial

Converter

STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7

2-3

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MT89L80 Advance Information

STi3 STi4 STi5

STi6

STi7

F0i

C4i

A0 A1 A2

STi1

STi2

STi0

65432

7 8 9 10 11 12 13 14 15 16 17

1819202122

44 PIN PLCC

DTA

ODE

CSTo

4443424140

2425262728

STo1

STo0

STo2

39 38 37 36 35 34 33 32 31 30 29

STo3 STo4 STo5 STo6 STo7 V

D0 D1 D2 D3 D4

V DTA STi0 STi1 STi2

NC STi3 STi4 STi5

STi6 STi7

RESET

C4i

R/W

2 3 4 5 6 7 8

9 10 11 12

13 14

F0i

15 16

19 20

23 24

48 PIN SSOP

(JEDEC MO-118, 300mil Wide)

48 47 46 45 44

43 42 41 40 39 38 37 36

35 34 33 32 31 30 29 28 27 26

CSTo ODE STo0 STo1 STo2 NC STo3

STo4

STo5 STo6 STo7

Figure 2 - Pin Connections

Pin Description

Pin #

PLCC48SSOP

22DTA Data Acknowledgment (5V Tolerant Three-state Output). This active low output

3-5 3-5 STi0-2 ST-BUS Inputs 0 to 2 (5V-tolerant Inputs). Serial data input streams. These streams

7-11 7-11 STi3-7 ST-BUS Inputs 3 to 7 (5V-tolerant Inputs). Serial data input streams. These streams

12 12,36 V

13 RESET Device Reset ( 5v-tolerant input). This pin is only available for the 48-pin SSOP

13 14 F0i Frame Pulse (5V-tolerant Input). This is the input for the frame synchronization

Name Description

indicates that a data bus transfer is complete. A pull-up resistor is required at this output.

have data rates of 2.048Mbit/s with 32 channels.

may have data rates of 2.048Mbit/s with 32channels.

+3.3 Volt Power Supply.

package.This active low input puts the device in its reset state. It clears the internal counters and registers. All ST-BUS outputs are set to the high impedance state. In normal operation. The RESET pin must be held low for a minimum of 100nsec to reset the device.

pulse for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to reset on the next negative transition of C4i.

14 15 C4i 4.096 MHz Clock (5V-tolerant Input). ST-BUS bit cell boundaries lie on the alternate

falling edges of this clock.

15-17 16-18 A0-2 Address 0-2 / Input Streams 8-10 (5V-tolerant Input). These are the inputs for the

address lines on the microprocessor interface.

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Page 3

Advance Information MT89L80

Pin Description (continued)

Pin #

PLCC48SSOP

19-21 20-22 A3-5 Address 3-5 / Input Streams 11-13 (5V-tolerant Input). These are the inputs for the

22 23 DS Data Strobe (5V-tolerant Input). This is the input for the active high data strobe on the

23 24 R/W Read/Write (5V-tolerant Input). This is the input for the read/write signal on the

24 26 CS Chip Select (5V-tolerant Input). This is the input for the active low chip select on the

25-27 27-29 D7-D5 Data Bus (5V -tolerant I/O): These are the bidirectional data pins on the microprocessor

29-33 31-35 D4-D0 Data Bus (5V -tolerant I/O): These are the bidirectional data pins on the microprocessor

Name Description

address lines on the microprocessor interface.

microprocessor interface.

microprocessor interface - high for read, low for write.

microprocessor interface

interface.

34 1,

25,37

35-39 38-42 STo7-3 ST-BUS Outputs 7 to 3 (5V-Tolerant Three-state Outputs). These are the pins for the

41-43 44-46 STo2-0 ST-BUS Outputs 2to 0 (5V-Tolerant Three-state Outputs). These are the pins for the

44 47 ODE Output Drive Enable (5V -tolerant Input). If this input is held high, the STo0-STo7 output

1 48 CSTo Control ST-BUS Output (5V-Tolerant Output). Each frame of 256 bits on this ST-BUS

6, 18,

28, 40

6, 19,

30, 43

Ground.

eight 2048 kbit/s ST-BUS output streams.

eight 2048kbit/s ST-BUS output streams.

drivers function normally. If this input is low, the STo0-STo7 output drivers go into their high impedance state. NB: Even when ODE is high, channels on the STo0-STo7 outputs can go high impedance under software control.

output contains the values of bit 1 in the 256 locations of the Connection Memory High. No Connection.

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MT89L80 Advance Information

Functional Description

In recent years, there has been a trend in telephony towards digital switching, particularly in association with software control. Simultaneously, there has been a trend in system architectures towards distributed processing or multi-processor systems.

In accordance with these trends, MITEL has devised the ST-BUS (Serial Telecom Bus). This bus architecture can be used both in software-controlled digital voice and data switching, and for interprocessor communications. The uses in switching and in interprocessor communications are completely integrated to allow for a simple general purpose architecture appropriate for the systems of the future.

The serial streams of the ST-BUS operate continuously at 2048 kbit/s and are arranged in 125 µs wide frames which contain 32 8-bit channels. MITEL manufactures a number of devices which interface to the ST-BUS; a key device being the MT89L80 chip.

The MT89L80 can switch data from channels on STBUS inputs to channels on ST-BUS outputs, and simultaneously allows its controlling microprocessor to read channels on ST-BUS inputs or write to channels on ST-BUS outputs (Message Mode). To the microprocessor, the MT89L80 looks like a memory peripheral. The microprocessor can write to the MT89L80 to establish switched connections between input ST-BUS channels and output ST-BUS channels, or to transmit messages on output ST-BUS channels. By reading from the MT89L80, the microprocessor can receive messages from ST-BUS input channels or check which switched connections have already been established.

By integrating both switching and interprocessor communications, the MT89L80 allows systems to use distributed processing and to switch voice or data in an ST-BUS architecture.

Hardware Description

Serial data at 2048 kbit/s is received at the eight STBUS inputs (STi0 to STi7), and serial data is transmitted at the eight ST-BUS outputs (STo0 to STo7). Each serial input accepts 32 channels of digital data, each channel containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec (e.g., MITEL’s MT8964).

This serial input word is converted into parallel data and stored in the 256 X 8 Data Memory . Locations in the Data Memory are associated with particular channels on particular ST-BUS input streams. These locations can be read by the microprocessor which controls the chip.

Locations in the Connection Memory, which is split into high and low parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input, then the contents of the Connection Memory Low location associated with the output channel is used to address the Data Memory. This Data Memory address corresponds to the channel on the input ST-BUS stream on which the data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode), then the contents of the Connection Memory Low location associated with the output channel are output directly, and this data is output repetitively on the channel once every frame until the microprocessor intervenes.

The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives address information at A5 to A0 and handles the microprocessor control signals CS, DTA, R/W and DS. There are two parts to any address in the Data Memory or Connection Memory.

A5 A4 A3 A2 A1 A0 Hex Address Location

0 1 1

•

* Writing to the Control Register is the only fast transaction.

†

Memory and stream are speciﬁed by the contents of the Control Register.

2-6

0 0 0

•

0 0 0

•

0 0 0

•

0 0 0

•

0 0 1

•

Figure 3- Address Memory Map

00 - 1F

20 21

•

Control Register *

Channel 0 Channel 1

Channel 31

† †

•

†

Page 5

Advance Information MT89L80

The higher order bits come from the Control Register, which may be written to or read from via the Control Interface. The lower order bits come from the address lines directly.

The Control Register also allows the chip to broadcast messages on all ST-BUS outputs (i.e., to put every channel into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the Connection Memory Low. The Connection Memory High determines whether individual output channels are in Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of MT89L80s to be constructed. It also controls the CSTo pin.

All ST-BUS timing is derived from the two signals C4i and F0i.

Software Control

The address lines on the Control Interface give access to the Control Register directly or, depending on the contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory.

If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory and stream selected in the Control Register.

The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and the stream address bits deﬁne one of the ST-BUS input or output streams.

Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the Connection Memory Low.

The other mode control bit, bit 6, puts every output channel on every output stream into active Message Mode; i.e., the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1, regardless of the actual values.

(unused)

Mode

Control

Bits

76543210

Memory

Select

Bits

Stream

Address

Bits

Bit Name Description

7 Split Memory When 1, all subsequent reads are from the Data Memory and writes are to the Connection

Memory Low, except when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for subsequent operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.

6 Message

Mode

When 1, the contents of the Connection Memory Low are output on the Serial Output streams except when the ODE pin is low. When 0, the Connection Memory bits for each channel determine what is output.

5 (unused)

4-3 Memory

Select Bits

0-0 - Not to be used 0-1 - Data Memory (read only from the microprocessor port) 1-0 - Connection Memory Low 1-1 - Connection Memory High

2-0 Stream

Address Bits

The number expressed in binary notation on these bits refers to the input or output ST-BUS stream which corresponds to the subsection of memory made accessible for subsequent operations.

Figure 4 - Control Register Bits

2-7

Page 6

MT89L80 Advance Information

No Corresponding Memory

- These bits give 0s if read.

76 543210

Per Channel

Control Bits

Bit NameE Description

2 Message

Channel

When 1, the contents of the corresponding location in Connection Memory Low are output on the location’s channel and stream. When 0, the contents of the corresponding location in Connection Memory Low act as an address for the Data Memory and so determine the source of the connection to the location’s channel and stream.

1 CSTo Bit This bit is output on the CSTo pin one channel early. The CSTo bit for stream 0 is output

ﬁrst.

0 Output

Enable

If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the output driver for the location’s channel and stream. This allows individual channels on individual streams to be made high-impedance, allowing switching matrices to be constructed. A 1 enables the driver and a 0 disables it.

Figure 5 - Connection Memory High Bits

Stream

Address

Bits

76 543210

Channel Address

Bits

Bit Name Description

7-5* Stream

Address

Bits*

4-0* Channel

Address

Bits*

The number expressed in binary notation on these 3 bits is the number of the ST-BUS stream for the source of the connection. Bit 7 is the most signiﬁcant bit. e.g., if bit 7 is 1, bit 6 is 0 and bit 5 is 0, then the source of the connection is a channel on STi4.

The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the connection (The ST-BUS stream where the channel lies is deﬁned by bits 7, 6 and 5.). Bit 4 is the most signiﬁcant bit. e.g., if bit 4 is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.

*If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to deﬁne the source of the connection which is output on the channel and stream associated with this location.

Figure 6 - Connection Memory Low Bits

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Advance Information MT89L80

If bit 6 of the Control Register is 0, then bits 2 and 0 of each Connection Memory High location function normally (see Fig. 5). If bit 2 is 1, the associated STBUS output channel is in Message Mode; i.e., the byte in the corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low deﬁne the ST-BUS input stream and channel where the byte is to be found (see Fig. 6).

If the ODE pin is low, then all ser ial outputs are highimpedance. If it is high and bit 6 in the Control Register is 1, then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the Connection Memory High location enables the output drivers for the corresponding individual ST-BUS output stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Fig. 5).

Bit 1 of each Connection Memory High location (see Fig. 5) is output on the CSTo pin once every frame. To allow for delay in any external control circuitry the bit is output one channel before the corresponding channel on the ST-BUS streams, and the bit for stream 0 is output ﬁrst in the channel; e.g., bit 1’s for channel 9 of streams 0-7 are output synchronously with ST-BUS channel 8 bits 7-0.

Fig. 7 shows the interface between the MT89L80s and the ﬁlter/codecs. Fig. 8 shows the position of these components in an example architecture.

The MT8964 ﬁlter/codec in Fig. 7 receives and transmits digitized voice signals on the ST-BUS input DR, and ST-BUS output DX, respectively. These signals are routed to the ST-BUS inputs and outputs on the top MT89L80, which is used as a digital speech switch.

The MT8964 is controlled by the ST-BUS input D originating from the bottom MT89L80, which generates the appropriate signals from an output channel in Message Mode. This architecture optimizes the messaging capability of the line circuit by building signalling logic, e.g., for on-off hook detection, which communicates on an ST-BUS output. This signalling ST-BUS output is monitored by a microprocessor (not shown) through an ST-BUS input on the bottom MT89L80.

Fig. 8 shows how a simple digital switching system may be designed using the ST-BUS architecture. This is a private telephone network with 256 extensions which uses a single MT89L80 as a speech switch and a second MT89L80 for communication with the line interface circuits.

Applications

Use in a Simple Digital Switching System

Figs. 7 and 8 show how MT89L80s can be used with MT8964s to form a simple digital switching system.

STo0 STi0

89L80 used

speech

switch

89L80 used

in message

mode for

control and

signalling

MT89L80

STo0 STi0

Line Interface Circuit with 8964 Filter/Codec

MT8964

Filter/Codec

Signalling

Logic

Line Driver

and

2- to 4-

Wire

Converter

Figure 7 - Example of Typical Interface between 89L80s and 8964s for Simple Digital Switching System

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MT89L80 Advance Information

Line Interface Circuit

with Codec (e.g. 8964)

Line 1

Controlling

Micro-

Processor

Speech

Switch

89L80

Control &

Signalling

89L80

STo0-7

STi0-7

STo0-7

STi0-7

•

Repeated for Lines

2 to 255

Line Interface Circuit

with Codec (e.g.8964)

Line 256

Figure 8 - Example Architecture of a Simple Digital Switching System

•

Repeated for Lines

2 to 255

2-10

Page 9

Advance Information MT89L80

Absolute Maximum Ratings*

Parameter Symbol Min Max Units

1 Supply Voltage -0.3 5.0 V 2 Voltage on any I/O pin (except supply pins) V 3 Current at Digital Outputs I 4 Storage Temperature T 5 Package Power Dissipation P

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions - Voltages are with respect to ground (V

VSS-0.3 VDD+0.3 V

-55 +125 °C

) unless otherwise stated.

Characteristics Sym Min Typ Max Units Test Conditions

1 Operating Temperature T 2 Positive Supply V 3 Input High Voltage V 4 Input High Voltage on 5V Tolerant Inputs V 5 Input Low Voltage V

OP DD

IH IH IL

DC Electrical Characteristics - Voltages are with respect to ground (V

Characteristics Sym Min Typ

1 2 Input High Voltage V 3 Input Low Voltage V 4 Input Leakage I 5 Input Pin Capacitance C 6 7 Output High Current I 8 Output Low Voltage V

9 Output Low Current I 10 High Impedance Leakage I 11 Output Pin Capacitance C

‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. *

Supply Current I

I N P U T S

Output High Voltage V

O U

P U

0.7V

0.8V 10 mA Sourcing. VOH=2.4V

5 mA Sinking. VOL = 0.4V

-40 +85 °C

3.0 3.6 V

0.7V

‡

0.3V

) unless otherwise stated.

Max Units Test Conditions

4 7 mA Outputs unloaded

0.3V

5 µAVI between VSS and V

10 pF

0.4 V IOL = 5 mA

5 µAVO between VSS and V

10 pF

5.5 V

V V

VIOH = 10 mA

20 mA

AC Electrical Characteristics _Timing Parameter Measurement Voltage Levels

Characteristics Sym Level Units Test Conditions

1 CMOS Threshold Voltage V 2 CMOS Rise/Fall Threshold Voltage high V 3 CMOS Rise/Fall Threshold Voltage low V

0.5V

0.7V

0.3V

V V V

2-11

Page 10

MT89L80 Advance Information

AC Electrical Characteristics† - Clock Timing (Figures 9 and 10)

Characteristics Sym Min Typ

‡

Max Units Test Conditions

1 2 Clock Width High t 3 Clock Width Low t 4 Clock Transition Time t 5 Frame Pulse SetupTime t 6 Frame Pulse Hold Time t 7 Frame Pulse Width t

† Timing is over recommended temperature & power supply voltages. ‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.

NB: Frame Pulse is repeated every 512 cycles of C4i.

C4i

F0i

Clock Period* t

I N P U T S

CLK

CTT

FPS

FPH

FPW

220 244 300 ns

85 122 150 ns 85 122 150 ns

10 ns 10 190 ns 10 190 ns

244 ns

BIT CELLS

C4i

F0i

Channel 31

Bit o

Channel 0

Bit 7

Figure 9- Frame Alignment

CLK

FPH

CTT

FPS

CHL

FPW

CTT

FPH

FPS

2-12

Figure 10 - Clock Timing

Page 11

Advance Information MT89L80

AC Electrical Characteristics† - Serial Streams (Figures 11, 12 and 13)

Characteristics Sym Min Typ‡Max Units Test Conditions

1 2 STo0/7 Delay - High Z to Active t 3 STo0/7 Delay - Active to Active t 4 Output Driver Enable Delay t 5 External Control Delay t 6 7 Serial Input Hold Time t

† Timing is over recommended temperature & power supply voltages. ‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.

C4i

STo0/7 Delay - Active to High Z t

O U

T P U

T S

Serial Input Setup Time t

Bit Cell Boundary

SAZ

SZA

SAA

OED

XCD

SIS

SIH

555nsR 555nsC 555nsC

=1 KΩ*, CL=150 pF

=150 pF

50 ns RL=1 KΩ*, CL=150 pF

55 ns CL=150 pF 20 ns 20 ns

ODE

STo0 to STo7

CSTo

SAZ

SZA

SAA

XCD

Figure 11 - Serial Outputs and External Control

STo0 to STo7

C4i

STi0 to STi7

HM LM

OED

Figure 12 - Output Driver Enable

Bit Cell Boundaries

Figure 13 - Serial Inputs

SIS

SIH

2-13

Page 12

MT89L80 Advance Information

AC Electrical Characteristics† - Processor Bus (Figures 14)

Characteristics Sym Min Typ

‡

Max Units Test Conditions

1 Chip Select Setup Time t 2 Read/Write Setup Time t 3 Address Setup Time t

CSS

RWS

ADS

0ns 5ns 5ns

4 Acknowledgment Delay

Control Register Read Control Register Write t Connection Memory Read t Connection Memory Write t

Data Memory Read t 5 Fast Write Data Setup Time t 6 Slow Write Data Delay t 7 Read Data Setup Time t 8 Data Hold Time Read

Write

9 Read Data To High Impedance t

10 Chip Select Hold Time t 11 Read/Write Hold Time t 12 Address Hold Time t 13 Acknowledgment Hold Time t

AKD

FWS

SWD

RDS

DHT

RDZ

CSH

RWH

ADH

AKH

0ns

0nsC

10 90 ns RL=1 KΩ∗, CL=150 pF

510 ns

15 50 90 ns RL=1 KΩ∗, CL=150 pF

0ns 0ns 8ns

52 120 ns CL=150 pF 25 65 ns CL=150 pF

62 120 ns CL=150 pF 30 53 ns CL=150 pF

560 1220 ns CL=150 pF

122 ns

= 150 pF

50 80 ns RL=1 KΩ∗, CL=150 pF

A5 to A0

DTA

D7 to D0

CSS

RWS

ADS

SWD

RDS

AKD

FWS

AKH

DHT

RDZ

CSH

RWH

ADH

Figure 14 - Processor Bus

2-14

Page 13

Pin 1

Package Outlines

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin

5) A & B Maximum dimensions include allowable mold flash

20-Pin 24-Pin 28-Pin 48-Pin

Dim

Min Max Min Max Min Max Min Max

A 0.079

(2)

A10.002

(0.05)

B 0.0087

(0.22)

C 0.008

D 0.27

(6.9)

E 0.2

(5.0)

e 0.025 BSC

(0.635 BSC)

A20.065

(1.65)

H 0.29

(7.4)

L 0.022

(0.55)

0.013

(0.33)

(0.21)

0.295 (7.5)

0.22 (5.6)

0.073

(1.85)

0.32 (8.2)

0.037

(0.95)

- 0.079

0.002 (0.05)

0.0087 (0.22)

0.31

(7.9)

0.2

(5.0)

0.025 BSC

(0.635 BSC)

0.065 (1.65)

0.29

(7.4)

0.022 (0.55)

(2)

0.013

(0.33)

0.008

(0.21)

0.33

(8.5)

0.22

(5.6)

0.073

(1.85)

0.32

(8.2)

0.037

(0.95)

0.002 (0.05)

0.0087 (0.22)

0.39 (9.9)

0.2

(5.0)

0.025 BSC

(0.635 BSC)

0.065 (1.65)

0.29 (7.4)

0.022 (0.55)

0.079 (2)

0.013

(0.33)

0.008 (0.21)

0.42

(10.5)

0.22 (5.6)

0.073 (1.85)

0.32 (8.2)

0.037 (0.95)

0.095 (2.41)

0.008 (0.2)

0.62

(15.75)

0.291

(7.39)

0.025 BSC

(0.635 BSC)

0.089

(2.26)

0.395

(10.03)

0.02

(0.51)

0.110 (2.79)

0.016

(0.406)

0.0135 (0.342)

0.010 (0.25)

0.63

(16.00)

0.299 (7.59)

0.099 (2.52)

0.42

(10.67)

0.04

(1.02)

Small Shrink Outline Package (SSOP) - N Sufﬁx

General-11

Page 14

Package Outlines

e: (lead coplanarity)

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

4) For D & E add for allowable Mold Protrusion 0.010"

Dim

D/E

D1/E

D2/E

20-Pin 28-Pin 44-Pin 68-Pin 84-Pin

Min Max Min Max Min Max Min Max Min Max

0.165 (4.20)

0.090

(2.29)

0.385 (9.78)

0.350

(8.890)

0.290

(7.37)

0.026

(0.661)

0.013

(0.331)

0.020 (0.51)

0.180

(4.57)

0.120 (3.04)

0.395

(10.03)

0.356

(9.042)

0.330 (8.38)

0 0.004 0 0.004 0 0.004 0 0.004 0 0.004

0.032

(0.812)

0.021

(0.533)

0.050 BSC (1.27 BSC)

0.165

(4.20)

0.090 (2.29)

0.485

(12.32)

0.450

(11.430)

0.390 (9.91)

0.026

(0.661)

0.013

(0.331)

0.050 BSC (1.27 BSC)

0.020 (0.51)

0.180 (4.57)

0.120 (3.04)

0.495

(12.57)

0.456

(11.582)

0.430

(10.92)

0.032

(0.812)

0.021

(0.533)

0.165

(4.20)

0.090

(2.29)

0.685

(17.40)

0.650

(16.510)

0.590

(14.99)

0.026

(0.661)

0.013

(0.331)

0.050 BSC (1.27 BSC)

0.020

(0.51)

0.180 (4.57)

0.120 (3.04)

0.695

(17.65)

0.656

(16.662)

0.630

(16.00)

0.032

(0.812)

0.021

(0.533)

0.165

(4.20)

0.090

(2.29)

0.985

(25.02)

0.950

(24.130)

0.890

(22.61)

0.026

(0.661)

0.013

(0.331)

0.050 BSC (1.27 BSC)

0.020

(0.51)

0.200

(5.08)

0.130

(3.30)

0.995

(25.27)

0.958

(24.333)

0.930

(23.62)

0.032

(0.812)

0.021

(0.533)

(30.10)

(29.210)

(27.69)

(0.661)

(0.331)

0.165

(4.20)

0.090 (2.29)

1.185

1.150

1.090

0.026

0.013

0.050 BSC (1.27 BSC)

0.020 (0.51)

0.200

(5.08)

0.130

(3.30)

1.195

(30.35)

1.158

(29.413)

1.130

(28.70)

0.032

(0.812)

0.021

(0.533)

General-10

Plastic J-Lead Chip Carrier - P-Sufﬁx

Page 15

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