The MT8924 is designed to provide conference call
capability in digital switching systems. It allows up to
10 independent conferences to be set for up to 32
PCM voice channels.
A/µ-Law companded data from the PCM input port is
converted to linear format, processed by a dedicated
arithmetic unit, re-converted to companded format
and then sent to the PCM output port.The PCM
output signal contains all the information of each
channel connected in conference except its own.
Programmable attenuation and noise suppression
are provided for channels connected in conference
or transparent mode. Additionally, an input for an
external tone is featured that can be used as a signal
to indicate to connected parties that they are on a
conference call.
DSTi
OS
Overflow
Attenuation/Noise Suppression
Channel RAM
µ/A-Law
to
Linear
Serial-to-Parallel
Conversion
PCM Mode
Control
RESETWRRD
µ
A/
Timebase
F0i CkoD0-D7TDTF
Cki
and
Adder
PCM Tone
Generator
MUX
Figure 1 - Functional Block Diagram
Linear
to
µ/A-Law
Parallel-to-Serial
Conversion
Control
CS
DSTo
D
C/
8-3
Page 2
MT8924Preliminary Information
TD
TF
RESET
OS
DSTo
D7
D6
D5
D4
D3
D2
D1
10
11
12
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
VSS
A/
µ
DSTi
Cko
Cki
F0i
WR
RD
CS
C/
D
VDD
D0
Figure 2 - Pin Connections
Pin Description
Pin #NameDescription
1TDTone Duration (Input). When TD is High, a PCM-coded tone is sent out to all channels of
the enabled conferences instead of PCM data. TD is latched by frame pulse F0i so that all
channels have the same tone during the same frame number. When TD is Low, normal
operation is enabled.
2TFTone Frequency (Input). This input is connected to an external squarewave generator. TF
is strobed by frame pulse F0i so that all channels have the same tone frequency during the
same number of frames. The PCM-coded tone level corresponds to 1/10th of the full scale
value, and is activated when TD is High.
3RESETMaster RESET (Input). This input is used for system reset after power up, or when the
companding law format has been changed. The RESET pin is strobed by the rising edge of
clock Cki. Complete circuit initialization takes two frame periods. Resetting the device
disables the output drivers of the microprocessor interface and DSTo.
4OSOverflow Signalling (Output). When OS is Low , a conference is in the overflo w condition.
This signal is delayed by half of a timeslot relative to the beginning of the output channel of
the conference in overflow (see Figure 9).
5DST
ST-BUS Serial Output. This pin is the output for the PCM signal. It is enabled upon
o
channel selection, otherwise it is placed in a high impedance state. Maximum bit rate is
2.048 Mb/s.
6-13D7 to D0 Data Bus I/O Port. These are bidirectional data pins over which data and instructions are
transferred to and from the microprocessor (where D0 is the least significant bit). The bus is
in a high impedance state when RESET is Low and/or CS is High.
14V
DD
Positive Supply Voltage. Nominally 5 volts.
15C/DContr ol/Data Select (Input). The signal on this input defines whether the inf ormation on the
data bus should be interpreted as opcode or data. During a write operation a Low signal
defines the bus content as data, while a High signal defines it as opcode. During a read
operation this input differentiates overflow status between the first eight channels for C/D
being LOW, and the last two channels f or C/D being HIGH (see Instruction 4). This input also
allows status monitoring (see Instruction 6) during a read operation.
16CSChip Select (Input). This active low input selects the device for microprocessor read/write
operations. When CS is Low, data and instructions can be transferred to or from the
microprocessor, and when CS is High, the data bus is in a high impedance state.
17RDRead (Input). This active low input is for the read signal on the microprocessor interface.
The data bus is updated on the falling edge of RD.
18WRWrite Input. This active low input is for the write signal on the microprocessor interface. The
data bus is strobed on the rising edge of WR.
8-4
Page 3
Preliminary InformationMT8924
Pin Description (continued)
Pin #NameDescription
19F0iFrame Pulse (Input). This is an 8 kHz active low input used for frame synchronization of the
PCM bit stream. The first falling edge of Cki following the falling edge of frame pulse F0i
determines the start of a new frame and must correspond to the first bit of the first channel.
When PCM frames of 1544 kbit/s are used, the rising edge of F0i must correspond to the
Extra (193rd) bit.
20CkiClock (Input). This signal is the timing reference used for all internal operations. The PCM
bit cell boundaries lie on the alternate falling edges of this clock. The maximum allowable
clock frequency is 4096 kHz.
21CkoClock (Output). This pin provides the master clock for a digital crosspoint switch (e.g.,
MT898x series, or the MT9080, MT9085 combination). Normally the signal on this pin is
identical to Cki. When Extra bit operating mode is selected (see Instruction 5), the first two
cycles of the master clock are suppressed (see Figure 10). This feature allows the MT8924
to operate in 1544 kbit/s systems.
22DSTiST-BUS Serial Input. This pin accepts the serial PCM input stream at a maximum allowable
bit rate of 2048 kbit/s. In normal operation the first bit of the first channel is defined by the
rising edge of Cki following the falling edge of frame pulse F0i. When Extra bit operating
mode is selected, the first bit of the first channel defines the extra bit.
23A/µA/µ - Law Select Input. When A/µ is High, A-Law is selected, and when A/µ is Low ,µ-Law is
selected. The companding law selection must be done before initializing the de vice using the
RESET pin.
24V
Functional Description
Negative Power Supply Voltage. Nominally 0 Volts.
SS
channel N+1, frame M and subtracted during the
second half of channel N-1, frame M+1. After Linear-
The MT8924 is a device designed to provide
conferencing in a digital switching system in any
combination for up to all 32 channels of a 2048 kbit/s
ST-BUS stream (see Figure 3).
The information of channel N, frame M is first
converted to Linear PCM and then added to the
signal from other conferencees during the first half of
to-PCM conversion the subtraction result goes to the
parallel-to-serial converter, and appears at the
output on the N+1 channel, M+1 frame with respect
to the corresponding sending party information (see
Figure 4).
To a microprocessor the MT8924 appears as a
memory mapped peripheral device that can be
controlled by a set of six instructions. These
commands can be used to establish or cancel
Microcontroller
conferences between the PCM channels and also to
transmit control messages on specific operating
modes. The microprocessor can initiate and receive
status messages or check conference connections
If the sum of the channels involv ed in one conference
exceeds the full scale value of the accumulator, an
overflow condition is generated which can be
monitored specifically by reading the status of the
overflow register. If an overflow condition occurs,
then each channel in a conference can be
independently attenuated if desired.
PCM Byte
+ve input-ve input
B7 - B0B7 - B0
Alternatively, a conference in the overflow condition
can be detected using the OS signal in conjunction
with frame pulse F0i. OS will be low during the
second half of a general output channel slot time N,
if channel N belongs to a conference in overflow (see
Figure 11). This information can be used to control
input channel attenuation through software control.
F1F0B7B6B5B4B3B2B1B0Comments
00+ Full Scale11111111No Inversion
+ 0 Level10000000
- 0 Level00000000
- Full Scale01111111
01+ Full Scale10101010Even Bit Inversion
+ 0 Level11010101
- 0 Level01010101
- Full Scale00101010
10+ Full Scale11010101Odd Bit Inversion
+ 0 Level10101010
- 0 Level00101010
- Full Scale01010101
11+ Full Scale10000000Bit Inversion
+ 0 Level11111111
- 0 Level01111111
- Full Scale00000000
B7 (sign bit) is the MSB and B0 is the LSB
F1-F0 corresponds to the D5-D4 bits of the control byte of Operating Mode Instruction 5
Table 2 - PCM Byte Format
8-6
Page 5
Preliminary InformationMT8924
Noise Suppression
When noise suppression is enabled for a specific
input channel then the PCM bytes for this channel,
when below the selected threshold level, are
converted to PCM bytes corresponding to the
minimum PCM code level before being added to the
conference sum.
The four threshold levels available correspond to the
first, fifth, ninth and sixteenth step of the first
segment. These are 1/4096, 9/4096, 16/4096, and
32/4096 with respect to full scale A-Law, and 1/8159,
9/8159, 16/8159, and 32/8159 with respect to full
scale µ-Law (see Table 1).
PCM Format Selection
PCM digital code assignment is register
programmable and achieved through the use of
Instruction 5 (see Table 2). The available formats are
CCITT G.711 A-Law or µ-Law, with true-sign
Alternate Digit Inversion or true-sign/Inverted
Magnitude coding.
Output clock Cko provides a reference time base for
a digital time/space crosspoint switch. Normally this
signal is identical to the master clock input Cki.
When operating with the extra bit selection, through
Instruction 5, Cko is low for two clock periods, which
allows operation of the MT8924 with the 1.544 MHz
PCM frame format (see Figure 10).
Testing and Diagnostic Feature
For testing and diagnostic purposes, a status
instruction has been provided that indicates
conference location and attenuation level for each
channel requested. This data appears on the
databus upon status request.
Programmable Control
Instruction 1 : Conference Mode Connection
This function connects a PCM channel to a
conference. The control information from the
microprocessor consists of two data bytes and one
control byte. The first byte contains the conference
number (bits D0-D3) and the Start bit S (D4). When
S is High, the accumulator registers connected to a
conference are initialized. S set to High is only
required in Instruction 1 of the first channel
connected to a new conference, otherwise S is set
LOW to bring other channels into the conference.
The second byte contains the number of the
channel to be connected (D0-D4), and the Insert
Tone Enable bit IT (D5). When IT and TD are both
High all the channels belonging to that conference
are enabled using the insert tone function. The
third byte contains a four bit opcode (D0-D3) plus
information about the attenuation level and noise
suppression to be applied to the specific channel.
Transparent Mode
The MT8924 can operate in transparent mode. In
this case the PCM input (DSTi) is passed unmodified
through the MT8924 to the output (DSTo) with a
delay of one frame and one channel. This feature
allows attenuation of specific channels that are not
connected to a conference.
Tone Insertion
The MT8924 provides for tone insertion into PCM
output channels by using the two input pins TD and
TF. An externally generated square wave tone
applied to the TF input will generate a level
corresponding to 1/10 of the full scale accumulator
value when TD is High. Only channels connected in
a conference with the insertion tone bit (IT) active
will have the PCM coded tone at their output (see
Instruction 1).
Instruction 2 : Transparent Mode Connection
This function sets up a PCM channel for
transparent mode operation. The control
information from the microprocessor consists of
one data byte and one control byte.
The first byte contains the channel number, and
the second byte contains a four bit opcode (D0-D3)
and information about attenuation and noise
suppression levels to be applied to the specific
channel. PCM data on this channel is not added to
any conference, but is transferred to the PCM
output after a full frame pulse plus one channel
delay. It is not affected by the tone control pins (TF,
TD).
Instruction 3 : Disconnection
This function disconnects a PCM channel from a
conference. The control information from the
microprocessor consists of one data byte and one
8-7
Page 6
MT8924Preliminary Information
control byte. The data byte contains the number of
the channel to be disconnected. The second byte
contains the opcode (D0-D3). One frame pulse
must pass between disconnection and
reconnection of the same channel.
Instruction 4 : Overflow Status Monitoring
This function extracts overflow status information
on all existing conferences and transfers it to the
microprocessor data bus. This instruction consists
of two control bytes which are differentiated by the
C/D control signal. C/D set Low reads the status of
the first eight conferences, while C/D set High
reads the status of the remaining two conferences.
A conference is in overflow when the
corresponding status bit is high.
Instruction 5 : PCM Mode Select
This function is used to set the PCM format. The
control byte from the microprocessor consists of
one data byte. It contains the Extra Bit E (D6), the
Format Bits F1-F0 (D5, D4), and the opcode (D0D3). The E bit must be high when the PCM frame
contains an extra bit (i.e. 1.544 Mb/s). Normally E
is Low. Bits F1-F0 are used to select the PCM byte
format, according to Table 2. After RESET the
default values correspond to F1 at Low and F0 at
High if A-Law is selected, and F1 at High and F0 at
High if µ-Law is selected. All channels must be
disconnected when the PCM mode select
instruction is sent. They must remain disconnected
for at least two frame pulses after the instruction is
sent. It is recommended that this instruction be
used immediately following a system reset (see
RESET pin description).
Instruction 6 : Status Monitoring
This function is a read operation which consists of
a data byte, a control byte, and a status byte. It
extracts information for test and diagnostic
purposes and transfers it to the microprocessor
bus. The first byte contains the channel number,
while the second byte contains the opcode (D0D3). The third byte contains the status information
about the operating mode of the channel (D4-D7);
the attenuation level (D2-D3); and the noise
suppression level (D0-D1).
8-8
Page 7
Preliminary InformationMT8924
Instruction 1 : Channel Connection in Conference Mode
Control SignalsData BusComments
CSRDC/DWRD7D6D5D4D3D2D1D0
0100XXXSP3P2P1P0Conference Number
0100XXITC4C3C2C1C0PCM Channel Number and
Insertion Tone control
0110A1A0T1T00111Opcode, Attenuation, and
Noise Suppression control
S:Conference Start BitT1-T0:Channel Noise Suppression
P3-P0:Conference Number (1-10)T1/T0A-Lawµ-Law
IT:Insertion Tone Function Enable (IT=1)00no noise suppression
C4-C0:Channel Number (0-31)019/40969/8159
A1-A0:Channel Attenuation1016/409616/8159
Instruction 2 : Channel Connection in Transparent Mode
Control SignalsData BusComments
00 = -0dB1132/409632/8159
01 = -3dB
10 = -6dB
CSRDC/DWRD7D6D5D4D3D2D1D0
0100XXXC4C3C2C1C0PCM Channel Number
0110A1A0T1T00011Opcode and Attenuation
T1-T0: see noise suppression description given for Instruction 1
Instruction 3 : Channel Disconnection
Control SignalsData BusComments
CSRDC/DWRD7D6D5D4D3D2D1D0
0100XXXC4C3C2C1C0PCM Channel Number
0110XXXX1111Opcode
Instruction 4: Overflow Status Monitoring
Control SignalsData BusComments
CSRDC/DWRD7D6D5D4D3D2D1D0
0001CF
8CF7
CF6CF5CF4CF3CF2CF1Conferences 1 to 8
0011XXXXXXCF10CF9Conferences 9 to 10
CF10 - CF1 : Conference is in overflow when bit is HIGH
Note : as long as RD remains LOW, the overflow status of the conference selected by C/D can be monitored in real time
8-9
Page 8
MT8924Preliminary Information
Instruction 5 : PCM Operating Mode Selection
Control SignalsData BusComments
CSRDC/DWRD7D6D5D4D3D2D1D0
0110XEF1F00101see Table 1
E:Extra bit insertion (active when E=1)
F1 - F0:PCM byte format selection (see Table 1)
Instruction 6 : Status Monitoring
CSRDC/DWRD7D6D5D4D3D2D1D0
0100XXXC4C3C2C1C0
0110XXXX0110
00 = no bit inverted
01 = even bit (B0, B2, B4, B6) inverted
10 = odd bit (B1, B3, B5) inverted
11 = all bits (B0, B1, B2, B3, B4, B5, B6) inverted
0.4VPins 5, 21; IOL=8 mA
10µAPins 1-3, 6-13, 15-20, 22-23;
VIN=0 to V
DD
10µAPins 6-13; VIN=0 to VDD;
CS=V
DD
10mAPin 14; Cki=4.096 MHz
5pFfrequency=1MHz; TOP=0
15pF
10pF
to 70°C;
unused pins tied to VSS;
VDD=5V±5%
8-11
Page 10
MT8924Preliminary Information
AC Electrical Characteristics - Clocked Timing* (T
=0 to 70°C; VDD=5V5%)
OP
CharacteristicsSymMinTypMaxUnitsTest Conditions
1Clock periodt
2Clock low level widtht
3Clock high level widtht
4Clock rise timet
5Clock fall timet
6Sync. low setup timet
7Sync. low level hold timet
8Sync. high setup timet
9Sync. high widtht
10OS propagation delay from rising
CK
WLCK
WHCK
RCK
FCK
SLSY
HLSY
SHSY
WHSY
t
PDOS
230ns
100ns
100ns
25ns
25ns
50ns**
40ns
80ns
t
CK
ns
100nsCL=50pF
edge of Clock
11Cko propagation delay to Clock
t
PDEC
80nsCL=50pF
edges
12TD setup timet
13TD hold timet
14TD setup timet
15TD hold time
* All AC characteristics are valid 250µs after VDD and the clock have been applied. CL is the max. capacitive load and RL is the test pull up
resistor. With Extra Bit Insert operating mode these times are 80ns longer.
** With Extra Bit Insert operating mode this time becomes 3tCK.
STD
HTD
STF
t
HTD
80ns
40ns
80ns
40ns
Cki
F0i
TD
TF
Cko
OS
t
WHCK
t
CK
t
WLCK
t
SLSY
t
STD
t
STF
t
t
HLSY
PDEC
t
t
t
HTF
RCK
HTD
t
SHSY
t
PDEC
t
PDOS
t
FCK
t
WHSY
8-12
Figure 5 - Clock Timing
Page 11
Preliminary InformationMT8924
AC Electrical Characteristics - PCM Timing* (T
=0 to 70°C; VDD=5V5%)
OP
CharacteristicsSymMinTypMaxUnitsTest Conditions
1Input PCM setup timet
2Input PCM hold time
t
3Output PCM propagation delayt
SPCM
HPCM
PD
80ns
35ns
25125nsCL=150pF, RL=1KΩ
in 2.048MHz mode **
*All AC characteristics are valid 250µs after VDD and the clock have been applied. CL is the max. capacitive load and R
resistor.
**With Extra Bit Insert operating mode these times are 80ns longer.
Cki
F0i
DSTi
0
t
PD
12
t
t
SPCM
HPCM
MSB
is the test pull up
L
DSTo
MSB
Figure 6 - PCM Timing
AC Electrical Characteristics - RESET Timing* (T
=0 to 70°C; VDD=5V5%)
OP
CharacteristicsSymMinTypMaxUnitsTest Conditions
1RESET low setup timet
2RESET low hold timet
3RESET high setup timet
4RESET high level widtht
* All AC characteristics are valid 250µs after VDD and the clock have been applied. CL is the max. capacitive load and RL is the test pull up
resistor.
Cki
RESET
t
SLRES
SLRES
HLRES
SHRES
WHRES
t
100ns
50ns
90ns
t
CK
HLRES
t
SHRES
t
WHRES
ns
Figure 7 - Reset Timing
8-13
Page 12
MT8924Preliminary Information
AC Electrical Characteristics - Write Timing (T
CharacteristicsSymMinTypMaxUnitsTest Conditions
1Write Pulse low widtht
2Write Pulse high widtht
3Repetition Interval between active Write
Pulses
4Read high setup time to active Write
Pulse
5Read high hold time from active Write
Pulse
6Write Pulse rise timet
7Write Pulse fall timet
8CS low setup time to WR falling edget
9CS low hold time from WR falling edget
10CS high setup time to WR rising edget
11CS high hold time from WR rising edge t
12C/D setup time to Write Pulse endt
13C/D hold time from Write Pulse endt
14Input setup time to Write Pulse endt
15Input hold time from Bus Write Pulse
end
WLWR
WHWR
t
REPWR
t
SHRD
t
HHRD
RWR
FWR
SLCSWR
HLCSWR
SHCSWR
HHCSWR
SC/DWR
HCDWR
SDWR
t
HDWR
=0 to 70°C; VDD=5V5%)
OP
150ns
200ns
500ns
0ns
20ns
60ns
60ns
0nsActive case
0nsActive case
0ns
0ns
130ns
25ns
130ns
25ns
WR
RD
CS
C/D
DIN
t
SHRD
t
SLCSWR
t
HHRD
t
HCDWR
t
HDWR
t
WHWR
t
SHCSWR
t
HLCSWR
t
REPWR
t
FWR
t
WLWR
t
SCDWR
t
SDWR
Figure 8 - Write Timing Characteristics
t
RWR
t
HHCSWR
8-14
Page 13
Preliminary InformationMT8924
AC Electrical Characteristics - Read Timing (T
CharacteristicsSymMinTypMaxUnitsTest Conditions
1Read Pulse low widtht
2Read Pulse high widtht
3Repetition Interval between active Read
Pulses
4Write high setup time to active Read
Pulse
5Write high hold time from active Read
Pulse
6Read Pulse rise timet
7Read Pulse fall timet
8Low setup time to RD falling edget
9Low hold time from RD falling edget
10High setup time to RD falling edget
11High hold time from RD rising edget
12C/D setup time to RD Pulse startt
13Hold time from Read Pulse endt
14Propagation delay from falling edge of
Read Pulse
15Propagation delay from rising edge of
Read Pulse to high impedance state
WLRD
WHRD
t
REPRD
t
SHWR
t
HHWR
RRD
FRD
SLCSRD
HLCSRD
SHCSRD
HHCSRD
SCDRD
HCDRD
t
PDD
t
HZ
=0 to 70°C; VDD=5V5%)
OP
180ns
200ns
500ns
0ns
20ns
60ns
60ns
0nsActive case
0nsActive case
0nsActive case
0nsActive case
20ns
25ns
120nsRead; CL=200pF
80nsWrite; CL=200pF
RD
WR
CS
C/D
DOUT
t
SLCSRD
t
SHWR
t
SCDRD
t
HHWR
t
HCDRD
t
HZ
t
WHRD
t
SHCSRD
t
HLCSRD
t
REPRD
t
FRD
t
PDD
t
WLRD
Figure 9 - Read Timing Characteristics
t
RRD
t
HHCSRD
8-15
Page 14
MT8924Preliminary Information
Cki
Cko
F0i
Cki
OS
t
PDEC
Extra Bit
Bit 0 Channel 0
Bit 1 Channel 0
Figure 10 - CKo Timing with Extra Bit Insertion Mode
Channel N Channel N+1 Channel N-1
Figure 11 - OS Timing with Output PCM Channel belonging to a Conference in Overflow
8-16
Page 15
Pin 1
Package Outlines
E
A
A
1
16-Pin18-Pin20-Pin24-Pin28-Pin
DIM
MinMaxMinMaxMinMax
A0.093
A
B0.013
C0.009
D0.398
E0.291
e0.050 BSC
H0.394
L0.016
(2.35)
0.004
1
(0.10)
(0.33)
(0.231)
(10.1)
(7.40)
(1.27 BSC)
(10.00)
(0.40)
0.104
(2.65)
0.012
(0.30)
0.020
(0.51)
0.013
(0.318)
0.413
(10.5)
0.299
(7.40)
0.419
(10.65)
0.050
(1.27)
D
0.093
(2.35)
0.004
(0.10)
0.013
(0.33)
0.009
(0.231)
0.447
(11.35)
0.291
(7.40)
0.050 BSC
(1.27 BSC)
0.394
(10.00)
0.016
(0.40)
L
e
4 mils (lead coplanarity)
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) A & B Maximum dimensions include allowable mold flash
B
0.104
(2.65)
0.012
(0.30)
0.030
(0.51)
0.013
(0.318)
0.4625
(11.75)
0.299
(7.40)
0.419
(10.65)
0.050
(1.27)
0.093
(2.35)
0.004
(0.10)
0.013
(0.33)
0.009
(0.231)
0.496
(12.60)
0.291
(7.40)
0.050 BSC
(1.27 BSC)
0.394
(10.00)
0.016
(0.40)
0.104
(2.65)
0.012
(0.30)
0.020
(0.51)
0.013
(0.318)
0.512
(13.00)
0.299
(7.40)
0.419
(10.65)
0.050
(1.27)
Lead SOIC Package - S Suffix
C
H
L
MinMaxMinMax
0.093
(2.35)
0.004
(0.10)
0.013
(0.33)
0.009
(0.231)
0.5985
(15.2)
0.291
(7.40)
0.050 BSC
(1.27 BSC)
0.394
(10.00)
0.016
(0.40)
0.104
(2.65)
0.012
(0.30)
0.020
(0.51)
0.013
(0.318)
0.614
(15.6)
0.299
(7.40)
0.419
(10.65)
0.050
(1.27)
0.093
(2.35)
0.004
(0.10)
0.013
(0.33)
0.009
(0.231)
0.697
(17.7)
0.291
(7.40)
0.050 BSC
(1.27 BSC)
0.394
(10.00)
0.016
(0.40)
(0.318)
0.7125
(10.65)
0.104
(2.65)
0.012
(0.30)
0.020
(0.51)
0.013
(18.1)
0.299
(7.40)
0.419
0.050
(1.27)
NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters.
2. Converted inch dimensions are not necessarily exact.
General-7
Page 16
Package Outlines
E
1
D
32
n-2 n-1 n
1
E
L
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
A
b
D
1
e
2
b
A
2
Plastic Dual-In-Line Packages (PDIP) - E Suffix
8-Pin16-Pin18-Pin20-Pin
DIM
PlasticPlasticPlasticPlastic
MinMaxMinMaxMinMaxMinMax
A
A
2
b
b
2
C
D
D
1
E
E
1
e
e
A
L
e
B
e
C
NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.
Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no
liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of
patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or
service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever.
Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or
other intellectual property rights owned by Mitel.
This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or
contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this
publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific
piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or
data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in
any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Mitel’s
conditions of sale which are available on request.
M Mitel (design) and ST-BUS are registered trademarks of MITEL Corporation
Mitel Semiconductor is an ISO 9001 Registered Company
Copyright 1999 MITEL Corporation
All Rights Reserved
Printed in CANADA
TECHNICAL DOCUMENTATION - NOT FOR RESALE
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.