Datasheet MT8924AE Datasheet (MITEL)

Page 1
MT8924
PCM Conference Circuit (PCC)
Preliminary Information
Features
Supports up to 10 independent conferences for up to 32 PCM Voice Channels
ST-BUS compatible 2.048 Mb/s PCM Serial Interface (also supports 1.536 Mb/s and 1.544 Mb/s data rates)
Parallel microprocessor port for device control
Programmable noise suppression
External Tone Input
Pin selectable A/µ-Law format
Low power CMOS technology
Available in 24 Pin PDIP and SOIC packages
Applications
Digital PBX / KTS
Conference bridges
Digital C.O. switches
ISSUE 1 April 1994
Ordering Information
MT8924AE 24 Pin Plastic DIP (600 mil) MT8924AS 24 Pin SOIC
0°C to +70°C
Description
The MT8924 is designed to provide conference call capability in digital switching systems. It allows up to 10 independent conferences to be set for up to 32 PCM voice channels.
A/µ-Law companded data from the PCM input port is converted to linear format, processed by a dedicated arithmetic unit, re-converted to companded format and then sent to the PCM output port.The PCM output signal contains all the information of each channel connected in conference except its own.
Programmable attenuation and noise suppression are provided for channels connected in conference or transparent mode. Additionally, an input for an external tone is featured that can be used as a signal to indicate to connected parties that they are on a conference call.
DSTi
OS
Overflow
Attenuation/Noise Suppression
Channel RAM
µ/A-Law
to
Linear
Serial-to-Parallel
Conversion
PCM Mode
Control
RESET WRRD
µ
A/
Timebase
F0i Cko D0-D7TDTF
Cki
and
Adder
PCM Tone Generator
MUX
Figure 1 - Functional Block Diagram
Linear
to
µ/A-Law
Parallel-to-Serial
Conversion
Control
CS
DSTo
D
C/
8-3
Page 2
MT8924 Preliminary Information
TD
TF
RESET
OS
DSTo
D7 D6
D5
D4 D3 D2 D1
10 11 12
1 2
3 4 5
6 7 8 9
24 23 22 21 20 19 18 17 16 15 14 13
VSS A/
µ
DSTi Cko Cki F0i WR RD CS C/
D VDD D0
Figure 2 - Pin Connections
Pin Description
Pin # Name Description
1TDTone Duration (Input). When TD is High, a PCM-coded tone is sent out to all channels of
the enabled conferences instead of PCM data. TD is latched by frame pulse F0i so that all channels have the same tone during the same frame number. When TD is Low, normal operation is enabled.
2TFTone Frequency (Input). This input is connected to an external squarewave generator. TF
is strobed by frame pulse F0i so that all channels have the same tone frequency during the same number of frames. The PCM-coded tone level corresponds to 1/10th of the full scale value, and is activated when TD is High.
3 RESET Master RESET (Input). This input is used for system reset after power up, or when the
companding law format has been changed. The RESET pin is strobed by the rising edge of clock Cki. Complete circuit initialization takes two frame periods. Resetting the device disables the output drivers of the microprocessor interface and DSTo.
4 OS Overflow Signalling (Output). When OS is Low , a conference is in the overflo w condition.
This signal is delayed by half of a timeslot relative to the beginning of the output channel of the conference in overflow (see Figure 9).
5 DST
ST-BUS Serial Output. This pin is the output for the PCM signal. It is enabled upon
o
channel selection, otherwise it is placed in a high impedance state. Maximum bit rate is
2.048 Mb/s.
6-13 D7 to D0 Data Bus I/O Port. These are bidirectional data pins over which data and instructions are
transferred to and from the microprocessor (where D0 is the least significant bit). The bus is in a high impedance state when RESET is Low and/or CS is High.
14 V
DD
Positive Supply Voltage. Nominally 5 volts.
15 C/D Contr ol/Data Select (Input). The signal on this input defines whether the inf ormation on the
data bus should be interpreted as opcode or data. During a write operation a Low signal defines the bus content as data, while a High signal defines it as opcode. During a read operation this input differentiates overflow status between the first eight channels for C/D being LOW, and the last two channels f or C/D being HIGH (see Instruction 4). This input also allows status monitoring (see Instruction 6) during a read operation.
16 CS Chip Select (Input). This active low input selects the device for microprocessor read/write
operations. When CS is Low, data and instructions can be transferred to or from the microprocessor, and when CS is High, the data bus is in a high impedance state.
17 RD Read (Input). This active low input is for the read signal on the microprocessor interface.
The data bus is updated on the falling edge of RD.
18 WR Write Input. This active low input is for the write signal on the microprocessor interface. The
data bus is strobed on the rising edge of WR.
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Preliminary Information MT8924
Pin Description (continued)
Pin # Name Description
19 F0i Frame Pulse (Input). This is an 8 kHz active low input used for frame synchronization of the
PCM bit stream. The first falling edge of Cki following the falling edge of frame pulse F0i determines the start of a new frame and must correspond to the first bit of the first channel. When PCM frames of 1544 kbit/s are used, the rising edge of F0i must correspond to the Extra (193rd) bit.
20 Cki Clock (Input). This signal is the timing reference used for all internal operations. The PCM
bit cell boundaries lie on the alternate falling edges of this clock. The maximum allowable clock frequency is 4096 kHz.
21 Cko Clock (Output). This pin provides the master clock for a digital crosspoint switch (e.g.,
MT898x series, or the MT9080, MT9085 combination). Normally the signal on this pin is identical to Cki. When Extra bit operating mode is selected (see Instruction 5), the first two cycles of the master clock are suppressed (see Figure 10). This feature allows the MT8924 to operate in 1544 kbit/s systems.
22 DSTiST-BUS Serial Input. This pin accepts the serial PCM input stream at a maximum allowable
bit rate of 2048 kbit/s. In normal operation the first bit of the first channel is defined by the rising edge of Cki following the falling edge of frame pulse F0i. When Extra bit operating mode is selected, the first bit of the first channel defines the extra bit.
23 A/µ A/µ - Law Select Input. When A/µ is High, A-Law is selected, and when A/µ is Low ,µ-Law is
selected. The companding law selection must be done before initializing the de vice using the RESET pin.
24 V
Functional Description
Negative Power Supply Voltage. Nominally 0 Volts.
SS
channel N+1, frame M and subtracted during the second half of channel N-1, frame M+1. After Linear-
The MT8924 is a device designed to provide conferencing in a digital switching system in any combination for up to all 32 channels of a 2048 kbit/s ST-BUS stream (see Figure 3).
The information of channel N, frame M is first converted to Linear PCM and then added to the signal from other conferencees during the first half of
to-PCM conversion the subtraction result goes to the parallel-to-serial converter, and appears at the output on the N+1 channel, M+1 frame with respect to the corresponding sending party information (see Figure 4).
To a microprocessor the MT8924 appears as a memory mapped peripheral device that can be controlled by a set of six instructions. These commands can be used to establish or cancel
Microcontroller
conferences between the PCM channels and also to transmit control messages on specific operating modes. The microprocessor can initiate and receive status messages or check conference connections
STi0
. . . .
STix-1
STix
MT8980/81/82 Digital Switch
MT8924
PCM Conference
Circuit (PCC)
STo0
. . . .
STox-1
STox
that are currently in operation.
Input Information
B
A
DSTi
Input Channels Frame M
C
MT8924
N+2N+1N
Output Information
B+C A+C A+B
N+2 N+3N+1
Output Channels Frame M+1
DSTo
Figure 3 -Typical Conference Connection
Figure 4 - Input/Output Channel Relationship
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MT8924 Preliminary Information
Noise
Threshold
A-Law 1/4096 1000 0000 0000 0000
9/4096 1000 0100 0000 0100 16/4096 1000 1000 0000 1000 32/4096 1000 1111 0000 1111
µ-Law 1/8159 1111 1111 0111 1111
9/8159 1111 1011 0111 1011 16/8159 1111 0111 0111 0111 32/8159 1111 0000 0111 0000
Table 1 - PCM Noise Suppression Threshold Levels
Overflow Detection / Input Channel Attenuation
If the sum of the channels involv ed in one conference exceeds the full scale value of the accumulator, an overflow condition is generated which can be monitored specifically by reading the status of the overflow register. If an overflow condition occurs, then each channel in a conference can be independently attenuated if desired.
PCM Byte
+ve input -ve input
B7 - B0 B7 - B0
Alternatively, a conference in the overflow condition can be detected using the OS signal in conjunction with frame pulse F0i. OS will be low during the second half of a general output channel slot time N, if channel N belongs to a conference in overflow (see Figure 11). This information can be used to control input channel attenuation through software control.
F1 F0 B7 B6 B5 B4 B3 B2 B1 B0 Comments
0 0 + Full Scale 11111111No Inversion
+ 0 Level 10000000
- 0 Level 00000000
- Full Scale 01111111
0 1 + Full Scale 10101010Even Bit Inversion
+ 0 Level 11010101
- 0 Level 01010101
- Full Scale 00101010
1 0 + Full Scale 11010101Odd Bit Inversion
+ 0 Level 10101010
- 0 Level 00101010
- Full Scale 01010101
1 1 + Full Scale 10000000Bit Inversion
+ 0 Level 11111111
- 0 Level 01111111
- Full Scale 00000000
B7 (sign bit) is the MSB and B0 is the LSB F1-F0 corresponds to the D5-D4 bits of the control byte of Operating Mode Instruction 5
Table 2 - PCM Byte Format
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Preliminary Information MT8924
Noise Suppression
When noise suppression is enabled for a specific input channel then the PCM bytes for this channel, when below the selected threshold level, are converted to PCM bytes corresponding to the minimum PCM code level before being added to the conference sum.
The four threshold levels available correspond to the first, fifth, ninth and sixteenth step of the first segment. These are 1/4096, 9/4096, 16/4096, and 32/4096 with respect to full scale A-Law, and 1/8159, 9/8159, 16/8159, and 32/8159 with respect to full scale µ-Law (see Table 1).
PCM Format Selection
PCM digital code assignment is register programmable and achieved through the use of Instruction 5 (see Table 2). The available formats are CCITT G.711 A-Law or µ-Law, with true-sign Alternate Digit Inversion or true-sign/Inverted Magnitude coding.
Output clock Cko provides a reference time base for a digital time/space crosspoint switch. Normally this signal is identical to the master clock input Cki. When operating with the extra bit selection, through Instruction 5, Cko is low for two clock periods, which allows operation of the MT8924 with the 1.544 MHz PCM frame format (see Figure 10).
Testing and Diagnostic Feature
For testing and diagnostic purposes, a status instruction has been provided that indicates conference location and attenuation level for each channel requested. This data appears on the databus upon status request.
Programmable Control
Instruction 1 : Conference Mode Connection
This function connects a PCM channel to a conference. The control information from the microprocessor consists of two data bytes and one control byte. The first byte contains the conference number (bits D0-D3) and the Start bit S (D4). When S is High, the accumulator registers connected to a conference are initialized. S set to High is only required in Instruction 1 of the first channel connected to a new conference, otherwise S is set LOW to bring other channels into the conference. The second byte contains the number of the channel to be connected (D0-D4), and the Insert Tone Enable bit IT (D5). When IT and TD are both High all the channels belonging to that conference are enabled using the insert tone function. The third byte contains a four bit opcode (D0-D3) plus information about the attenuation level and noise suppression to be applied to the specific channel.
Transparent Mode
The MT8924 can operate in transparent mode. In this case the PCM input (DSTi) is passed unmodified through the MT8924 to the output (DSTo) with a delay of one frame and one channel. This feature allows attenuation of specific channels that are not connected to a conference.
Tone Insertion
The MT8924 provides for tone insertion into PCM output channels by using the two input pins TD and TF. An externally generated square wave tone applied to the TF input will generate a level corresponding to 1/10 of the full scale accumulator value when TD is High. Only channels connected in a conference with the insertion tone bit (IT) active will have the PCM coded tone at their output (see Instruction 1).
Instruction 2 : Transparent Mode Connection
This function sets up a PCM channel for transparent mode operation. The control information from the microprocessor consists of one data byte and one control byte.
The first byte contains the channel number, and the second byte contains a four bit opcode (D0-D3) and information about attenuation and noise suppression levels to be applied to the specific channel. PCM data on this channel is not added to any conference, but is transferred to the PCM output after a full frame pulse plus one channel delay. It is not affected by the tone control pins (TF, TD).
Instruction 3 : Disconnection
This function disconnects a PCM channel from a conference. The control information from the microprocessor consists of one data byte and one
8-7
Page 6
MT8924 Preliminary Information
control byte. The data byte contains the number of the channel to be disconnected. The second byte
contains the opcode (D0-D3). One frame pulse must pass between disconnection and reconnection of the same channel.
Instruction 4 : Overflow Status Monitoring
This function extracts overflow status information on all existing conferences and transfers it to the microprocessor data bus. This instruction consists of two control bytes which are differentiated by the C/D control signal. C/D set Low reads the status of the first eight conferences, while C/D set High reads the status of the remaining two conferences. A conference is in overflow when the corresponding status bit is high.
Instruction 5 : PCM Mode Select
This function is used to set the PCM format. The control byte from the microprocessor consists of one data byte. It contains the Extra Bit E (D6), the Format Bits F1-F0 (D5, D4), and the opcode (D0­D3). The E bit must be high when the PCM frame contains an extra bit (i.e. 1.544 Mb/s). Normally E is Low. Bits F1-F0 are used to select the PCM byte format, according to Table 2. After RESET the default values correspond to F1 at Low and F0 at High if A-Law is selected, and F1 at High and F0 at High if µ-Law is selected. All channels must be disconnected when the PCM mode select instruction is sent. They must remain disconnected for at least two frame pulses after the instruction is sent. It is recommended that this instruction be used immediately following a system reset (see RESET pin description).
Instruction 6 : Status Monitoring
This function is a read operation which consists of a data byte, a control byte, and a status byte. It extracts information for test and diagnostic purposes and transfers it to the microprocessor bus. The first byte contains the channel number, while the second byte contains the opcode (D0­D3). The third byte contains the status information about the operating mode of the channel (D4-D7); the attenuation level (D2-D3); and the noise suppression level (D0-D1).
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Preliminary Information MT8924
Instruction 1 : Channel Connection in Conference Mode
Control Signals Data Bus Comments
CS RD C/D WR D7 D6 D5 D4 D3 D2 D1 D0
0100XXXSP3P2P1P0Conference Number 0100XXITC4C3C2C1C0PCM Channel Number and
Insertion Tone control
0110A1A0T1T00111Opcode, Attenuation, and
Noise Suppression control
S: Conference Start Bit T1-T0: Channel Noise Suppression P3-P0: Conference Number (1-10) T1/T0 A-Law µ-Law IT: Insertion Tone Function Enable (IT=1) 00 no noise suppression C4-C0: Channel Number (0-31) 01 9/4096 9/8159 A1-A0: Channel Attenuation 10 16/4096 16/8159
Instruction 2 : Channel Connection in Transparent Mode
Control Signals Data Bus Comments
00 = -0dB 11 32/4096 32/8159 01 = -3dB 10 = -6dB
CS RD C/D WR D7 D6 D5 D4 D3 D2 D1 D0
0100XXXC4C3C2C1C0PCM Channel Number 0110A1A0T1T00011Opcode and Attenuation
T1-T0: see noise suppression description given for Instruction 1
Instruction 3 : Channel Disconnection
Control Signals Data Bus Comments
CS RD C/D WR D7 D6 D5 D4 D3 D2 D1 D0
0100XXXC4C3C2C1C0PCM Channel Number 0110XXXX1111Opcode
Instruction 4: Overflow Status Monitoring
Control Signals Data Bus Comments
CS RD C/D WR D7 D6 D5 D4 D3 D2 D1 D0
0001CF
8CF7
CF6CF5CF4CF3CF2CF1Conferences 1 to 8
0011XXXXXXCF10CF9Conferences 9 to 10
CF10 - CF1 : Conference is in overflow when bit is HIGH Note : as long as RD remains LOW, the overflow status of the conference selected by C/D can be monitored in real time
8-9
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MT8924 Preliminary Information
Instruction 5 : PCM Operating Mode Selection
Control Signals Data Bus Comments
CS RD C/D WR D7 D6 D5 D4 D3 D2 D1 D0
0110XEF1F00101see Table 1
E: Extra bit insertion (active when E=1) F1 - F0: PCM byte format selection (see Table 1)
Instruction 6 : Status Monitoring
CS RD C/D WR D7 D6 D5 D4 D3 D2 D1 D0
0100XXXC4C3C2C1C0 0110XXXX0110
00 = no bit inverted 01 = even bit (B0, B2, B4, B6) inverted 10 = odd bit (B1, B3, B5) inverted 11 = all bits (B0, B1, B2, B3, B4, B5, B6) inverted
Control Signals Data Bus Comments
0011P3P2P1P0A1A0T1T0
P3 - P0: channel mode operation information A1 - A0: see channel attenuation description
Note: Instruction 6 enables the data bus to read the status until reset by C/D=0, WR=1, and CS=0
0000 = no connection for Instruction 1 1111 = transparent mode T1 - T0: see noise suppression description 1010 - 0001 = conference mode for Instruction 1 P3 - P0 provides conference number
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Preliminary Information MT8924
Absolute Maximum Ratings*
Parameter Symbol Min Max Units
1 Supply Voltage VDD - V 2 Voltage on any I/O pin V 3 Current on any I/O pin I 4 Storage Temperature T 5 Power Dissipation (plastic package) P
I/O
I/O
ST
D
SS
- 0.3 7 V
VSS - 0.3 VDD + 0.3 V
± 10 mA
- 65 + 150 °C 500 mW
* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed.
Recommended Operating Conditions
Characteristics Sym Min Typ* Max Units Test Conditions
1 Supply Voltage V 2 Ambient Operating Temp. Range T 3 Input Voltage High V
4 Input Voltage Low V
DD
OP
IH
IL
* Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
DC Characteristics: Clocked operation (T
4.75 5 5.25 V 0 +70 °C
2.4 V
V
SS
=0 to 70°C; VDD=5V5%)
OP
0.8 V
DD
V for 400mv noise
margin
Characteristics Sym Min Typ Max Units Test Conditions
1 Input Low Level 2 Input High Level 3 Output Low Level V 4 Output High Level V 5 Output Low Level V 6 Input Leakage Current I
7 Data Bus Leakage Current I
8 Supply Current I
All DC characterisitics are valid 250µs after V
V
IL
V
OH
OL
IL
OL
DD
and C4i have been applied.
DD
2.0 V Pins 1-3, 6-13, 15-20, 22-23
IH
OL
2.4 V Pins 4, 6-13; IOL=4 mA
AC Electrical Characteristics - Capacitances
Characteristics Sym Min Typ Max Units Test Conditions
1 Input Capacitance C 2 I/O Capacitance (Bidirectional) C 3 Output Capacitance C
I
I/O
O
0.8 V Pins 1-3, 6-13, 15-20, 22-23
0.4 V Pins 4, 6-13; IOL=4 mA
0.4 V Pins 5, 21; IOL=8 mA 10 µA Pins 1-3, 6-13, 15-20, 22-23;
VIN=0 to V
DD
10 µA Pins 6-13; VIN=0 to VDD;
CS=V
DD
10 mA Pin 14; Cki=4.096 MHz
5 pF frequency=1MHz; TOP=0 15 pF 10 pF
to 70°C; unused pins tied to VSS; VDD=5V±5%
8-11
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MT8924 Preliminary Information
AC Electrical Characteristics - Clocked Timing* (T
=0 to 70°C; VDD=5V5%)
OP
Characteristics Sym Min Typ Max Units Test Conditions
1 Clock period t 2 Clock low level width t 3 Clock high level width t 4 Clock rise time t 5 Clock fall time t 6 Sync. low setup time t 7 Sync. low level hold time t 8 Sync. high setup time t 9 Sync. high width t
10 OS propagation delay from rising
CK WLCK WHCK
RCK
FCK SLSY HLSY
SHSY
WHSY
t
PDOS
230 ns 100 ns 100 ns
25 ns
25 ns 50 ns ** 40 ns 80 ns
t
CK
ns
100 ns CL=50pF
edge of Clock
11 Cko propagation delay to Clock
t
PDEC
80 ns CL=50pF
edges 12 TD setup time t 13 TD hold time t 14 TD setup time t 15 TD hold time
* All AC characteristics are valid 250µs after VDD and the clock have been applied. CL is the max. capacitive load and RL is the test pull up
resistor. With Extra Bit Insert operating mode these times are 80ns longer.
** With Extra Bit Insert operating mode this time becomes 3tCK.
STD HTD
STF
t
HTD
80 ns 40 ns 80 ns 40 ns
Cki
F0i
TD
TF
Cko
OS
t
WHCK
t
CK
t
WLCK
t
SLSY
t
STD
t
STF
t
t
HLSY
PDEC
t
t
t
HTF
RCK
HTD
t
SHSY
t
PDEC
t
PDOS
t
FCK
t
WHSY
8-12
Figure 5 - Clock Timing
Page 11
Preliminary Information MT8924
AC Electrical Characteristics - PCM Timing* (T
=0 to 70°C; VDD=5V5%)
OP
Characteristics Sym Min Typ Max Units Test Conditions
1 Input PCM setup time t 2 Input PCM hold time
t
3 Output PCM propagation delay t
SPCM HPCM
PD
80 ns 35 ns 25 125 ns CL=150pF, RL=1K
in 2.048MHz mode **
*All AC characteristics are valid 250µs after VDD and the clock have been applied. CL is the max. capacitive load and R
resistor.
**With Extra Bit Insert operating mode these times are 80ns longer.
Cki
F0i
DSTi
0
t
PD
12
t
t
SPCM
HPCM
MSB
is the test pull up
L
DSTo
MSB
Figure 6 - PCM Timing
AC Electrical Characteristics - RESET Timing* (T
=0 to 70°C; VDD=5V5%)
OP
Characteristics Sym Min Typ Max Units Test Conditions
1 RESET low setup time t 2 RESET low hold time t 3 RESET high setup time t 4 RESET high level width t
* All AC characteristics are valid 250µs after VDD and the clock have been applied. CL is the max. capacitive load and RL is the test pull up
resistor.
Cki
RESET
t
SLRES
SLRES
HLRES
SHRES
WHRES
t
100 ns
50 ns 90 ns
t
CK
HLRES
t
SHRES
t
WHRES
ns
Figure 7 - Reset Timing
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MT8924 Preliminary Information
AC Electrical Characteristics - Write Timing (T
Characteristics Sym Min Typ Max Units Test Conditions
1 Write Pulse low width t 2 Write Pulse high width t 3 Repetition Interval between active Write
Pulses
4 Read high setup time to active Write
Pulse
5 Read high hold time from active Write
Pulse 6 Write Pulse rise time t 7 Write Pulse fall time t 8 CS low setup time to WR falling edge t 9 CS low hold time from WR falling edge t
10 CS high setup time to WR rising edge t 11 CS high hold time from WR rising edge t 12 C/D setup time to Write Pulse end t 13 C/D hold time from Write Pulse end t 14 Input setup time to Write Pulse end t 15 Input hold time from Bus Write Pulse
end
WLWR
WHWR
t
REPWR
t
SHRD
t
HHRD
RWR
FWR SLCSWR HLCSWR SHCSWR HHCSWR
SC/DWR HCDWR
SDWR
t
HDWR
=0 to 70°C; VDD=5V5%)
OP
150 ns 200 ns 500 ns
0ns
20 ns
60 ns 60 ns
0 ns Active case 0 ns Active case 0ns 0ns
130 ns
25 ns
130 ns
25 ns
WR
RD
CS
C/D
DIN
t
SHRD
t
SLCSWR
t
HHRD
t
HCDWR
t
HDWR
t
WHWR
t
SHCSWR
t
HLCSWR
t
REPWR
t
FWR
t
WLWR
t
SCDWR
t
SDWR
Figure 8 - Write Timing Characteristics
t
RWR
t
HHCSWR
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Preliminary Information MT8924
AC Electrical Characteristics - Read Timing (T
Characteristics Sym Min Typ Max Units Test Conditions
1 Read Pulse low width t 2 Read Pulse high width t 3 Repetition Interval between active Read
Pulses
4 Write high setup time to active Read
Pulse
5 Write high hold time from active Read
Pulse 6 Read Pulse rise time t 7 Read Pulse fall time t 8 Low setup time to RD falling edge t 9 Low hold time from RD falling edge t
10 High setup time to RD falling edge t 11 High hold time from RD rising edge t 12 C/D setup time to RD Pulse start t 13 Hold time from Read Pulse end t 14 Propagation delay from falling edge of
Read Pulse
15 Propagation delay from rising edge of
Read Pulse to high impedance state
WLRD
WHRD
t
REPRD
t
SHWR
t
HHWR
RRD
FRD
SLCSRD HLCSRD SHCSRD HHCSRD
SCDRD HCDRD
t
PDD
t
HZ
=0 to 70°C; VDD=5V5%)
OP
180 ns 200 ns 500 ns
0ns
20 ns
60 ns
60 ns 0 ns Active case 0 ns Active case 0 ns Active case 0 ns Active case
20 ns 25 ns
120 ns Read; CL=200pF
80 ns Write; CL=200pF
RD
WR
CS
C/D
DOUT
t
SLCSRD
t
SHWR
t
SCDRD
t
HHWR
t
HCDRD
t
HZ
t
WHRD
t
SHCSRD
t
HLCSRD
t
REPRD
t
FRD
t
PDD
t
WLRD
Figure 9 - Read Timing Characteristics
t
RRD
t
HHCSRD
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MT8924 Preliminary Information
Cki
Cko
F0i
Cki
OS
t
PDEC
Extra Bit
Bit 0 Channel 0
Bit 1 Channel 0
Figure 10 - CKo Timing with Extra Bit Insertion Mode
Channel N Channel N+1 Channel N-1
Figure 11 - OS Timing with Output PCM Channel belonging to a Conference in Overflow
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Page 15
Pin 1
Package Outlines
E
A
A
1
16-Pin 18-Pin 20-Pin 24-Pin 28-Pin
DIM
Min Max Min Max Min Max
A 0.093
A
B 0.013
C 0.009
D 0.398
E 0.291
e 0.050 BSC
H 0.394
L 0.016
(2.35)
0.004
1
(0.10)
(0.33)
(0.231)
(10.1)
(7.40)
(1.27 BSC)
(10.00)
(0.40)
0.104 (2.65)
0.012 (0.30)
0.020 (0.51)
0.013
(0.318)
0.413 (10.5)
0.299 (7.40)
0.419
(10.65)
0.050 (1.27)
D
0.093 (2.35)
0.004 (0.10)
0.013 (0.33)
0.009
(0.231)
0.447
(11.35)
0.291 (7.40)
0.050 BSC (1.27 BSC)
0.394
(10.00)
0.016 (0.40)
L
e
4 mils (lead coplanarity)
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) A & B Maximum dimensions include allowable mold flash
B
0.104 (2.65)
0.012 (0.30)
0.030 (0.51)
0.013
(0.318)
0.4625 (11.75)
0.299 (7.40)
0.419
(10.65)
0.050 (1.27)
0.093 (2.35)
0.004 (0.10)
0.013 (0.33)
0.009
(0.231)
0.496
(12.60)
0.291 (7.40)
0.050 BSC
(1.27 BSC)
0.394
(10.00)
0.016 (0.40)
0.104 (2.65)
0.012 (0.30)
0.020 (0.51)
0.013
(0.318)
0.512
(13.00)
0.299 (7.40)
0.419
(10.65)
0.050 (1.27)
Lead SOIC Package - S Suffix
C
H
L
Min Max Min Max
0.093 (2.35)
0.004 (0.10)
0.013 (0.33)
0.009
(0.231)
0.5985 (15.2)
0.291 (7.40)
0.050 BSC
(1.27 BSC)
0.394
(10.00)
0.016 (0.40)
0.104 (2.65)
0.012 (0.30)
0.020 (0.51)
0.013
(0.318)
0.614 (15.6)
0.299 (7.40)
0.419
(10.65)
0.050 (1.27)
0.093 (2.35)
0.004 (0.10)
0.013 (0.33)
0.009
(0.231)
0.697 (17.7)
0.291 (7.40)
0.050 BSC (1.27 BSC)
0.394
(10.00)
0.016 (0.40)
(0.318)
0.7125
(10.65)
0.104 (2.65)
0.012 (0.30)
0.020 (0.51)
0.013
(18.1)
0.299 (7.40)
0.419
0.050 (1.27)
NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters.
2. Converted inch dimensions are not necessarily exact.
General-7
Page 16
Package Outlines
E
1
D
32
n-2 n-1 n
1
E
L
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
A
b
D
1
e
2
b
A
2
Plastic Dual-In-Line Packages (PDIP) - E Suffix
8-Pin 16-Pin 18-Pin 20-Pin
DIM
Plastic Plastic Plastic Plastic
Min Max Min Max Min Max Min Max
A
A
2
b
b
2
C D
D
1
E
E
1
e
e
A
L
e
B
e
C
NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.
0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95)
0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)
0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77)
0.008
(0.203)
0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9)
0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)
0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26)
0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11)
0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)
0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62)
0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81)
0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52)
0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33)
0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356)
0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92)
C
e
A
e
B
e
C
General-8
Page 17
E
1
L
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
Package Outlines
32
1
E
n-2 n-1 n
D
A
b
D
1
e
2
b
A
2
C
e
A
e
B
Plastic Dual-In-Line Packages (PDIP) - E Suffix
α
DIM
A
A
2
b
b
2
C D
D
1
E E
E
1
E
1
e
e
A
e
A
e
B
L
α
22-Pin 24-Pin 28-Pin 40-Pin
Plastic Plastic Plastic Plastic
Min Max Min Max Min Max Min Max
0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35)
0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95)
0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)
0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77)
0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381)
1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2)
0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)
0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02)
0.290 (7.37) .330 (8.38)
0.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73)
0.246 (6.25) 0.254 (6.45)
0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)
0.400 BSC (10.16) 0.600 BSC (15.24) 0.600 BSC (15.24) 0.600 BSC (15.24)
0.300 BSC (7.62)
0.430 (10.92)
0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 15° 15° 15° 15°
Shaded areas for 300 Mil Body Width 24 PDIP only
Page 18
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