Datasheet MT88E45AS Datasheet (MITEL)

MT88E45

4-Wire Calling Number Identification Circuit 2

Advance Information

Features

• Compatible with:

• Bellcore GR-30-CORE, SR-TSV-002476,
ANSI/TIA/EIA-716, draft TIA/EIA-777;

• ETSI ETS 300 778-1 (FSK only variant) & -2;

• BT (British Telecom) SIN227 & SIN242

• Bellcore ‘CPE Alerting Signal’ (CAS), ETSI
‘Dual Tone Alerting Signal’ (DT-AS), BT Idle
State and Loop State ‘Tone Alert Signal’
detection

• 1200 baud Bell 202 and CCITT V.23 FSK
demodulation

• Separate differential input amplifiers with
adjustable gain for Tip/Ring and telephone
hybrid or speech IC connections

• Selectable 3-wire FSK data interface (bit
stream or 1 byte buffer)

• Facility to monitor the stop bit for framing error
check

• FSK Carrier detect status output

• 3 to 5V +/- 10% supply voltage

• Uses 3.579545MHz crystal or ceramic
resonator

• Low power CMOS with power down

Applications

• Bellcore CID (Calling Identity Delivery) and
CIDCW (Calling Identity Delivery on Call
Waiting) telephones and adjuncts

• ETSI, BT CLIP (Calling Line Identity
Presentation) and CLIP with Call Waiting
telephones and adjuncts

• Fax and answering machines

• Computer Telephony Integration (CTI) systems

(4-Wire CNIC2)

DS5143 ISSUE 2 March 1999

Ordering Information

MT88E45AS 20 Pin SOIC

-40°C to 85°C

Description

The MT88E45 is a low power CMOS integrated
circuit suitable for receiving the physical layer signals
used in North American (Bellcore) Calling Identity
Delivery on Call Waiting (CIDCW) and Calling
Identity Delivery (CID) services. It is also suitable for
ETSI and BT Calling Line Identity Presentation
(CLIP) and CLIP with Call Waiting services.

The MT88E45 contains a 1200 baud Bell 202/CCITT
V.23 FSK demodulator and a CAS/DT-AS detector.
Two input op-amps allow the MT88E45 to be
connected to both Tip/Ring and the telephone hybrid
or speech IC receive pair for optimal CIDCW
telephone architectural implementation. FSK
demodulation is always on Tip/Ring, while CAS
detection can be on Tip/Ring or Hybrid Receive. Tip/
Ring CAS detection is required for Bellcore’s
proposed Multiple Extension Interworking (MEI) and
BT’s on-hook CLIP. A selectable FSK data interface
allows the data to be processed as a bit stream or
extracted from a 1 byte on chip buffer. Power
management has been incorporated to power down
the FSK or CAS section when not required. Full chip
power down is also available. The MT88E45 is
suitable for applications using a fixed power source
(with a +/-10% variation) between 3 and 5V.

IN1+
IN1-

GS1
IN2+
IN2-

GS2

V

REF

FSKen+Tip/Ring CASen

+

-

PWDN

PWDN

+

-

Bias
Generator

Oscillator

OSC1 OSC2

Hybrid CASen

MODE

PWDN

Anti-Alias
Filter

PWDN

FSKen

Control Bit
Decode

CB1

CB0

PWDN

CASen

CB2

FSK
Bandpass

FSKen
CASen

2130Hz
Bandpass

2750Hz
Bandpass

CASen

Figure 1 - Functional Block Diagram

FSK
Demodulator

Carrier
Detector

Tone
Detection
Algorithm

MODE

Data Timing
Recovery

DR

STD

Guard
Time

Mux

DATA
DCLK

CD

DR/STD

ST/GT

EST

Vdd
Vss

1

MT88E45 Advance Information

V

REF

IN1+

IN1-

GS1

Vss
OSC1
OSC2

CB0

DCLK
DATA

1
2
3
4
5
6
7
8
9
10

MT88E45

20
19
18
17
16
15
14
13
12
11

Figure 2 - Pin Connections

Pin Description

Pin # Name Description

1V

2 IN1+ Tip/Ring Op-amp Non-inverting (Input).

Voltage Reference (Output). Nominally Vdd/2. It is used to bias the Tip/Ring and Hybrid input

REF

op-amps.

IN2+
IN2­GS2
CB2

CB1
Vdd

CD
ST/GT

EST
DR/STD

3 IN1- Tip/Ring Op-amp Inverting (Input).
4 GS1 Tip/Ring Gain Select (Output). This is the output of the Tip/Ring connection op-amp. The op-

amp should be used to connect the MT88E45 to Tip and Ring. The Tip/Ring signal can be
amplified or attenuated at GS1 via selection of the feedback resistor between GS1 and IN1-. FSK
demodulation (which is always on Tip/Ring) or CAS detection (f or MEI or BT on-hook CLIP) of the

GS1 signal is enabled via the CB1 and CB2 pins. See Tables 1 and 2.
5 Vss Power supply ground.
6 OSC1 Oscillator (Input). Crystal connection. This pin can also be driven directly from an external clock

source.
7 OSC2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external clock, this pin

should be left open.
8 CB0 Control Bit 0 (CMOS Input). This pin is used primarily to select the 3-wire FSK data interface

mode. When it is low, interface mode 0 is selected where the FSK bit stream is output directly.

When it is high, interface mode 1 is selected where the FSK byte is stored in a 1 byte b uffer which

can be read serially by the application’s microcontroller.

The FSK interface is consisted of the DATA, DCLK and DR/STD pins. See the 3 pin descriptions

to understand how CB0 affects the FSK interface.

When CB0 is high and CB1, CB2 are both low the MT88E45 is put into a power down state

consuming minimal power supply current. See Tables 1 and 2.
9 DCLK 3-wire FSK Interface Data Clock (Schmitt Input/CMOS Output). In mode 0 (when the CB0 pin

is logic low) this is a CMOS output which denotes the nominal mid-point of a FSK data bit.

In mode 1 (when the CB0 pin is logic high) this is a Schmitt trigger input used to shift the FSK data

byte out to the DATA pin.

2

Advance Information MT88E45

Pin Description

Pin # Name Description

10 DATA 3-wire FSK Interface Data (CMOS Output). Mark frequency corresponds to logical 1. Space

frequency corresponds to logical 0.
In mode 0 (when the CB0 pin is logic low) the FSK serial bit stream is output to the DATA pin
directly.
In mode 1 (when the CB0 pin is logic high) the start bit is stripped off, the data byte and the trailing
stop bit are stored in a 9 bit buffer. At the end of each word signalled by the DR/STD pin, the
microcontroller should shift the byte out onto the DATA pin by applying 8 read pulses to the DCLK
pin. A 9th DCLK pulse will shift out the stop bit for framing error checking.

11 DR/STD 3-wire FSK Interface Data Ready/CAS Detection Delayed Steering (CMOS Output). Active

low.
When FSK demodulation is enabled via the CB1 and CB2 pins this pin is the Data Ready output.
It denotes the end of a word. In both FSK interface modes 0 and 1, it is normally hi and goes low
for half a bit time at the end of a word. But in mode 1 if DCLK starts during DR low, the first rising
edge of the DCLK input will return DR to high. This feature allows an interrupt requested by a low
going DR to be cleared upon reading the first DATA bit.
When CAS detection is enabled via the CB1 and CB2 pins this pin is the Delayed Steering output.
It goes low to indicate that a time qualified CAS has been detected.

12 EST CAS Detection Early Steering (CMOS Output). Active high. This pin is the raw CAS detection

output. It goes high to indicate the presence of a signal meeting the CAS accept frequencies and
signal level. It is used in conjunction with the ST/GT pin and external components to time qualify
the detection to determine whether the signal is a real CAS.

13 ST/GT CAS Detection Steering/Guard Time (CMOS Output/Analog Input). It is used in conjunction

with the EST pin and external components to time qualify the detection to determine whether the
signal is a real CAS.
A voltage greater than V
detected by asserting the DR/STD pin low. A voltage less than V
accept a new CAS and returns DR/STD to high.

14 CD Carrier Detect (CMOS Output). Active low.

A logic low indicates that an FSK signal is present. A time hysteresis is provided to allow for
momentary signal discontinuity. The demodulated FSK data is inhibited until carrier detect has

been activated.
15 Vdd Positive power supply.
16 CB1 Control Bit 1 (CMOS Input). Together with CB2 this pin selects the MT88E45’s functionality

between FSK demodulation, Tip/Ring CAS detection and Hybrid CAS detection.

When CB0 is high and CB1, CB2 are both low the MT88E45 is put into a power down state

consuming minimal power supply current. See Tables 1 and 2.
17 CB2 Control Bit 2 (CMOS Input). Together with CB1 this pin selects the MT88E45’s functionality

between FSK demodulation, Tip/Ring CAS detection and Hybrid CAS detection.

When CB0 is high and CB1, CB2 are both low the MT88E45 is put into a power down state

consuming minimal power supply current. See Tables 1 and 2.
18 GS2 Hybrid Gain Select (Output). This is the output of the hybrid receive connection op-amp. The op-

amp should be used to connect the MT88E45 to the telephone hybrid or speech IC receive pair.

The hybrid receive signal can be amplified or attenuated at GS2 via selection of the feedback

resistor between GS2 and IN2-. When the CPE is off-hook CAS detection of the GS2 signal

should be enabled via the CB1 and CB2 pins. See Tables 1 and 2.

at this pin causes the MT88E45 to indicate that a CAS has been

TGt

frees up the MT88E45 to

TGt

19 IN2- Hybrid Op-amp Inverting (Input).
20 IN2+ Hybrid Op-amp Non-Inverting (Input).

3

MT88E45 Advance Information

CB0 CB1 CB2

0/1 1 1 Set by CB0 FSK Demodulation. Tip/Ring input (GS1) selected. DR/STD is DR.
0/1 1 0 Set by CB0 Hybrid CAS Detection. Hybrid Receive input (GS2) selected. DR/STD is STD.
0/1 0 1 Set by CB0 Tip/Ring CAS Detection. Tip/Ring input (GS1) selected. DR/STD is STD.

1 0 0 Mode 1 Power Down. The MT88E45 is disabled and draws virtually no power supply

0 0 0 Mode 0 Reserved for factory testing.

The number of control bits (CB) required to interface the MT88E45 with the microcontroller depends on the
functionality of the application, as shown in Table 2.

Functionality Group Controls Description

FSK (mode 0 or 1) and
Hybrid CAS only
(Non MEI compatible)

FSK

Interface

Function

When the line is off-hook, a Bellcore Multiple Extension Interworking (MEI)
compatible Type 2 CPE should be able to detect CAS from Tip/Ring while the
CPE is on-hook because it may be the ACK sender. Tip/Ring CAS detection is
also required for BT’s on-hook CLIP.

current.

Table 1 - CB0/1/2 Functionality

CB2 CB0 is hardwired to Vdd or Vss to select the FSK

interface.
CB1 hardwired to Vdd.
The microcontroller uses CB2 to select between the 2
functions.

FSK (mode 0 or 1),
Hybrid CAS,
Tip/Ring CAS
(MEI compatible or BT on-hook CLIP)

FSK (mode 1),
Hybrid CAS,
Tip/Ring CAS,
Power Down
(MEI compatible or BT on-hook CLIP)

FSK (mode 0), Hybrid CAS,
Tip/Ring CAS, Power Down
(MEI compatible or BT on-hook CLIP)

Table 2 - Control Bit Functionality Groups

CB1
CB2

CB1
CB2

CB0
CB1
CB2

Functional Overview

The MT88E45 is compatible with FSK and FSK plus
CAS (CPE Alerting Signal) based Caller ID ser vices
around the world. Caller ID is the generic name for a
group of services offered by telephone operating
companies whereby information about the calling
party is delivered to the subscriber. In Europe and
some other countries Caller ID is known as Calling
Line Identity Presentation (CLIP). ETSI calls CAS
‘Dual Tone Alerting Signal’ (DT-AS), BT calls it ‘Tone
Alert Signal’.

Depending on the service, data delivery can occur
when the line is in the on-hook or off-hook state. In

CB0 is hardwired to Vdd or Vss to select the FSK
interface.
The microcontroller uses CB1 and CB2 to select between
the 3 functions.

CB0 is hardwired to Vdd to select FSK interface mode 1.
The microcontroller uses CB1 and CB2 to select between
the 4 functions.

All 3 pins are required.

most countries the data is modulated in either Bell
202 or CCITT V.23 FSK format and transmitted at
1200 baud from the serving end office to the
subscriber’s terminal. Additionally in off-hook
signalling, the special dual tone CAS is used to alert
the terminal before FSK data transmission. BT uses
CAS to alert the terminal prior to FSK in both on­hook (Idle State) and off-hook (Loop State)
signalling.

In North America, Caller ID uses the voiceband data
transmission interface defined in the Bellcore
document GR-30-CORE. The terminal or CPE
(Customer Premises Equipment) requirements are
defined in Bellcore document SR-TSV-002476.
Typical services are CND (Calling Number Delivery),

4

Advance Information MT88E45

CNAM (Calling Name Delivery), VMWI (Visual
Message Waiting Indicator) and CIDCW (Calling
Identity Delivery on Call Waiting).

In Europe, Caller ID requirements are defined by
ETSI. The CPE documents are ETS 300 778-1 for
on-hook, ETS 300 778-2 for off-hook. The end office
requirements are ETS 300 659-1 (on-hook) and ETS
300 659-2 (off-hook). ETSI has defined services
such as CLIP and CLIP with Call Waiting which are
similar to those of Bellcore. Some European
countries produce their own national specifications.
For example, in the UK BT’s standards are SIN227
and SIN242, the UK CCA (Cable Communications
Association) standard is TW/P&E/312.

In on-hook Caller ID, such as CND, CNAM and CLIP,
the information is typically transmitted (in FSK) from
the end office before the subscriber picks up the
phone. There are various methods such as between
the first and second rings (North Amer ica), between
an abbreviated ring and the first true ring (Japan,
France and Germany). On-hook Caller ID can also
occur without ringing for services such as VMWI. In
BT’s on-hook CLIP, the signalling begins with a line
polarity reversal, followed by CAS and then FSK.
Bellcore calls an on-hook capable Caller ID CPE a
‘Type 1 CPE’.

In off-hook Caller ID, such as CIDCW and CLIP with
Call Waiting, information about a new calling party is
sent to the subscriber who is already engaged in a
call. Bellcore’s method uses CAS to alert the CPE.
When the CPE detects CAS and there are no off­hook extensions, the CPE should mute its
transmission path and send an acknowledgment to
the end office via a DTMF digit called ACK. Upon
receiving ACK, the end office will send the FSK data.
Bellcore calls an off-hook capable CPE a ‘Type 2
CPE’. A Type 2 CPE is capable of off-hook and Type
1 functionalities and should ACK with a DTMF ‘D’.
The ETSI and BT off-hook signalling protocols are
similar to Bellcore’s but with timing and signal
parametric differences. ETSI has no requirement for
off-hook extension checking before ACK.

One factor affecting the quality of the CIDCW service
is the CPE’s CAS speech immunity. Although the end
office has muted the far end party before and after it
sends CAS, the near end (the end which is to receive
the information) user may be still talking. Therefore
the CPE must be able to detect CAS successfully in
the presence of near end speech. This is called the
talkdown immunity. The CPE must also be immune
to imitation of CAS by speech from both ends of the
connection because the CAS detector is
continuously exposed to speech throughout the call.
This is called the talkoff immunity.

If the CPE is a telephone, one way to achieve good
CAS speech immunity is to put CAS detection on the
telephone hybrid or speech IC receive pair instead of
on Tip and Ring. Talkdown immunity improves
because the near end speech has been attenuated
while the CAS level is the same as on Tip/Ring,
resulting in improved signal to speech ratio. Talkoff
immunity is also improved because the near end
speech has been attenuated.

In the present Bellcore off-hook protocol, the CPE
should not ACK if it detected an off-hook extension.
The FSK will not be sent and the customer will not
receive a paid for service. Bellcore, in conjunction
with the TIA (Telecommunications Industry
Association) TR41.3.1 working group, has defined a
CPE capability called Multiple Extension
Interworking (MEI) which will overcome this problem.

In the MEI scheme, all MEI compatible CPE’s must
be capable of detecting CAS when the line is off­hook, even though the CPE itself may be on-hook.
This is because under some conditions an on-hook
CPE may become the ACK sender. Another reason
for the on-hook CPE to detect CAS is to maintain
synchronous call logs between on and off-hook
CPEs. When CAS is received and all off-hook CPEs
are MEI compatible, one of the CPEs will ACK and
all compatible sets will receive FSK.

A problem arises in a CPE where the CAS detector
is connected only to the hybrid or speech IC receive
pair: it cannot detect CAS when it is on-hook. The
reason is that when the CPE is on-hook either the
hybrid/speech IC is non functional or the signal level
is severely attenuated. Therefore an on-hook Type 2
CPE must be capable of detecting CAS from Tip/
Ring, in addition to detecting CAS from the hybrid/
speech IC receive signal when it is off-hook.

The MT88E45 offers an optimal solution which
combines good speech immunity and MEI
compatibility. Two input op-amps allow the MT88E45
to be connected both to Tip/Ring and to the hybrid/
speech IC receive pair. Both connections can be
differential or single ended. FSK demodulation is
always on the Tip/Ring signal. CAS detection can be
from the Tip/Ring or hybrid/speech IC receive signal.
Being able to detect CAS on Tip/Ring also makes the
MT88E45 suitable for BT on-hook CLIP applications.

For applications such as those in most European
countries where Tip/Ring CAS detection is not
needed, then the Tip/Ring and Hybrid op-amp gains
can be tailored independently to meet country
specific FSK and CAS signal level requirements
respectively. Note that since the Hybr id op-amp is for

5

MT88E45 Advance Information

CAS detection only, its gain can always be tailored
specifically for the CAS signal level.

The FSK demodulator is compatible with Bellcore,
ETSI and BT standards. The demodulated FSK data
is either output directly (bit stream mode) or stored in
a one byte buffer (buffer mode). In the buffer mode,
the stop bit immediately following a byte is also
stored and can be shifted out after the data byte.
This facility allows for framing error checking
required in Type 2 CPEs. In the bit stream mode, two
timing signals are provided. One indicates the bit
sampling instants of the data byte, the other the end
of byte. A carrier detector indicates presence of
signal and shuts off the data stream when there is no
signal.

The entire chip can be put into a virtually zero
current power down mode. The input op-amps, FSK
demodulator, CAS detector and the oscillator are all
shut off. Furthermore, power management has been
incorporated to minimize operating current. When
FSK is selected the CAS detector is powered down.
When CAS is selected the FSK demodulator is
powered down.

Functional Description

hook CLIP, while Hybrid CAS detection is needed for
optimal CAS speech immunity.

The feedback resistor connected between GS1 and
IN1- can be used to adjust the Tip/Ring signal gain.
The feedback resistor connected between GS2 and
IN2- can be used to adjust the hybrid receive signal
gain. When the Tip/Ring op-amp is selected, the
GS2 signal is ignored. When the Hybrid op-amp is
selected, the GS1 signal is ignored.

Either or both op-amps can be configured in the
single ended input configuration shown in Figure 3,
or in the differential input configuration shown in
Figure 4.

IN+

C

Voltage Gain

(AV) = RF / R

Highpass Corner Frequency

f

= 1/(2πRINC)

-3dB

R

IN

IN

R

F

IN-

GS

V

REF

Figure 3 - Single Ended Input Configuration

3 to 5V Operation

The MT88E45’s FSK and CAS reject levels are
proportional to Vdd. When operated at Vdd equal 3V
+/- 10%, to keep the FSK and CAS reject levels as at
5V (nominal) the Tip/Ring and Hybrid op-amp gains
should be reduced from those of 5V. Gains for
nominal Vdd (with a +/- 10% variation) other than 3
or 5V can be chosen as interpolation between the 3
and 5V settings.

Input Configuration

The MT88E45 provides an input arrangement
comprised of two op-amps and a bias source (V
V

is a low impedance voltage source which is

REF

REF

used to bias the op-amp inputs at Vdd/2. The Tip/
Ring op-amp (IN1+, IN1-, GS1 pins) is for connecting
to Tip and Ring. The Hybrid op-amp (IN2+, IN2-,
GS2 pins) is for connecting to the telephone hybrid
or speech IC receive pair.

Either FSK or CAS detection can be selected for the
Tip/Ring connection, while the hybrid connection is
for CAS detection only. Phrased in another way, FSK
demodulation is always on Tip/Ring, while CAS
detection can be on Tip/Ring or Hybrid Receive. Tip/
Ring CAS detection is required for MEI and BT on-

R1

C1

R4

C2

R3

Differential Input Amplifier

C1 = C2
R1 = R4 (For unity gain R5= R4)
R3 = (R2R5) / (R2 + R5)

Voltage Gain

(A

diff) = R5/R1

).

V

Input Impedance

(Z

diff) = 2

IN

R1

2

+ (1/ωC)

R5

R2

Highpass Corner Frequency

f

= 1/(2πR1C1)

-3dB

2

IN+

IN-

GS

V

REF

Figure 4 - Differential Input Configuration

CAS Detection

In North America, CAS is used in off-hook signalling
only. In Europe (ETSI) it is used in off-hook
signalling, and by BT in both on and off-hook
signalling. ETSI calls it the Dual Tone Alerting Signal
(DT-AS). Although the ETSI on-hook standard
contains a DT-AS specification, BT is the only
administration known to employ CAS in on-hook

6

Advance Information MT88E45

c

2130 Hz and 2750 Hz

CAS/DT-AS Characteristics

Bellcore

a

(Off-hook only)

(Off-hook)

ETSI

b

(Off-hook = ‘Loop State’)

(On-hook = ‘Idle State’)

Frequency Tolerance +/-0.5% +/-0.5% Off-hook: +/-0.6%

On-hook: +/-1.1%

Signal Level (per tone) -14 to -32 dBm

d

-9.78 to -32.78 dBm

+0.22 to -37.78 dBm

(-12 to -35 dBVe)

Reject Level (per tone) -45 dBm On-hook: -43.78 dBm

BT

(-2 to -40 dBV)

(-46 dBV)

Maximum Twist (V

2130Hz/V2750Hz

) +/-6 dB +/-6 dB +/-7 dB

Duration 75 to 85 ms 75 to 85 ms Off-hook: 80 to 85 ms

On-hook: 88 to 110 ms

Reject Duration Off-hook: <=70 ms

On-hook: <=20 ms

Signal to Noise Ratio Speech Speech Off-hook: Speech

On-hook: >= 20 dB

(300-3400 Hz)

Hybrid Op-amp (GS2) Gain

0 dB 0 dB 0 dB

Vdd = 5V +/- 10%
Hybrid Op-amp (GS2) Gain

-3.5 dB -3.5dB TBD

Vdd = 3V +/- 10%

a. SR-TSV-002476, Issue 1 Dec 1992
b. ETS 300 778-2 Jan 98. The DT-AS plus FSK variant of ETSI on-hook signalling described in ETS 300 778-1 is not supported

because on-hook DT-AS uses the GS1 op-amp. With the GS1 gain in Table 4, the minimum DT-AS level will be below the

MT88E45’s minimum accept level.
c. SIN227 Issue 3 Nov 97, SIN242 Issue 2 Nov 96
d. dBm - Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms.
e. dBV - Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms

Table 3 - CAS/DT-AS Characteristics

signalling. (BT calls it Tone Alert Signal.) The CAS/
DT-AS characteristics are summarized in Table 3.

is key to good speech immunity. The first indication
that there might be a CAS is when EST goes high.
EST high indicates that both tones are present. EST

Table 3 shows the Hybrid op-amp gain for operation
at 3V and 5V nominal Vdd, with a ± 10% Vdd
variation. For 3V operation, the Hybrid op-amp gain
should be reduced from the 5V setting to maintain

low indicates that one or both tones is not present.
STD low indicates that CAS has been detected.
When STD returns high it indicates that CAS has
ended.

the CAS reject level and to maintain the talkoff
immunity: the CAS threshold is directly proportional
to Vdd, when Vdd is reduced the threshold becomes
lower, hence lower level CAS are accepted. If the
gain is not reduced, the MT88E45 will be more
talkoff prone.

The timing algorithm consists of 2 components: a
tone present guard time (tGP) and a tone absent
guard time (tGA). tGP sets the minimum accept
duration for CAS. That is, both tones must be
detected continuously for tGP for STD to go low to
indicate that CAS has been detected. For STD to

When CAS detection is selected, the dual purpose
output pin DR/STD is STD. STD goes low when CAS
has been detected, and returns high after CAS has
ended.

return high to indicate that CAS has ended, one or
both tones must have disappeared for tGA. The
purpose of tGA is to bridge over momentary EST
dropouts once EST has met the minimum tone
duration so as to decrease the likelihood of a long
talkoff being broken up into several talkoffs. Usually

CAS Guard Time

tGA is set very short or removed altogether because

there is another way to deal with the problem (by
The guard time circuit shown in Figure 5 implements
a timing algorithm which determines whether the

ignoring further detections for 2 seconds after every

detection).
signal is a CAS. Proper selection of the guard time(s)

7

MT88E45 Advance Information

Both Tones Present

CAS

EST

ST/GT

MT88E45

P

Q1

+

-

Comparator

t

DP

t

REC

t

GP

VTGt

Q2

N

= Vss

t

DA

t

ABS

t

GA

=R1C ln [Vdd / (Vdd-VTGt)]

t

GP

=RpC ln Vdd - Vdiode (Rp/R2)

t

GA

Rp=R1 || R2

=0 if R2=0

t

GA

Vdd

C

ST/GT

V

diode

R1

EST

Rp=R1 || R2

DR/STD
Indicates STD in CAS

detection mode

VTGt - Vdiode (Rp/R2)

R2

STD

Figure 5 - CAS Guard Time Circuit Operation

Tone present guard time (tGP) operation: In Figure 5
initially there is no CAS, EST is low so Q1 is off. C
has been fully charged applying 0V to ST/GT so Q2
is on. When both tones are detected EST goes high
and turns off Q2. Because C has been fully charged
(ST/GT=0V), the comparator output is low and Q1
stays off. With both Q1 and Q2 off the high at EST
discharges C through R1 and the ST/GT voltage
increases from 0V. When the voltage exceeds the
comparator threshold VTGt, which is typically 0.5
Vdd, the comparator output goes high; Q1 turns on
and accelerates the discharge of C (ST/GT goes
quickly to Vdd); STD goes low to indicate that a valid
CAS has been received. If one or both tones
disappeared before tGP has been reached (i.e. when
ST/GT voltage is still below VTGt), Q2 turns back on
and charges C quickly to bring the ST/GT voltage
back to 0V. Then if EST goes high again the t

GP

duration must start over.

Tone absent guard time (tGA) operation: In Figure 5
initially both tones have been detected for tGPso C is
fully discharged and ST/GT is at Vdd. While both
tones continue to be detected EST stays high; ST/

GT is at Vdd (the comparator output is high); so Q1
is on and Q2 is off. When one or both tones stop
EST goes low and turns off Q1. Because C is fully
discharged (ST/GT=Vdd), the comparator output is
high and Q2 stays off. With both Q1 and Q2 off the
low at EST charges C through Rp=(R1 || R2) and the
ST/GT voltage falls towards 0V. When the voltage
has fallen below VTGt, the comparator output goes
low. Since EST is also low Q2 turns on and
accelerates the charging of C so that ST/GT goes
quickly to 0V. STD goes high to indicate that the CAS
has ended. If EST goes back to high before tGA has
been reached (i.e. when ST/GT voltage is still above
V

), Q1 turns back on and discharges C quickly to

TGt

bring the ST/GT voltage back to Vdd. Then if EST
goes low again the tGA duration must start over. To
set tGA=0, set R2 to 0.

In Figure 5, tDP is the delay from the start of CAS to
EST responding, tDA is the delay from the end of CAS
to EST responding. The total delay from the start of
CAS to STD responding is t

REC=tDP+tGP.

The total
delay from the end of CAS to STD responding is
t

ABS=tDA+tGA

.

8

Advance Information MT88E45

Parameter North America: Bellcore

a

Europe: ETSI

b

UK: BT

c

Mark (Logical 1) Frequency 1200 Hz +/- 1% 1300 Hz +/- 1.5%
Space (Logical 0) Frequency 2200 Hz +/- 1% 2100 Hz +/- 1.5%
Received Signal Level -4.23 to -36.20 dBm

(476 to 12 mVrms)

d

Signal Reject Level -48.24 dBm (3mVrms) for

On-hook No Ring Signalling

-5.78 to -33.78 dBm
(-8 to -36 dBV)

On-hook: -47.78 dBm

(-50dBV)

f,g

e

-5.78 to -37.78 dBm
(-8 to -40 dBV)

such as VMWI
Transmission Rate 1200 baud +/- 1% 1200 baud +/- 1%
Twist (V

MARK/VSPACE

Signal to Noise Ratio Single Tone (f):

) -6 to +10 dB -6 to +6 dB

>= 25 dB

-18 dB (f<=60Hz)

(300 to 3400 Hz)

>= 20 dB

(300 to 3400 Hz)

-12 dB (60<f<=120Hz)

-6 dB (120<f<=200Hz)

+25 dB (200<f<3200Hz)

+6 dB (f>=3200Hz)

Tip/Ring Op-Amp (GS1) Gain

0 dB -2 dB

h

0 dB

Vdd = 5V +/- 10%
Tip/Ring Op-Amp (GS1) Gain

-3.5 dB -5.5 dB

i

TBD

Vdd = 3V +/- 10%

a. ANSI/TIA/EIA-716 and draft TIA/EIA-777. Bellcore has agreed to the values and will synchronize its requirements.
b. ETS 300 778-1 (On-hook) Sep 97, ETS 300 778-2 (Off-hook) Jan 98.
c. SIN 227 Issue 3 Nov 97, SIN242 Issue 2 Nov 96.
d. Nor th Amer ican on-hook signalling range. The off-hook range is inside the on-hook range: 190mVrms to 12mVrms.
e. dBm - Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms
f. dBV - Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms.
g. ETSI on-hook signalling range. The off-Hook signalling levels are inside this range: -8.78 to -30.78 dBm (-11 to -33 dBV).
h. The 5V ETSI Tip/Ring op-amp gain can be 0 dB if there is no FSK reject level requirement.
i. The 3V ETSI Tip/Ring op-amp gain can be -3.5dB if there is no FSK reject level requirement.

Table 4 - FSK Signal Characteristics

FSK Demodulation

The FSK characteristics are shown in Table 4. In
North America, TIA (Telecommunications Industry
Association) also defines standards. The Type 1
Caller ID CPE standard is ANSI/TIA/EIA-716. The
Type 2 standard is being drafted to become TIA/EIA-

777. The North American FSK characteristics in
Table 4 are from ANSI/TIA/EIA-716. They differ from
those Bellcore published in SR-TSV-002476 and SR-

3004. Bellcore is represented in TR41.3.1 and will
synchronize to the TIA requirements in its future
documents.

The TIA Type 1 standard includes an FSK reject
level:

• if data is not preceded by ringing (e.g. VMWI),
FSK signals below 3mVrms (-48.24 dBm) shall
be rejected

• if data is preceded by ringing, FSK detection
may be extended below 3mVrms

The MT88E45 is compliant with the Bellcore/TIA,
ETSI and BT requirements with the Tip/Ring op-amp
gains in Table 4. In Europe if the country specific
FSK requirements do not incorporate ETSI’s FSK
reject level then the Tip/Ring op-amp gain can also
be 0dB at 5V and -3.5dB at 3V to meet the ETSI
minimum CAS level for on-hook signalling (-40 dBV).

For 3V operation, the FSK receiver becomes more
sensitive and lower level signals will be accepted
than at 5V. To maintain the FSK reject level, the Tip/
Ring input op-amp gain should be reduced. Note that
since the Tip/Ring op-amp is also used for Tip/Ring
CAS detection, the CAS level will also be reduced for
on-hook detection.

9

MT88E45 Advance Information

FSK Data Interface

The MT88E45 provides a powerful dual mode 3-wire
interface so that the data bytes in the demodulated
FSK bit stream can be extracted without the need
either for an external UART or for the CPE’s
microcontroller to perform the function in software.
The interface is specifically designed for the 1200
baud rate and is consisted of 3 pins: DATA, DCLK
(Data Clock) and DR (Data Ready). DR/STD is a
dual purpose output pin. When FSK is selected it is
DR.

Two modes (modes 0 and 1) are selectable via the
CB0 pin. In mode 0, the FSK bit stream is output
directly. In mode 1, the data byte and the trailing stop
bit are stored in a 9 bit buffer. If mode 1 is desired,
the CB0 pin can be hardwired to Vdd. If mode 0 is
desired and full chip power down is not required, the
CB0 pin can be hardwired to Vss.

In Bellcore’s off-hook protocol, a Type 2 CPE should
restore the voicepath within 50ms after the end of
the FSK signal. Due to noise, end of carrier detection
is not always reliable. The draft TIA Type 2 standard
has proposed that the CPE must detect the end of
FSK when any one of the following occurs:

• absence of carrier signal or,

• more than five framing errors (trailing stop bit a
0 instead of a 1) have been detected in the FSK
message or,

• more than 150ms of continuous mark signal or
space signal has been detected.

bit, it can also be used to read the stop bit to check
for framing error.

Alternatively, DCLK and DATA may occupy 2 bits of a
microcontroller’s input port. The microcontroller polls
the input port and saves the DATA bit whenever
DCLK changes from low to high. When DR goes low,
the word may then be assembled from the last 8
saved bits.

DATA may also be connected to a personal
computer’s serial communication port after
conversion from CMOS to RS-232 voltage levels.

Mode 1 - Buffer Mode

This mode is selected when the CB0 pin is high. In
this mode the received byte is stored on chip. At the
end of a byte DR goes low to indicate that a new byte
has become available. The microcontroller applies
DCLK pulses to read the register contents serially
out of the DATA pin (see Figure 14).

Internal to the MT88E45, the star t bit is stripped off,
the data bits and the trailing stop bit are sampled and
stored. Midway through the stop bit, the 8 data bits
and the stop bit are parallel loaded into a 9 bit shift
register and DR goes low . The register’s contents are
shifted out to the DATA pin on the supplied DCLK’s
rising edges in the order they were received. The last
bit must be shifted out and DCLK returned to low
before the nextDR. DCLK must be low for t
DR goes low and must remain low for t
has gone low (see Figure 14).

DDS

after DR

DDH

before

Mode 0 - Bit Stream Mode

This mode is selected when the CB0 pin is low. In
this mode the FSK data is output directly to the DATA
pin. DCLK and DR pins are timing signal outputs
(see Figure 13).

For each received stop and start bit sequence, the
MT88E45 outputs a fixed frequency clock string of 8
pulses at the DCLK pin. Each DCLK rising edge
occurs in the middle of a DATA bit cell. DCLK is not
generated for the start and stop bits. Consequently,
DCLK will clock only valid data into a peripheral
device such as a serial to parallel shift register or a
microcontroller. The MT88E45 also outputs an end
of word pulse (Data Ready) at the DR pin. DR goes
low for half a nominal bit time at the beginning of the
trailing stop bit. It can be used to interrupt a
microcontroller or cause a serial to parallel converter
to parallel load its data into the microcontroller. Since
the DR rising edge occurs in the middle of the stop

10

If DCLK begins while DR is low , DR will return to high
upon the first DCLK rising edge. If DR interrupts a
microcontroller then this feature allows the interrupt
to be cleared by the first read pulse. Otherwise DR is
low for half a nominal bit time (1/2400 sec).

Reading the stop bit allows the software to check for
framing errors. When framing error is not checked
the microcontroller only needs to send 8 DCLK
pulses to shift the data byte out.

Carrier Detect

The carrier detector provides an indication of the
presence of a signal in the FSK frequency band. It
detects the presence of a signal of sufficient
amplitude at the output of the FSK bandpass filter.
The signal is qualified by a digital algorithm before
the CD output is set low to indicate carrier detection.
A 10ms hysteresis is provided to allow for
momentary signal dropout once CD has been

Advance Information MT88E45

activated. CD is released when there is no activity at
the FSK bandpass filter output for 10ms.

When CD is inactive (high), the raw output of the
FSK demodulator is ignored by the internal data
timing recovery circuit. In mode 0 the DATA, DCLK
and DR pins are forced high. In mode 1 the output
shift register is not updated and DR is high; if DCLK
is clocked, DATA is undefined.

Note that signals such as speech, CAS and DTMF
tones also lie in the FSK frequency band and the
carrier detector may be activated by these signals.
They will be demodulated and presented as data. To
avoid the false data, the MT88E45 should be put into
CAS or power down mode when FSK is not
expected. Ringing, on the other hand, does not pose
a problem as it is ignored by the carrier detector.

Interrupt

The DR/STD output can be used to interrupt a
microcontroller. When the MT88E45 is the only
interrupt source, DR/STD can be connected directly
to the microcontroller’s interrupt input. Figure 9
shows the necessary connections when the
MT88E45 is one of many interrupt sources. The
diodes and resistors implement a wired-or so that the
microcontroller is interrupted (INT low active or
falling edge triggered) when one or more of INT1,
INT2 or DR/STD is low. The microcontroller can
determine which one of DR/STD, INT1 or INT2
caused the interrupt by reading them into an input
port.

When system power is first applied and CB0/1/2
have already been configured to select CAS
detection, DR/STD will power up as logic low. This is
because there is no charge across the ST/GT
capacitor in Figure 5, hence ST/GT is at Vdd which
causes STD to be low. If DR/STD is used to interrupt
a microcontroller the interrupt will not clear until the
capacitor has charged up. Therefore upon initial
power up the microcontroller should ignore this
interrupt source until there is sufficient time to
charge the capacitor. Alternatively, the MT88E45 can
be put into power down mode: DR/STD goes high
and clears the interrupt, ST/GT goes low and the
capacitor will charge up quickly.

In power down mode both input op-amps, V

REF

and
the oscillator are non functional. DCLK becomes an
input because to select the power down state CB0 is
1 which will select FSK interface mode 1. If the
application uses FSK interface mode 0 and the
MT88E45 needs to be powered down then a pull
down resistor should be added at the DCLK pin to
define its state during power down (R15 in Figure 7).
When the MT88E45 is powered down DATA, DR/
STD, CD are high; EST and ST/GT are low.

To reduce the operating current an Intelligent Power
Down feature has been incorporated. When FSK is
selected, the CAS detector is powered down. When
CAS is selected the FSK demodulator is powered
down. The two input op-amps are not affected and
both will remain operational.

Oscillator

The MT88E45 requires a 3.579545MHz crystal or
ceramic resonator to generate its oscillator clock. To
meet the CAS detection frequency tolerance
specifications the crystal or resonator must have a

0.1% frequency tolerance. The crystal specification
is as follows: (e.g. CTS MP036S)

Frequency: 3.579545MHz
Frequency Tolerance: ± 0.1% (over temperature

range of the application)
Resonance Mode: Parallel
Load Capacitance: 18pF
Maximum Series
Resistance: 150Ω
Maximum Drive Level: 2mW

Alternatively an external clock source can be used.
In which case the OSC1 pin should be driven directly
from a CMOS buffer and the OSC2 pin left open.

For 5V+/-10% applications any number of
MT88E45’s can be connected as shown in Figure 6
so that only one crystal is required.

MT88E45 MT88E45 MT88E45

OSC1 OSC2 OSC1 OSC2

OSC1 OSC2

Power Down

The MT88E45 can be powered down to consume
virtually no power supply current via a state of the
CB0/1/2 pins. Momentary transition of CB0/1/2 into
the power down code will not activate power down.

3.579545 MHz
(For 5V+/-10% applications only)

next MT88E45

Figure 6 - Common Crystal Connection

to the

11

MT88E45 Advance Information

Application Circuits

TIP

RING

R5 R6

D1

R1

C1

D3

R2

C2
= To Microcontroller
= From Microcontroller

(FSK Interface Mode 1 selected)

R15 is required only if
interface mode 0 and power
down features are used.

Unless stated otherwise, resistors are 1%, 0.1Watt; capacitors are 5%, 6.3V.
For 1000Vrms, 60Hz isolation from Tip to Earth and Ring to Earth:

R1,R2 430K, 0.5W, 5%, 475V min.C1,C2 2n2, 1332V min.

(e.g. IRC type GS-3)

both FSK

D4

D2

R15

R3

R4

Vss

R7

Xtal

TIP

RING

V

REF

IN1+
IN1­GS1
Vss
OSC1
OSC2
CB0
DCLK
DATA

Telephone

Hybrid

Speech IC

(Symbolic)

MT88E45

or

Tx+

Tx-

Rx+

Rx-

IN2+

IN2­GS2
CB2
CB1

Vdd

CD

ST/GT

EST

DR/STD

R11

R12

R13
R14

Microphone

Speaker

R10

R8

C3

R9

C4

Vdd

C5 C6

C6 should be
connected directly

D5

across Vdd and Vss
pins

If the 1000Vrms is handled by other methods then this circuit has to meet the FCC Part 68 Type B Ringer requirements:
R1,R2 432K, 0.1W, 1%, 56V min. C1,C2 2n2, 212V min.

Common to both sets of R1,R2: 5V, 0dB gain 3V, -3.5dB gain
R3,R4 34K C3,C4 2n2 R5,R10 53K6 35K7
R8,R9 464K C5 100n R6,R11 60K4 40K2
R13 825K C6 100n, 20% R7,R12 464K 309K
R14 226K or 26K1 D1-D4 Diodes. 1N4148 or equivalent
R15 100K, 20% D5 Diode. 1N4148 or equivalent

Xtal 3.579545MHz, 0.1% crystal

or ceramic resonator

Figure 7 - Application Circuit: Bellcore MEI Compatible Type 2 Telephone

12

Advance Information MT88E45

1.00

0.95

0.90

0.85

0.80

0.75

Gain Ratio

0.70

0.65

0.60

0.55

0.50

0.668

0.531

3.0 3.5 4.0 4.5 5.0

Gain ratio for
Bellcore GS1, GS2
ETSI GS2 op amps

Nominal Vdd (Volts)

Figure 8 - Gain Ratio as a Function of Nominal Vdd

Gain Setting Resistor Calculation Example for Figure 8:

0.794

Gain ratio for ETSI
GS1 op amp

• For the desired nominal Vdd, use Figure 8 to determine approximate Av.

• For the GS1 op-amp, start with the 0dB gain setting resistor values of R5

0dB

, R6

0dB

and R7

0dB

Figure 7 these values are 53K7, 60K4 and 464K respectively. Keep C1,C2,R1,R2,R3,R4 as in Figure 7
to maintain the highpass corner frequency constant for all gain settings.

• For the desired gain setting of Av:

R7Av= R7

0dB

x A

V

Scaled for desired gain. Choose
the closest standard resistor value as R7Av.

R5Av= R5

0dB

x A

Actual Av from now on is R7Av/R7

V

Scaled for good common mode range. Choose

0db

the closest standard resistor value as R5Av.

1/R6Av = 1/R5Av - 1/R7

Av

Calculate R6Av so that R5Av=R6Av || R7Av. Choose
the closest standard resistor value as R6Av.

• Repeat for R10, R11, R12for the GS2 op-amp.

Example:

• For a gain of -3.5dB, Av=10

•R7

= 464K x 0.668 = 309K9, the closest standard resistor value is 309K.

-3.5dB

-3.5/20

= 0.668

Av is now 309K/464K = 0.666

•R5
Therefore R6

= 53K6 x 0.666 = 35K7, the closest standard resistor value is 35K7.

-3.5dB

is calculated to be 40K4, the closest standard resistor value is 40K2.

-3.5dB

. In

13

MT88E45 Advance Information

Interrupt Source 1

INT1

(Open Drain)

Interrupt Source 2

INT2

(CMOS)

MT88E45

DR/STD
(CMOS)

Figure 9 - Application Circuit: Multiple Interrupt Source

Vdd

Resistor (R1)

R1 can be opened and
D1 shorted if the
microcontroller does not
read the

D1

INT1 pin.

Vdd

Resistor (R2)

Microcontroller

INT(input)

Input Port Bit

14

Advance Information MT88E45

Absolute Maximum Ratings* - Voltages are with respect to V

unless otherwise stated

SS

Parameter Symbol Min Max Units

1 Supply voltage with respect to V
2 Voltage on any pin other than supplies

ss

**

3 Current at any pin other than supplies I
4 Storage Temperature T

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
**

Under normal operating conditions voltage on any pin except supplies can be minimum V

limited to less than 200µΑ

Recommended Operating Conditions - Voltages are with respect to ground (V

Characteristics Sym Min Typ

1 Power Supplies V
2 Clock Frequency f

DD

OSC

V

DD

V

PIN

PIN

ST

-0.3 6 V

Vss-0.3 VDD+0.3 V

-65 150

-1V to maximum VDD+1V for an input current

SS

) unless otherwise stated.

SS

‡

Max Units

2.7 5.5 V

3.579545 MHz

10 mA

3 Tolerance on Clock Frequency ∆fc -0.1 +0.1 %
4 Operating Temperature T

o

‡ Typical figures are at 25

DC Electrical Characteristics

C and are for design aid only: not guaranteed and not subject to production testing.

†

Characteristics Sym Min Typ

OP

-40 85

‡

Max Units Test Conditions

o

C

o

C

1

Standby Supply

I

DDQ

0.1 15 µA All inputs are

Current

S
U
P

2 Operating Supply

P
L
Y

Current
VDD = 5V ±10%
VDD = 3V ±10%

I

DD

3.0

1.7

8

4.5

mA
mA

3 Power Consumption PO 44 mW
4

Schmitt Input High

V

T+

0.48*V

DD

0.68*V

DD

V

Threshold

DCLK

Schmitt Input Low

V

T-

0.28*V

DD

0.48*V

DD

V

Threshold
5 Schmitt Hysteresis V
6

CB0
CB1
CB2

CMOS Input High

Voltage

CMOS Input Low

HYS

V

V

IH

IL

0.2 V

0.7*V

V

SS

DD

V

DD

0.3*V

DD

V

V

Voltage

DCLK

7

DATA
DR/STD
CD, EST

ST/GT

Output High
Source Current

I

OH

0.8 mA VOH=0.9*V

VDD/VSS except
for oscillator pins.
No analog input.
outputs unloaded.
CB0/1/2 = 1/0/0

All inputs are
VDD/VSS except
for oscillator pins.
No analog input.
outputs unloaded.

DD

15

MT88E45 Advance Information

DC Electrical Characteristics† (continued)

Characteristics Sym Min Typ

DCLK

10

8

9

DATA
DR/STD
CD, EST

ST/GT

IN1+

IN1-

IN2+

IN2-

DCLK

CB0
CB1
CB2

GT

Output Low Sink

I

OL

2mAV

Current

Input Current Iin1 1 µAVin=VDD to V

Iin2 10 µAVin=VDD to V

Output High-

Ioz1 5 µAV

Impedance Current

V

11

REF

12 Output Resistance R
13

GT

Output Voltage V

Comparator

V

0.5VDD-0.1 0.5VDD+0.1 V No Load

REF

REF

0.5VDD-0.05 0.5VDD+0.05 V

TGt

Threshold Voltage

† DC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.

‡

Max Units Test Conditions

=0.1*V

OL

out

DD

=VDD to V

SS

SS

SS

2kΩ

AC Electrical Characteristics† - CAS Detection

Characteristic Sym Min Typ

1 Lower Tone Frequency f
2 Upper Tone Frequency f

L

H

3 Frequency Deviation: Accept 1.1%

4 Frequency Deviation: Reject 3.5%

5 Accept Signal Lev el (per tone)

Reject Signal Level (per tone)

6

Vdd=5V +/-10%
Reject Signal Level (per tone)

7

Vdd=3V+/-10%, 5V+/-10%

8 Twist: 20 log (V

2130Hz/V2750Hz

9 Signal to Noise Ratio SNR

† AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing
*Notes:

1. Tip/Ring signal level. Input op-amp configured to 0dB gain at Vdd=5V+/-10%, -3.5dB at Vdd=3V+/-10%.

2. Tip/Ring signal level. Input op-amp configured to 0dB gain at Vdd=5V+/-10%.

3. Both tones have the same amplitude.

4. Band limited random noise 300-3400Hz. Measurement valid only when tone is present.

5. dBV - Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms. Signal level is per tone.

6. dBm - Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms. Signal level is per tone.

)-7+7dB

CAS

-40

-37.78

20 dB 3,4

‡

Max Unit Notes*

2130 Hz
2750 Hz

-2

0.22

-46

-43.78

-47.22

-45

dBV

dBm

dBV

dBm

dBV

dBm

range within

which tones are

accepted

range outside of

which tones are

rejected

1, 5, 6

2, 5, 6

1, 5, 6

16

Advance Information MT88E45

AC Electrical Characteristics† - FSK Demodulation

Characteristics Sym Min Typ

‡

Max Units Notes*

1 Accept Signal Level Range

2 Bell 202 Format Reject Signal Level

-40

-37.78

10.0

-6.45

-4.23
476

-48.24

-50.46
3

dBV

dBm

mVrms

dBm

dBV

mVrms

1, 2, 4, 5

1, 2, 4, 5

3 Transmission Rate 1188 1200 1212 baud
4 Mark and Space Frequencies

Bell 202 1 (Mark)
Bell 202 0 (Space)

CCITT V.23 1 (Mark)
CCITT V.23 0 (Space)

5 Twist: 20 log (V

MARK/VSPACE

6 Signal to Noise Ratio SNR

† AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are nominal values and are for design aid only: not guaranteed and not subject to production testing.
*Notes:

1. Both mark and space have the same amplitude.

2. Tip/Ring signal level. Input op-amp configured to 0dB gain at Vdd=5V+/-10%, -3.5dB at Vdd=3V+/-10%.

3. Band limited random noise (200-3400Hz). Present when FSK signal is present. Note that the BT band is 300-3400Hz, the Bellcore
band is 0-4kHz.

4. dBV - Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms.

5. dBm - Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms.

) -6 +10 dB

FSK

1188
2178

1280.5

2068.5

1200
2200

1300
2100

1212
2222

1319.5

2131.5

Hz
Hz

Hz
Hz

20 dB 1,3

Electrical Characteristics† - Gain Setting Amplifiers

Characteristics Sym Min Max Units Test Conditions

1 Input Leakage Current I
2 Input Resistance R
3 Input Offset Voltage V

IN

OS

in

10 MΩ

4 Power Supply Rejection Ratio PSRR 30 dB 1kHz ripple on V
5 Common Mode Rejection CMRR 40 dB V
6 DC Open Loop Voltage Gain A
7 Unity Gain Bandwidth f
8 Output Voltage Swing V

9 Capacitive Load (GS1,GS2) C
10 Resistive Load (GS1,GS2) R
11 Common Mode Range Voltage V

† Electrical characteristics are over recommended operating conditions, unless otherwise stated.

VOL

C

O

L

L

CM

40 dB

0.3 MHz

0.5

100 kΩ

1.0

1 µAVSS ≤ VIN ≤ V

25 mV

CMmin

V

DD

-0.7

V Load ≥ 100kΩ

50 pF

V

DD

-1.0

V

≤ VIN ≤ V

DD

DD

CMmax

17

MT88E45 Advance Information

AC Electrical Characteristics† - CAS Detection Timing

Characteristics Sym Min Max Units Notes

1 Tone present detect time t
2 Tone absent detect time t

† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.

DP
DA

0.5 10 ms See Figures 16, 17

0.1 8 ms See Figures 16, 17

AC Electrical Characteristics† - 3-Wire Interface Timing

Characteristics Sym Min Max Units Notes

1

OSC2

2 Power-down time t
3
4 Input FSK to CD high delay t

CD

Power-up time t

Input FSK to CD low delay t

PU

PD

CP

CA

50 ms
10 ms
25 ms

10 ms

5 Hysteresis 10 ms

† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.

AC Electrical Characteristics† - 3-Wire Interface Timing (Mode 0)

Characteristics Sym Min Typ

1

DR/STD

2 Fall time t

Rise time t

3 Low time t
4
5 Input FSK to DATA

DATA

Rate 1188 1200 1212 baud 1

delay

t

RR

RF

RL

IDD

415 416 417 µs2

‡

Max Units Notes*

200 ns into 50pF Load
200 ns into 50pF Load

15ms

6
7 Fall time t
8 DATA to DCLK delay t

DATA

DCLK

9 DCLK to DATA delay t
10
11 High time t

DCLK

12 Low time t
13

† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.
*Notes:

1. FSK input data at 1200 ±12 baud.

2. OSC1 at 3.579545 MHz ±0.1%.

3. Function of signal condition.

DCLK

DR/STD

Rise time t

Frequency f

DCLK0

DCLK to DR delay t

R

F

DCD

CDD

CH

CL

CRD

200 ns into 50pF Load

200 ns into 50pF Load
6 416 µs 1, 2, 3
6 416 µs 1, 2, 3

1201.6 1202.8 1204 Hz 2
415 416 417 µs2
415 416 417 µs2
415 416 417 µs2

18

Advance Information MT88E45

AC Electrical Characteristics† - 3-Wire Interface Timing (Mode 1)

Characteristics Sym Min Max Units Notes

1
2 Duty cycle 30 70 %

DCLK

3 Rise time t
4
5 DCLK low hold time after DR t

† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.

DCLK

DR/STD

Frequency f

DCLK low set up to DR t

DCLK1

R1

DDS

DDH

1 MHz

100 ns
500 ns
500 ns

AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels

Characteristics Sym Level Units Notes

1 CMOS Threshold Voltage V
2 Rise/Fall Threshold Voltage High V
3 Rise/Fall Threshold Voltage Low V

CT

HM

LM

0.5*V

0.7*V

0.3*V

DD
DD
DD

V
V
V

19

MT88E45 Advance Information

DAT A

DCLK

DR

t

DCD

t

R

t

CL

t

R

t

CDD

t

t

CH

Figure 10 - DATA and DCLK Mode 0 Output Timing

t

RF

t

RL

t

RR

V

HM

V

CT

V

F

t

F

V

HM

V

CT

V

LM

LM

V

HM

V

CT

V

LM

DCLK

Figure 11 - DR Output Timing

t

R1

Figure 12 - DCLK Mode 1 Input Timing

V

HM

V

LM

20

Advance Information MT88E45

TIP/RING
(A/B) WIRES

DATA
(Output)

DCLK
(Output)

DR
(Output)

start

start

start

b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5

stop

start

t

IDD

stop

start

stop

start

b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3b6

stop

t

CH

t

CL

stop

t

CRD

stop

1/f

DCLK0

t

RL

Figure 13 - Serial Data Interface Timing (Mode 0)

Demodulated Data
(Internal Signal)

DR (Data Ready)

Word N

7

stop

start

Note 1

1

0

Word N+1

234

(Output)

DDS

>t

DDH

1/f

DCLK1

>t

DCLK (Data Clock)
(Schmitt Input)

DAT A
(Output)

Word N-1

stop7

5

43210 6 7 stop

Word N

The DCLK input must be low before and after DR falling edge.
Note 1: DCLK occurs during DR low and returns DR to high.
Note 2: DCLK occurs after DR, so DR is low for half a nominal bit time.

Figure 14 - Serial Data Interface Timing (Mode 1)

5

67

t

RL

Note 2

stop

0

21

MT88E45 Advance Information

TIP/RING

PWDN

Note 1

OSC2

FSKen

Note 1

CD

DR

Note 5

1st Ring 2nd RingCh. seizure

ACDE

Note 2

t

PU

B

t

CP

Mark

Data

F

Note 2 Note 4

Note 3

t

PD

t

CA

A = 2sec typical

DCLK

B = 250-500ms
C = 250ms
D = 150ms

DATA

..101010..

Data

E = feature specific
Max C+D+E = 2.9 to 3.7sec
F ≥ 200ms

Figure 15 - Application Timing for Bellcore On-hook Data Transmission Associated with Ringing,

e.g., CID

Notes:
This on-hook case application is included because a CIDCW (off-hook) CPE should also be capable of receiving on-hook data
transmission (with ringing) from the end office.

1) PWDN and FSKen are internal signals decoded from CB0/1/2.

2) The CPE designer may choose to enable the MT88E45 only after the end of ringing to conserve power in a battery operated CPE.
CD is not activated by ringing.

3) The microcontroller in the CPE powers down the MT88E45 after CD has become inactive.

4) The microcontroller times out if CD is not activated.

5) This signal represents the mode of the DR/STD pin.

22

Advance Information MT88E45

TIP/RING

PWDN

Note 8

Hybrid CASen

Note 8

FSKen

Note 8

OSC2

EST

ST/GT

STD

Note 9

CD

DR

Note 9

DCLK

DATA

CPE goes off-hook

Note 1

Note 2

CAS ACK

AC EFG

t

PU

t

DP

t

GP

t

REC

Note 6

Note 7

CPE mutes handset & disables keypad

CPE sends

Note 5

Mark Data

BD

Note 3 Note 4

t

DA

t

GA

V

TGt

t

ABS

t

CP

Data

CPE unmutes handset
and enables keypad

t

CA

A = 75-85ms
B = 0-100ms
C = 55-65ms
D = 0-500ms
E = 58-75ms
F = feature specific
G ≤ 50ms

Notes:

Figure 16 - Application Timing for Bellcore Off-hook Data Transmission, e.g., CIDCW

1) In a CPE where AC power is not available, the designer may choose to switch over to line power when the CPE goes off-hook and
use battery power while on-hook. The CPE must also be CID (on-hook) capable because a CIDCW CPE includes CID functionality.

2) Non-FSK signals such as CAS, speech and DTMF tones are in the same frequency band as FSK. They will be demodulated and
give false data. Therefore the MT88E45 should be taken out of FSK mode when FSK is not expected.

3) The MT88E45 may be put into FSK mode as soon as the CPE has finished sending the acknowledgment signal ACK. TR-NWT­000575 specifies that ACK = DTMF ‘D’ for non-ADSI CPE, ‘A’ for ADSI CPE.

4) The MT88E45 should be taken out of FSK mode when CD has become inactive, or after 5 framing errors have been detected, or
after 150ms of continuous mark signal or space signal has been received. The framing errors need not be consecutive.

5) In an unsuccessful attempt where the end office does not send the FSK signal, the CPE should unmute the handset and enable the
keypad after interval D has expired.

6) The total recognition time is t
is the comparator threshold (refer to Figure 5 for details).

7) The total tone absent time is t
is the comparator threshold (refer to Figure 5 for details).

8) PWDN, Hybrid CASen and FSKen are internal signals decoded from CB0/1/2.

9) This signal represents the mode of the DR/STD pin.

= tGP + tDP, where tGP is the tone present guard time and tDP is the tone present detect time. V

REC

= tGA + tDA, where tGA is the tone absent guard time and tDA is the tone absent detect time. V

ABS

TGt

TGt

23

MT88E45 Advance Information

Line Reversal

‘Idle State Tone Alert Signal’

A/B Wires

PWDN

Note 6

DT-AS

AB C D E

Tip/Ring
CASen

Note 6

t

DP

EST

t

Note 1 Note 2

GP

ST/GT

t

REC

STD

Note 7

TE DC load

15±1ms

<120µA

20±5ms

TE AC load

Ch. seizure Mark

t

DA

t

GA

V

TGt

t

Note 3

ABS

< 0.5mA (optional)

Current wetting pulse (see SIN227)

Zss (Refer to SIN227)

Data

F

Ring

G

Note 4

50-150ms

Note 4

FSKen

Note 6

CD

t

CP

t

CA

Note 5

A ≥ 100ms
B = 88-110ms

DR

Note 7

DCLK

C ≥ 45ms (up to 5sec)
D = 80-262ms
E = 45-75ms
F ≤ 2.5sec (typ. 500ms)

DATA

OSC2

..101010..

t

PU

Data

t

PD

G > 200ms
Note: All values

obtained from SIN227
Issue 1

Figure 17 - Application Timing for BT Caller Display Service (CDS), e.g., CLIP

Notes:

1) The total recognition time is t
is the comparator threshold (refer to Figure 5 for details).

2) The total tone absent time is t
is the comparator threshold (refer to Figure 5 for details).

3) By choosing tGA=15ms, t
edge.

4) SIN227 specifies that the AC and DC loads should be removed between 50-150ms after the end of the FSK signal, indicated by CD
returning to high. The MT88E45 may also be powered down at this time.

5) The MT88E45 should be taken out of FSK mode when FSK is not expected to prevent the FSK demodulator from reacting to other
in-band signals such as speech, DT-AS/CAS and DTMF tones.

6) PWDN, Tip/Ring CASen, FSKen are internal signals decoded from CB0/1/2.

7) This signal represents the mode of the DR/STD pin.

= tGP + t

REC

= tGA + t

ABS

will be 15-25ms so that the current wetting pulse and AC load can be applied right after the STD rising

ABS

where tGP is the tone present guard time and tDP is the tone present detect time. V

DP ,

where tGA is the tone absent guard time and tDA is the tone absent detect time. V

DA ,

TGt

TGt

24

Advance Information MT88E45

A/B Wires

PWDN

Note 3

TE DC load

TE AC load

FSKen

Note 3

CD

DR

Note 4

DCLK

DATA

OSC2

Line Reversal (Optionally sent)

Ring Burst

ABCDEF

Note 1
250-400ms

t

PU

Ch. seizure

t

CP

..101010.. Data

Mark

Note 2
50-150ms

Data

First Complete
Ring Cycle

t

CA

A = 200-450ms
B ≥ 500ms
C = 80-262ms
D = 45-262ms
E ≤ 2.5s (typ. 500ms)
F >200ms
Note: Parameter F

t

PD

from "CCA Exceptions
Document Issue 3"

Notes:

Figure 18 - Application Timing for UK’s CCA Caller Display Service (CDS), e.g., CLIP

1) From TW/P&E/312. Start time: The CPE should enter the signalling state by applying the DC and AC terminations within this time
after the end of the ring burst.

2) End time: The CPE should leave the signalling state by removing the DC and AC terminations within this time after the end of Data,
indicated by CD returning to high. The MT88E45 should also be taken out of FSK mode at this time to prevent the FSK demodulator
from reacting to other in-band signals such as speech, and DTMF tones.

3) PWDN and FSKen are internal signals decoded from CB0/1/2.

4) This signal represents the mode of the DR/STD pin.

25

Pin 1

Package Outlines

E

A

A

1

16-Pin 18-Pin 20-Pin 24-Pin 28-Pin

DIM

Min Max Min Max Min Max

A 0.093

A

B 0.013

C 0.009

D 0.398

E 0.291

e 0.050 BSC

H 0.394

L 0.016

(2.35)

1

0.004

(0.10)

(0.33)

(0.231)

(10.1)

(7.40)

(1.27 BSC)

(10.00)

(0.40)

0.104

(2.65)

0.012

(0.30)

0.020

(0.51)

0.013

(0.318)

0.413

(10.5)

0.299

(7.40)

0.419

(10.65)

0.050

(1.27)

D

0.093
(2.35)

0.004
(0.10)

0.013
(0.33)

0.009

(0.231)

0.447

(11.35)

0.291
(7.40)

0.050 BSC
(1.27 BSC)

0.394

(10.00)

0.016
(0.40)

L

e

4 mils (lead coplanarity)

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

4) A & B Maximum dimensions include allowable mold flash

B

0.104

(2.65)

0.012
(0.30)

0.030
(0.51)

0.013

(0.318)

0.4625
(11.75)

0.299
(7.40)

0.419

(10.65)

0.050
(1.27)

0.093
(2.35)

0.004
(0.10)

0.013
(0.33)

0.009

(0.231)

0.496

(12.60)

0.291
(7.40)

0.050 BSC
(1.27 BSC)

0.394

(10.00)

0.016
(0.40)

0.104
(2.65)

0.012
(0.30)

0.020
(0.51)

0.013

(0.318)

0.512

(13.00)

0.299
(7.40)

0.419

(10.65)

0.050
(1.27)

Lead SOIC Package - S Suffix

C

H

L

Min Max Min Max

0.093
(2.35)

0.004
(0.10)

0.013
(0.33)

0.009

(0.231)

0.5985
(15.2)

0.291
(7.40)

0.050 BSC

(1.27 BSC)

0.394

(10.00)

0.016
(0.40)

0.104
(2.65)

0.012
(0.30)

0.020
(0.51)

0.013

(0.318)

0.614
(15.6)

0.299
(7.40)

0.419

(10.65)

0.050
(1.27)

0.093

(2.35)

0.004

(0.10)

0.013

(0.33)

0.009

(0.231)

0.697

(17.7)

0.291

(7.40)

0.050 BSC

(1.27 BSC)

0.394

(10.00)

0.016

(0.40)

(0.318)

0.7125

(10.65)

0.104
(2.65)

0.012
(0.30)

0.020
(0.51)

0.013

(18.1)

0.299
(7.40)

0.419

0.050
(1.27)

NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters.

2. Converted inch dimensions are not necessarily exact.

General-7

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